TWI650769B - Memory device and programming method for memory cell array - Google Patents

Abstract

A memory device and a stylized method of a memory cell array. The memory device includes a memory cell array, a selection switch, a column decoder, a voltage generator, and a memory controller. The memory controller controls the column decoder according to the input data to adjust the control path sequence of the address control signal, and the memory controller simultaneously controls the voltage generator to adjust the data path sequence of the input data signal, thereby The memory cells in the program are programmed.

Description

Stylized method of memory device and memory cell array

The present invention relates to a control technique for a memory device, and more particularly to a memory device and a memory cell array for reducing the time taken to perform a programmatic operation.

When the user writes the input data to the cache memory, the command, the memory cell address, and the input data to be accessed are input to the cache memory. Then, the internal circuit in the cache memory will program the specific memory cell according to these parameters, so as to write the input data into the specific memory cell. There are two main types of cache memory: NOR type cache memory and NAND type cache memory. Compared to NAND-type cache memory, NOR-type cache memory requires a long time for program/erase operation, but NOR-type cache memory can provide complete address and data bus, so it can be allowed. Access any memory cell on the NOR type cache.

If you want to speed up the programming of the NOR-type cache and shorten the time it takes for the stylization (usually called tPP), it seems that you can get a detailed flow of how to program the NOR-type cache. Make adjustments. The above stylized operations can usually be divided into two parts, the first part is a program pulse operation and a program verify (PV) operation. The stylized pulse operation applies a high voltage to the target memory cell to adjust the threshold voltage (Vt) of the target memory cell (eg, to increase the threshold voltage of the target memory cell). The stylized verification operation verifies that the target memory cell has reached a predetermined threshold voltage, thereby confirming that the target memory cell has actually stored the input data. Stylized pulse operations typically take up the time tPP of most stylized operations.

Since the stylized operation in the NOR type cache requires a large amount of current and is limited by the pumping Capability in the hardware circuit, the stylized pulse operation can only drive a certain number of data paths, resulting in multiple times. The stylized pulse operation is sequentially performed to completely write the input data. However, the data of the cache memory is written by first erasing all the memory cells, and then staging each memory cell, so it may not be necessary to program each memory cell. .

Therefore, how to reduce the time to reduce the stylized operation of the cache memory is one of the important issues.

The present invention provides a memory device and a memory cell array stylized method, which rearranges the data path sequence of the input data signal according to the content of the input data, and simultaneously rearranges the control path sequence of the address control signal, thereby skipping the The memory cells that need to be programmed to reduce the time it takes to perform stylized operations.

A memory device of the present invention includes a memory cell array, a selection switch, a column decoder, a voltage generator, and a memory controller. The memory cell array includes a plurality of memory cells. The selection switch is coupled to the memory cell array. The column decoder is coupled to the selection switch, and the column decoder receives the memory cell address to generate an address control signal. The voltage generator is coupled to the selection switch. The memory controller is coupled to the column decoder and the voltage generator. The memory controller obtains input data to control the voltage generator to generate an input data signal. The memory controller controls the column decoder according to the input data signal to adjust the control path sequence of the address control signal, and the memory controller simultaneously controls the voltage generator to adjust the data path sequence of the input data signal, thereby Stylize.

The stylized method of the memory cell array of the present invention comprises the steps of: obtaining input data to generate an input data signal; adjusting a control path sequence of the address control signal according to the input data, and simultaneously adjusting a data path sequence of the input data signal; And performing program operation on a part or all of the memory cells in the memory cell array according to the address control signal and the input data signal.

Based on the above, the memory controller in the memory device according to the embodiment of the present invention rearranges the conduction sequence of the control path in the selection switch according to the input data in the data buffer (that is, the control path of the address control signal) The sequence) and the data providing sequence of the data paths are simultaneously re-arranged (ie, the data path order of the input data signals), thereby collectively rearranging the bit lines provided to the memory cell array. Thereby, the memory cells that need to be programmed can be programmed, and the memory cells that do not need to be programmed can be skipped. As a result, the number of processing operations of the stylized operation in the memory device may be reduced, thereby reducing the time taken for the stylized operation.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1 is a block diagram of a memory device 100. The memory device 100 of the present embodiment may be a reverse (NOR) type cache memory. The components in Figure 1 are primarily used for program pulse (PGM-Pulse) operations on memory cells. The memory device 100 mainly includes a memory cell array 110, a selection switch 120, a column decoder 130, a voltage generator 140, and a control logic circuit 160. The memory device 100 also includes a row decoder 135 and a data buffer 150.

The memory cell array 110 includes a plurality of memory cells. The selection switch 120 is coupled to the memory cell array 110. The selection switch 120 of the present embodiment may be a column selection switch, and it is provided with a plurality of path switches (presented in the form of transistors M1, M2 in FIG. 1), and each path switch corresponds to each data path. Row decoder 135 receives memory cell address Adr to provide word line WL to memory array 110. The column decoder 130 is coupled to the selection switch 120. Column decoder 130 receives memory cell address Adr to generate an address control signal. In this embodiment, the symbols Y0 to Y3 are taken as an example of the address control signal. The voltage generator 140 is coupled to the selection switch 120 to provide an input profile signal for each of the path switches. This embodiment uses the symbols HVDIN0~HVDIN7 as an example of an input data signal. The voltage generator 140 can be implemented by a voltage boost circuit, which can also be referred to as a high voltage (HV) circuit.

The data buffer 150 is configured to receive and temporarily store the input data Data. The control logic circuit 160 controls the data buffer 150 and the voltage generator to generate the input data signals HVDIN0~HVDIN7 according to the externally supplied command CMD. In the embodiment of the present invention, the data buffer 150 can also receive and temporarily store the command CMD. The select switch 120 is controlled by the address control signals Y0~Y3 and the input data signals HVDIN0~HVDIN7 to provide the bit line BL to the memory array 110.

For convenience of description of the following embodiments, the present embodiment defines a "data path DP" as consisting of the following processes: (1) The input data Data is input to the memory device 100 and temporarily stored in the data buffer. 150; (2) the control logic circuit 160 sequentially transfers the input data Data temporarily stored in the data buffer 150 to the voltage generator 140 according to the instruction CMD; (3) the voltage generator 140 will be located in the logical domain (logic domain The input data Data is converted into an input data signal of a high voltage domain (eg, HVDIN0~HVDIN7), and the input data signal is supplied to the data input terminal of the selection switch 120; (4) the programized pulse is to be performed. The memory cells of the program are programmed to be biased according to the bit line BL generated by the input data signal. If you want to program a specific memory cell, the input data signal corresponding to a particular memory cell will be a high voltage signal, otherwise the corresponding input data signal will be 0 volts (V). In this embodiment, the "control path CP" is defined as being composed of the following processes: (1) the column decoder 130 obtains the memory cell address Adr; (2) the column decoder 130 pairs the memory cell address Adr The decoding is performed to control a portion of the path switches of the selection switch 120 to be turned on, thereby allowing the input data signals corresponding to the path switches to pass to reach a particular memory cell.

This explains how the stylized pulse program actually affects the overall time of the stylized operation. In a NOR type flash memory, the number of memory cells that can be simultaneously programmed can depend on the driving ability of the voltage generator 140 for current. Since the stylized operation of the memory cell will require a large amount of current to drive the memory cell, the voltage generator 140 cannot push a large number of memory cells at the same time due to its limited current driving capability. Therefore, the input logic Data is generally sequentially arranged by the control logic circuit 160 to perform the programmatic operation of the memory cells in a divided and partially provided manner. In other words, the control logic circuit 160 will arrange the data path sequence in the data path DP according to the data path scheme to determine the time taken for the stylization operation. The "pump capacity" described in this embodiment is the number of bits in which the voltage generator 140 simultaneously performs a programmatic pulse operation on the stylized memory cell.

2 is a detailed circuit diagram of some of the components of the memory device 100 of FIG. 1. Referring to FIG. 2, it is assumed that the memory cell array 110 has 32 memory cells to be programmed; the selection switch 120 has a plurality of data path groups 121-128 (eg, 8 data path groups), each data. A path group consists of multiple path switches (eg, 4 path switches). The number of bits of the address control signals Y0~Y3 (i.e., 4) is equal to the number of path switches in a single data path group (i.e., 4). The number of memory cells to be programmed in the memory cell array 110 (i.e., 32) is equal to the number of path switches in a single data path group (i.e., 4) multiplied by the number of data path groups (i.e., 8). The value. The number of data path groups 121-128 (i.e., 8) is greater than the pump capacity (i.e., 2).

In this embodiment, the number of bits that can be used for the stylized pulse operation of the stylized memory cell is two. That is, the voltage generator 140 has a pump capacity of two. For example, if you want to perform the first stylized pulse operation on the memory cell cA and the memory cell cB, you need to provide corresponding signals to the input data signals HVDIN0 and HVDIN1 (eg, if the memory cell needs to be programmed: input data signal) It is a high voltage signal; if the memory cell does not need to be programmed: the input data signal is 0V), and the specific path switch in the data path groups 121 and 122 is controlled to be turned on by the address control signal Y0, so that the input data signals HVDIN0 and HVDIN1 are input. The memory cells cA and cB are transferred to the memory cells cA and cB as shown by arrows 210 and 220 in FIG. In other words, if you want to complete a stylized pulse operation on a 32-bit memory cell, you will need 16 programmed pulses.

Table 1 shows the control path sequence and data path sequence for 16 stylized pulses for a 32-bit memory cell. The "control path sequence" is used to indicate the turn-on sequence of the address control signals for certain path switches; the "data path order" is used to indicate the input order of the input data signals. Table 1  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td></tr><tr><td> 1 </td><td> Y0 </td><td> HVDIN0/HDVIN1 </td></tr><tr><td> 2 </td><td> Y0 </td><td> HVDIN2/HDVIN3 </td></tr><tr><td> 3 </td><td> Y0 </td><td> HVDIN4 /HDVIN5 </td></tr><tr><td> 4 </td><td> Y0 </td><td> HVDIN6/HDVIN7 </td></tr><tr><td> 5 </td><td> Y1 </td><td> HVDIN0/HDVIN1 </td></tr><tr><td> 6 </td><td> Y1 </td><td> HVDIN2/ HDVIN3 </td></tr><tr><td> 7 </td><td> Y1 </td><td> HVDIN4/HDVIN5 </td></tr><tr><td> 8 < /td><td> Y1 </td><td> HVDIN6/HDVIN7 </td></tr><tr><td> 9 </td><td> Y2 </td><td> HVDIN0/HDVIN1 </td></tr><tr><td> 10 </td><td> Y2 </td><td> HVDIN2/HDVIN3 </td></tr><tr><td> 11 </ Td><td> Y2 </td><td> HVDIN4/HDVIN5 </td></tr><tr><td> 12 </td><td> Y2 </td><td> HVDIN6/HDVIN7 < /td></tr><tr><td> 13 </td><td> Y3 </td><td> HVDIN0/HDVIN1 </td></tr><tr><td> 14 </td ><td> Y3 </td><td> HVDIN2/HDVIN3 </td></tr><tr><td> 15 </td><td> Y3 </td><td> HVDIN4/HDVIN5 </td></tr><tr><td> 16 </td><td> Y3 </td><td> HVDIN6/HDVIN7 </td></tr ></TBODY></TABLE>

As can be seen from Table 1, the memory device 100 of FIG. 1 will perform a programmed pulse operation on the 32-bit memory cells one by one. In this data path scheme, the column decoder 130 and the control logic circuit 160 of FIG. 1 do not need to refer to the input data Data to adjust the control path sequence of the control path CP and the data path sequence of the data path DP, as long as the received data path is received. The memory cell address Adr and the order of the input data Data may be generated to generate a corresponding control path sequence and data path order.

However, the above data path scheme actually takes a lot of time, because many memory cells that do not need to be programmed are still programmed, as explained below. In the flash memory, the program for writing data is to first reset the memory cells in the entire flash memory device to logic "1" by erasing, and then program the memory cells to make some memory cells. The bit is modified to a logical "0". In other words, not every time you need to program a 32-bit memory cell.

For example, when the memory cell cA of FIG. 2 needs to be programmed, but the memory cell cB does not need to be programmed, the voltage generator 140 still performs the stylized pulse for the first time (that is, the number of programmed pulses is 1). The high voltage data is to be passed to the input data signal HVDIN0 and 0V is passed to the input data signal HVDIN1.

In addition, the diverse input data Data will affect the efficiency of the voltage generator 140 during operation. For example, in the data path scheme consistent with Table 1, it is not considered whether the bit arrangement in the input data Data really needs to be required for each memory cell to be supplied with current by the voltage generator 140 for a programmed pulse operation. Since the actual address of the memory cell has a specific mapping relationship with the logical address, and this mapping relationship will be described in the following embodiments, here actually corresponds to the actual address B0 and B1 of the memory cell. The bit values in the logical addresses D00 and D08 are taken as an example. When both bit values of the logical address of the input data Data D00 and D08 are logic "1", the usage rate of the voltage generator 140 is zero because no high voltage signal is required. When the logical address of the input data Data is that one of the bit values D00 and D084 is a logical "0" and the other bit value is a logical "1", the usage rate of the voltage generator 140 is 50%. The usage rate of the voltage generator 140 is 100% only when the bit values of the logical addresses D00 and D08 in the input data Data are all logic "0". In other words, when the usage rate of the voltage generator 140 is not 100%, it is actually a waste of time for the stylized pulse operation.

FIG. 3 is a block diagram showing a memory device 300 in accordance with an embodiment of the invention. The main difference between FIG. 1 and FIG. 3 is that the control logic circuit 160 of FIG. 1 is replaced by the memory controller 360 of FIG. The memory controller 360 of FIG. 3 is coupled to the column decoder 130 in addition to the data buffer 150 and the voltage generator 140. The memory controller 360 of this embodiment can directly read the input data Data and the command CMD, and can also read the required input data Data from the data buffer 150. In other words, the memory controller 360 and the data buffer 150 can be bidirectionally coupled to enable the memory controller 360 to control the data buffer 150 for reading and temporarily storing the input data 150. The memory controller 360 of FIG. 3 controls the column decoder 130 according to the input data Data to adjust the control path sequence of the address control signals Y0~Y3, and the memory controller 360 simultaneously controls the voltage generator to adjust according to the input data Data. The data path sequence of the data signals HDVIN0~HDVIN7 is input to program the memory cells in the memory cell array 110. The memory controller 360 can be implemented by a control unit such as a logic circuit, a microprocessor, or the like.

Comparing the memory device 100 of FIG. 1 with the memory device 300 of FIG. 3, the control logic circuit 160 of FIG. 1 can only control the data path DP. In contrast, the memory controller 360 of FIG. 3 can simultaneously control the data path DP and the control path CP according to the bit data of the input data Data to rearrange the data path sequence and control the content in the path sequence. Thereby, the memory cells that need to be programmed can be programmed, and the memory cells that do not need to be programmed can be skipped. As a result, the number of processing operations of the stylized operation in the memory device 300 may be reduced, thereby reducing the time taken for the stylized operation. The related embodiments in accordance with the spirit of the present invention will be described below, and the application in the related embodiments can be adjusted according to the needs of the embodiment.

Here, the mapping relationship between the actual address of the memory cell and the logical address is described. 4 is an enantiomorphic relationship diagram between the actual address Bit00~Bit32 of the memory cell and the logical address D00~D31. As shown in FIG. 4, based on the application of the cache memory device, the actual address of the memory cell is different from the logical address of the memory cell, because access to the memory cell in order will result in access. The speed is too slow. Therefore, in this embodiment, the memory cells to be programmed (and the 32-bit memory cells) are based on the number of data path groups 121-128 (eg, 8) and the physical addresses of the memory cells to be programmed, Bit00~Bit32. It is divided into a plurality of memory cell groups (for example, 8 memory groups G1 to G8). Each of the memory cell groups G1 to G8 corresponds to each of the data path groups 121 to 128. The mapping between the physical address and the logical address of the stylized memory cell is that the physical address of the jth memory cell in the i-th memory cell group is [(i-1)×4+( J-1)], the logical address of the jth memory cell in the i-th memory cell group is [(j-1)×8+(i-1)], where i and j are positive integers, i It is less than or equal to the number of data path groups 121~128 (ie, 8), and j is less than or equal to the number of path switches in a single data path group (ie, 4). For example, the physical address of the first memory cell in the first memory cell group is Bit00 ("0x8+0"), and the logical address thereof is D00 ("0x8+0"); The physical address of the first memory cell in the three memory cell groups is Bit08 ("2×4+0"), and the logical address is D02 ("0×8+2"); the fifth memory The physical address of the third memory cell in the cell group is Bit18 ("4x4+2"), and its logical address is D20 ("2x8+4"). The logical addresses D00~D31 of the memory cells in the memory cell group G1~G8 will be the same as the logical address of the input data DAata.

Here, the data path scheme used by the memory controller 360 of FIG. 3 will be described with reference to FIG. 5 to implement the programd pulse operation described in the embodiment of the present invention. FIG. 5 is a flow chart illustrating a stylized method of a memory cell array in accordance with an embodiment of the invention. Here, the input data Data[31:0] is equal to (1111-1110-1111-1100-1111-0010-1111-1100) as an example. For example, the values of the bits Data[0], Data[8], Data[16], Data[24], Data[1], Data[17], Data[10], and Data[11] are all logical "0" ", the remaining bits of the input data Data are logical "1". In addition, it is explained here that the logical address of Data[0] is D00; the logical address of the bit Data[1] is D01, and so on.

Referring to FIG. 3 and FIG. 5 simultaneously, in step S510, the memory controller 360 performs initialization, and sets the first memory cell group G1 to be the memory cell group to be searched in the following steps. That is, the memory controller 360 sets i to 1 (i = 1) to indicate the first memory group G1.

Then, the memory controller 360 sequentially searches for whether the at least one first bit corresponding to the logical address of the memory cell of the memory cell group in the input data Data is a specific value to be programmed. For example, in step S520, since the memory cell group to be searched is set as the first memory cell group G1 in advance in step S510, the logic of the memory cell of the memory cell group G1 in the input data Data is calculated by the memory controller 360. Whether the bit corresponding to the address (ie, logical addresses D00, D08, D16, and D24) (ie, Data[0], Data[8], Data[16], and Data[24]) is required A specific value for a stylized operation (for example, a logical "0"). In step S530, the memory controller 360 determines the bits Data[0], Data[8] of the input data Data corresponding to the logical addresses D00, D08, D16 and D24 of the memory cells in the memory cell group G1, Whether Data[16] and Data[24] are not specific values. If the memory controller 360 stores the bit data Data[0], Data[8], Data[16] of the input data corresponding to the logical addresses D00, D08, D16 and D24 of the memory cell in the memory cell group G1. When Data[24] is logical "1" non-logic "0", then the process proceeds from step S530 to step S532, and the memory controller 360 determines whether the memory cell group is the last memory group G8. That is, the memory controller 360 determines whether i is 8. When the memory cell group is not the last memory group, the process proceeds from step S532 to step S534, the value i indicating the memory group is incremented by 1 (i.e., i++1) and proceeds to step S520 again to The bit of the input data Data mapped from the logical address of the memory cell (ie, logical addresses D01, D09, D17, and D25) from the next memory group (eg, the second memory group G2) Yuan to determine whether a specific value (logical "0") for stylized operations is required.

If the memory controller 360 has determined the specificity from at least one first bit corresponding to the logical addresses D00, D08, D16, and D24 of the memory cells of the specific memory cell group (eg, the first memory cell group G1) When the value (logic "0"), for example, the bit Data[0] is equal to the logic "0", the process proceeds from step S530 to step S540, the memory controller 360 counts the number of the first bit, and judges the input data. Whether the number of first bits in Data reaches the pump capacity of the voltage generator (ie, 2). In this embodiment, since the bits Data[0] and Data[8] corresponding to the logical addresses D00 and D08 are all logical "0", the bits Data[0] and Data[8] belong to the first One yuan and make the number of "first digits" reach 2.

When the number of the first bit in the input data Data reaches the pump capacity (2), the process proceeds from step S540 to step S560, and the memory controller 360 determines the specific data path group corresponding to the specific memory cell group G1. 121, the input data signal HVDIN0 is set, and the address control signal is set according to the logical addresses D0 and D8 corresponding to the first bit (that is, the bits Data[0] and Data[8]) of the input data Data. Y0, Y1. The logical addresses D00 and D08 correspond to the address control signals Y0 and Y1, respectively. The logical addresses D00 and D08 correspond to the actual addresses Bit00 and Bit01 of the memory cell, respectively. The number of stylized pulses, control path sequence, and data path sequence at this time are shown in Table 2. Table 2  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td><td> Actual address of the memory cell to be programmed</td></tr><tr><td> 1 </td><td> Y0/Y1 </td><td > HVDIN0 </td><td> Bit00/Bit01 </td></tr></TBODY></TABLE>

In step S570, the memory controller 360 controls the column decoder 130 to adjust according to the input data signal HVDIN0 set in the data corresponding to the pulse number 1 in Table 2 and the set address control signal Y0/Y1. The control path sequence of the address control signals, and the memory controller 360 simultaneously controls the voltage generator 140 to adjust the data path sequence of the input data signals to program the corresponding memory cells. After step S570 is executed, the process returns to step S520 to continue the stylization operation of the subsequent memory cells.

In this embodiment, since the bits Data[16] and Data[24] of the input data Data located in the same memory cell group G1 are also logical "0", the same as steps S520, S530, S540, and S560 described above. In the step flow of S570, the memory cells corresponding to the specific data path group G1 and the logical addresses D16 and D24 are programmed according to the set input data signal and the set address control signal. The logical addresses D16 and D24 correspond to the actual addresses Bit02 and Bit03 of the memory cell, respectively. Table 2 above also adds a column of data corresponding to pulse number 2, which is presented in Table 3 below: Table 3  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td><td> Actual address of the memory cell to be programmed</td></tr><tr><td> 1 </td><td> Y0/Y1 </td><td > HVDIN0 </td><td> Bit00/Bit01 </td></tr><tr><td> 2 </td><td> Y2/Y3 </td><td> HVDIN0 </td>< Td> Bit02/Bit03 </td></tr></TBODY></TABLE>

Returning from step S570 to step S520, since each of the memory cells in the memory cell group G1 has completed the stylized pulse operation, the memory controller 360 is in the input data Data by the next memory cell group (ie, the second Bits corresponding to the logical addresses of the memory cells of the memory cell group G2) (ie, logical addresses D01, D09, D17, and D25) (ie, Data[1], Data[9], Data[ 17] and Data[25]) are specific values that need to be stylized (for example, logic "0").

Since the memory controller 360 in the memory cell group G2, the logical data addresses D01 and D17 of the memory cell correspond to the input data Data bits Data[1], Data[17] are all logical "0", so the step is S520 proceeds to step S540 via step S530, and the memory controller 360 counts the number of first bits (bits Data[1] and Data[17]) to 2 . Then, from step S540 to step S570 via step S560, the memory controller 360 sets the input data signal HVDIN1 according to the specific data path group 122 corresponding to the specific memory cell group G2, and simultaneously according to the input data Data. The address addresses control signals Y0, Y3 are set by the logical addresses D01 and D17 corresponding to one bit (i.e., the bits Data[1] and Data[17]). The logical addresses D01 and D17 correspond to the address control signals Y0 and Y3, respectively. Then, the memory controller 360 performs a program operation on the memory cells corresponding to the specific data path group G2 and the logical addresses D01 and D17 according to a column of data corresponding to the pulse number 3 in Table 4 below. The logical addresses D01 and D17 correspond to the actual addresses Bit04 and Bit06 of the memory cell, respectively. Table 4  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td><td> Actual address of the memory cell to be programmed</td></tr><tr><td> 1 </td><td> Y0/Y1 </td><td > HVDIN0 </td><td> Bit00/Bit01 </td></tr><tr><td> 2 </td><td> Y2/Y3 </td><td> HVDIN0 </td>< Td> Bit02/Bit03 </td></tr><tr><td> 3 </td><td> Y0/Y2 </td><td> HVDIN1 </td><td> Bit04/Bit06 </ Td></tr></TBODY></TABLE>

Returning to step S520, the memory controller 360 is in the input data Data by the logical address of the memory cell of the memory cell group G2 (ie, the logical address D25) (ie, Data[25] Whether it is a specific value that needs to be stylized (for example, logic "0"). Since the bit Data[25] is not logical "0" and the bit of the input data Data corresponding to the memory cell group G2 has been searched, the process proceeds from step S530 to step S532 to proceed to S534, and the memory controller 360 will The value i indicating the group of memories is incremented by 1 (i.e., i = 3) and returns to step S520.

The memory controller 360 is in the input data Data by the logical address of the memory cell of the memory cell group G3 (ie, logical addresses D2, D10, D18, and D26) (ie, Data[2] ], Data[10], Data[18], and Data[26]) are specific values (logical "0"). Since only the bit Data[10] in the bits Data[2], Data[10], Data[18], and Data[26] is logic "0", the process proceeds from step S530 to step S540, and the memory controller 360 counts The number of the first bit is determined, and it is judged whether the number of the first bit in the input data Data reaches the pump capacity of the voltage generator (that is, 2). In this embodiment, only the bit Data[10] corresponding to the logical address in the cell group G3 is "first bit". Therefore, when the number of the first bit in the input data Data does not reach the pump capacity (2), the process proceeds from step S540 to step S550, and the memory controller 360 proceeds from the subsequent other memory cell groups (eg, memory). Whether the cell group G4~G8) has the same address control signal Y1 as the first bit (ie, Data[10]) in the specific memory cell group (ie, the memory cell group G3) The second bit. In this embodiment, the address control signal corresponding to the bit Data[10] is Y1, so the memory controller 360 searches for the bit with the same address control signal Y1 in the memory cell group G4~G8. The element, and this bit needs to be a specific value (logical "0"), thereby finding the bit Data[11] in the memory cell group G4.

When the memory controller 360 finds the second bit (ie, the bit Data[11]) from the other memory cell group G4, the process proceeds from step S550 to step S562, and the memory controller 360 will The two bits are recorded to prevent subsequent stylized pulse operations from repeating the second bit again. Then, proceeding from step S652 to step S565, the memory controller 360 sets the input data signal according to the specific data path group 123 corresponding to the specific memory cell group G3 and other data path groups 124 corresponding to the other memory cell group G4. HVDIN2 and HVDIN3, and the address control signal Y1 is set according to the logical address D10 corresponding to the first bit (that is, the bit Data[10]) in the input data Data. The reason why only a single address control signal Y1 is set is that the address control signals corresponding to the bit Data[10] and the bit Data[11] are both Y1. In other words, the bit Data[10] shares the address control signal Y1 with the bit Data[11].

The number of programmed pulses, control path sequence, and data path sequence at this time are shown in Table 5. table 5  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td><td> Actual address of the memory cell to be programmed</td></tr><tr><td> 1 </td><td> Y0/Y1 </td><td > HVDIN0 </td><td> Bit00/Bit01 </td></tr><tr><td> 2 </td><td> Y2/Y3 </td><td> HVDIN0 </td>< Td> Bit02/Bit03 </td></tr><tr><td> 3 </td><td> Y0/Y2 </td><td> HVDIN1 </td><td> Bit04/Bit06 </ Td></tr><tr><td> 4 </td><td> Y1 </td><td> HVDIN2/3 </td><td> Bit09/Bit13 </td></tr>< /TBODY></TABLE>

In step S570, the memory controller 360 pairs the corresponding input data signal HVDIN2/HVDIN3 and the set address control signal Y1 according to the pulse number 4 corresponding to the pulse number 4 in Table 5 to the corresponding memory cell (actual bit). Stylized pulse operation at Bit09/Bit13).

Returning to step S520, since the bits of the input data Data corresponding to the logical addresses in the memory groups G5 to G8 are all logic "1", the corresponding memory cells of the bits do not need to be programmed. Operation, therefore, will proceed to step S530, step S532 to step S590 to end the stylized operation of the memory cell array 110.

The above embodiment does not explain the case where the second bit is not found in step S550, which will be described below. It is assumed here that the value of the bit Data[11] is a logical "1" instead of the logical "0" described in the previous embodiment. When the bit Data[10] of the input data Data corresponding to the memory cell group G3 has been found and has proceeded to step S550, the memory controller 360 proceeds from the subsequent other memory cell groups (eg, the memory cell group G4). ~G8) looking for the second bit of the same address control signal Y1 as the first bit (ie, Data[10]) in the specific memory cell group (ie, the memory cell group G3) yuan. However, since the bits of the input data Data corresponding to the logical addresses in the memory cell groups G4 to G8 are all logic "1", the second bit is not found. Therefore, proceeding from step S550 to step S560, the memory controller 360 sets the input data signal HVDIN2 according to the specific data path group 123 corresponding to the specific memory cell group G3, and according to the first bit in the input data Data (also That is, the logical address D10 corresponding to the bit Data[10]) sets the address control signal Y1.

The number of stylized pulses, control path sequence, and data path sequence at this time are shown in Table 6. Table 6  <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Stylized pulse times</td><td> Control path order</td><td> Data path order</td><td> Actual address of the memory cell to be programmed</td></tr><tr><td> 1 </td><td> Y0/Y1 </td><td > HVDIN0 </td><td> Bit00/Bit01 </td></tr><tr><td> 2 </td><td> Y2/Y3 </td><td> HVDIN0 </td>< Td> Bit02/Bit03 </td></tr><tr><td> 3 </td><td> Y0/Y2 </td><td> HVDIN1 </td><td> Bit04/Bit06 </ Td></tr><tr><td> 4 </td><td> Y1 </td><td> HVDIN2 </td><td> Bit09 </td></tr></TBODY>< /TABLE>

In step S570, the memory controller 360 compares the data corresponding to the specific data path group G3 and the logical address D10 (corresponding to the first bit Data[10]) according to the data corresponding to the pulse number 4 in Table 6. The cell (actual address Bit09) performs a programmatic pulse operation.

As can be seen from the above embodiments, the embodiment of the present invention can implement a stylized pulse operation on the memory to be programmed in the memory cell array 110 by a small number of stylized pulses, for example, from the memory device 100 of FIG. The required 16 programmed pulses are reduced to the four programmed pulses required by the memory device 300 of Figure 3 in Table 5 or Table 6, thereby maximizing the usage of the voltage generator 140 of Figure 3.

In summary, the memory controller in the memory device according to the embodiment of the present invention re-arranges the turn-on sequence of the data path according to the input data in the data buffer (that is, the control path sequence of the address control signal) And the order in which the data of the data path is re-arranged at the same time (ie, the order of the data paths of the input data signals). Thereby, the memory cells that need to be programmed can be programmed, and the memory cells that do not need to be programmed can be skipped. As a result, the number of processing operations of the stylized operation in the memory device may be reduced, thereby reducing the time taken for the stylized operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 300‧‧‧ memory devices

110‧‧‧ memory cell array

120‧‧‧Selection switch

121~128‧‧‧data path group

130‧‧‧ column decoder

135‧‧ ‧ row decoder

140‧‧‧Voltage generator

150‧‧‧ data buffer

160‧‧‧Control logic

210, 220‧‧‧ arrows

360‧‧‧ memory controller

S510~S590‧‧‧Steps

Adr‧‧‧ memory cell address

Data‧‧‧ Input data

Y0~Y3‧‧‧ address control signal

HVDIN0~HVDIN7‧‧‧ input data signal

M1, M2‧‧‧ transistor

CP‧‧‧ control path

DP‧‧‧ data path

cA, cB‧‧‧ memory cells

Bit00~Bit31‧‧‧The actual address of the memory cell

D00~D31‧‧‧ logical address of memory cell

CMD‧‧ directive

WL‧‧‧ character line

BL‧‧‧ bit line

1 is a block diagram of a memory device. Figure 2 is a detailed circuit diagram of some of the components of the memory device of Figure 1. 3 is a block diagram showing a memory device in accordance with an embodiment of the invention. 4 is an enantiomorphic relationship diagram between the actual address Bit00~Bit32 of the memory cell and the logical address D00~D31. FIG. 5 is a flow chart illustrating a stylized method of a memory cell array in accordance with an embodiment of the invention.

Claims (14)

A memory device includes: a memory cell array including a plurality of memory cells; a selection switch coupled to the memory cell array to provide a bit line to the memory array; and a first decoder coupled to the selection switch, Receiving a memory cell address to generate an address control signal; a second decoder coupled to the memory cell array, receiving the memory cell address to provide a word line to the memory array; and a voltage generator coupled to the a selection switch; and a memory controller coupled to the first decoder and the voltage generator, the memory controller obtaining input data to control the voltage generator to generate an input data signal, wherein The memory controller controls the first decoder to adjust a control path sequence of the address control signal according to the input data, and the memory controller simultaneously controls the voltage generator to adjust the input data The data path sequence of the signals to program the memory cells. The memory device of claim 1, wherein the selection switch comprises a plurality of data path groups, each data path group being composed of a plurality of path switches, the bit of the address control signal The number is equal to the number of the path switches in a single data path group, and the number of memory cells to be programmed in the memory cell array The amount is equal to the number of the path switches in a single data path group multiplied by the number of the data path groups. The memory device of claim 2, wherein the to-be-programmed memory cell is divided into a plurality of memories according to the number of the data path groups and the physical address of the to-be-programmed memory cell. a group of cells corresponding to the data path group, wherein an mapping relationship between a physical address and a logical address of the memory cell to be programmed is, in the i-th memory cell group The physical address of the jth memory cell is [(i-1)×4+(j-1)], and the logical address of the jth memory cell in the i-th memory cell group is [(j- 1) × 8+(i-1)], where i and j are positive integers, i is less than or equal to the number of data path groups, and j is less than or equal to the number of the path switches in a single data path group, The logical address of the memory cell in the memory cell group is the same as the logical address of the input data. The memory device of claim 2, wherein the memory controller sequentially searches for the logical address corresponding to the memory cell of the memory cell group in the input data. Whether at least a first bit is a specific value to be programmed, and at least one first bit corresponding to the logical address of the memory cell of the specific memory cell group is the specific value The memory controller counts the number of the at least one first bit, when the number of the at least one first bit in the input data reaches the pump capacity of the voltage generator, The memory controller is based on the specific memory cell Setting the input data signal according to the specific data path group corresponding to the group, and setting the address control signal according to the logical address corresponding to the at least one first bit in the input data, thereby The specific data path group and the memory cell corresponding to the logical address are programmed. The memory device of claim 4, wherein when the number of the at least one first bit in the input data does not reach the pump capacity of the voltage generator, the memory The body controller searches for a second bit from the other memory cell group having the same address control signal as the at least one first bit in the specific memory cell group, when the memory control When the device finds the second bit from the other memory cell group, the memory controller is configured according to the specific data path group corresponding to the specific memory cell group and the other memory cells The other data path group corresponding to the group sets the input data signal, and sets the address control signal according to the logical address corresponding to the at least one first bit in the input data, thereby The specific data path group, the other data path group, and the memory cell corresponding to the logical address are programmed. The memory device of claim 4, wherein when the second bit is not found from the other memory cell group, the memory controller is configured according to the specific memory cell group Corresponding specific data path group setting the input data signal, and setting the address control signal according to the logical address corresponding to the at least one first bit in the input data, thereby Specific information The path group and the memory cell corresponding to the logical address are programmed. The memory device of claim 4, wherein the at least one first bit corresponding to the logical address of the memory cell of the memory cell group in the input data is When not the particular value, the memory controller ends the stylized operation of the memory cell array. A stylized method for a memory cell array, comprising: obtaining input data; adjusting a control path sequence of an address control signal according to the input data, and simultaneously adjusting a data path sequence of the input data signal to provide a bit line to the memory And arranging a portion or all of the plurality of memory cells in the array of memory cells according to the address control signal and the input data signal. The program method of claim 8, wherein the address control signal is used to control a plurality of data path groups, each data path group being composed of a plurality of path switches, the address control The number of bits of the signal is equal to the number of the path switches in the group of individual data paths, the number of cells to be programmed in the array of memory cells being equal to the number of the path switches in the group of individual data paths multiplied by The value of the number of data path groups. The stylized method of claim 9, further comprising: dividing the to-be-programmed memory cell into two according to the number of the data path groups and the physical address of the to-be-programmed memory cell a plurality of memory cell groups, said The memory cell group respectively corresponds to the data path group, wherein the relationship between the physical address and the logical address of the programized memory cell is the entity of the jth memory cell in the i-th memory cell group The address is [(i-1)×4+(j-1)], and the logical address of the jth memory cell in the i-th memory cell group is [(j-1)×8+(i- 1)], wherein i and j are positive integers, i is less than or equal to the number of the data path groups, and j is less than or equal to the number of the path switches in a single data path group, wherein the memory cell group The logical address of the memory cell is the same as the logical address of the input data. For example, in the stylized method of claim 10, adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal includes the following steps: Searching for whether the at least one first bit corresponding to the logical address of the memory cell of the memory cell group in the input data is a specific value to be programmed; when by a specific memory cell Counting the number of the at least one first bit when at least one first bit corresponding to the logical address of the memory cell of the group is the specific value; and when the input data is in the When the number of the at least one first bit reaches the pump capacity of the voltage generator for generating the input data signal, the input data signal is set according to the specific data path group corresponding to the specific memory cell group. And setting the address control signal according to a logical address corresponding to the at least one first bit in the input data. For example, in the stylized method of claim 11, adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal further includes the following steps: When the number of the at least one first bit in the input data does not reach the pump capacity of the voltage generator, the memory controller searches for other memory cells to find out whether there is any At least one first bit in the particular group of memory cells having the same second bit of the address control signal; and when the memory controller finds the same from the other group of memory cells In the second bit, the input data signal is set according to the specific data path group corresponding to the specific memory cell group and other data path groups corresponding to the other memory cell group, and The address control signal is set by a logical address corresponding to the at least one first bit in the input data. According to the stylized method of claim 12, adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal further includes the following steps: When the second bit is not found in the other memory cell group, the input data signal is set according to the specific data path group corresponding to the specific memory cell group, and according to the input data. The logical address corresponding to the at least one first bit sets the address control signal. According to the stylized method of claim 12, adjusting the control path sequence of the address control signal according to the input data, and simultaneously adjusting the data path sequence of the input data signal further includes the following steps: Ending the memory cell array when the at least one first bit corresponding to the logical address of the memory cell of the memory cell group is not the specific value in the input data Stylized operation.