TWI550682B - Memory device and method for fabricating the same - Google Patents

Description

Memory element and manufacturing method thereof 【0001】

 The present disclosure relates to a non-volatile memory element and a method of fabricating the same. In particular, there is a three-dimensional (3D) non-volatile memory element and a method of fabricating the same.

【0002】

 Conventional non-volatile memory components, such as NAND flash memory components, typically use a single-layer germanium or polysilicon conductive stripe to be placed in series between the bit line and the source line. Multiple memory cells between. In order to reduce the series resistance between the memory cells, the single crystal germanium or polycrystalline germanium conductive strips between the serial memory cells are usually ion implant doped. However, when fabricating a NAND flash memory device having a three-dimensional multilayer memory array, since the polysilicon or single crystal epitaxial conductive strip is stacked with a plurality of dielectric layers to form a multi-layer structure, the memory cells are located in a multi-layer stack. The vertical surface of the structure; the implantation of ion dopants in the polycrystalline germanium conductive strip between the memory cells not only complicates the process steps, increases the thermal budget of the process, and is difficult to control the diffusion of the ion dopant. It is easy to interfere with the reading, stylization and program/erase of the memory components, which leads to component failure.

[0003]

 Therefore, there is a need to provide a more advanced memory component and method of making the same to improve the problems faced by conventional techniques.

[0004]

 According to an embodiment of the present specification, a memory device is provided, comprising: a first conductive strip, a first memory layer, a first conductive pillar, a first dielectric layer, and a first conductive plug. The first conductive strip extends in the first direction. The first memory layer extends in the second direction and overlaps the first conductive strip, and the first memory area is defined where the first memory layer overlaps the first conductive strip. The first conductive column extends in the second direction and abuts the first memory layer and overlaps the first memory region. The first dielectric layer extends in the second direction and abuts the first conductive strip, the first memory layer, and the first conductive pillar. The first conductive plug extends in the second direction and at least partially overlaps the first conductive strip, and is connected to the first conductive strip, the first memory layer and the first conductive column by the first dielectric layer Electrically isolated.

[0005]

 According to another embodiment of the present specification, a method of fabricating a memory device is provided, comprising the steps of first forming a multi-layer stack structure on a surface of a substrate. The multilayer stack structure is repatterned to form a plurality of ridge-shaped stacks such that each ridge multilayer stack includes at least one conductive strip extending in a first direction. A layer of memory material is then formed on the bottom and sidewalls of at least one of the trenches between the ridged multilayer stacks. A layer of conductive material is then formed over the ridged multilayer stack and fills the trench. Next, the conductive material layer and the memory material layer are patterned to form a plurality of via holes in the trenches to expose a portion of the substrate and the conductive strips. Wherein the patterned memory material layer comprises at least one memory layer in the trench; the patterned conductive material layer comprises at least one conductive pillar in the trench, and the memory layer is defined at the overlap of the conductive strip Out of a memory area. Thereafter, a dielectric layer is formed on the sidewalls of the via and the substrate exposed to the outside. A plurality of conductive plugs are formed to partially fill the vias, respectively, and the conductive plugs are at least partially overlapped with the conductive strips. Subsequently, a plurality of dielectric plugs are formed on the conductive plugs to fill the through holes. Then, the conductive material layer is patterned again to form at least one word line on the top of the ridge multilayer laminate, extending in the third direction, and in electrical contact with the conductive column.

[0006]

 According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The stereo memory element includes at least a plurality of levels; each of the levels includes a plurality of memory cells and is connected in series by conductive strips extending in a first direction. Each of the memory cells includes a memory layer and a conductive column extending in the second direction. Wherein, the memory layer is adjacent to the conductive strip, and a memory area is defined at a position overlapping the conductive strip. The conductive column is adjacent to the memory layer and overlaps the memory region. a conductive plug having a parallel conductive column between the adjacent conductive cells of the two memory cells, at least partially overlapping the conductive strips connected in series with the two memory cells, and the conductive plugs are respectively separated by the dielectric layer The adjacent two memory cells and the conductive strip are electrically isolated.

【0007】

 Due to the arrangement of the conductive plug and the dielectric layer, the conductive plug has the function of a floating gate. When the three-dimensional memory component is operated, the conductive plug has an induced voltage due to the conduction of the conductive column, and Forming an inversion layer in the conductive strips of two adjacent memory cells in series helps to reduce the series resistance between the two memory cells. Therefore, it is not necessary to perform ion implantation doping on the conductive strips of the adjacent two memory cells in series, thereby reducing the series resistance between the memory cells. At the same time, the conventional technology can solve the problems of complicated process steps, increased thermal budget, and interference with reading, stylization and erasing of memory components due to the ion implantation doping process.

[0035]

100: Stereo memory component
101: substrate
102: through hole
103: Memory layer
104: conductive columnar body
105: Conductive strip
106: Memory area
108: conductive plug
109: Dielectric plug
110: Multi-layer stack structure
110a: groove
110b: ridge multilayer laminate
110c: sidewall of the trench
111-118: Conductive layer
121-128: Insulation
130: patterned hard mask layer
130a: groove opening
140: memory material layer
150: conductive material layer
160: dielectric layer
170: word line
180a-180f: memory cell
S51, S52, S61 S62, S71, S72, S81, S82, S91 and S92: tangent
D1: distance

[0008]

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.
1A is a perspective view showing the structure of a multilayer stacked structure according to an embodiment of the present invention;
1B is a structural top view of the multilayer stack structure according to FIG. 1A;
2A is a perspective view showing the structure after the patterning process of the multilayer stacked structure of FIG. 1A;
2B is a top view of the structure according to FIG. 2A;
3A is a perspective view showing the structure after forming a memory material layer and a conductive material layer on the structure of FIG. 2A in sequence;
Figure 3B is a top view of the structure according to Figure 3A;
4A is a structural top view after patterning the conductive material layer and the memory material layer of FIG. 3B;
Figure 4B is a partial structural perspective view taken along line S41 of Figure 4A;
Figure 4C is a partial structural perspective view taken along line S42 of Figure 4A;
5A is a top view of the structure after forming a dielectric layer in the structure of FIG. 4B;
Figure 5B is a partial structural perspective view taken along line S51 of Figure 5A;
Figure 5C is a partial structural perspective view taken along line S52 of Figure 5A;
6A is a top view of the structure after forming a plurality of conductive plugs in the structure of FIG. 5A;
Figure 6B is a partial structural perspective view taken along line S61 of Figure 6A;
Figure 6C is a partial structural perspective view taken along line S62 of Figure 6A;
Figure 7A is a top view showing the structure after forming a plurality of dielectric plugs in the structure of Figure 6A;
Figure 7B is a partial structural perspective view taken along line S71 of Figure 7A;
Figure 7C is a partial structural perspective view taken along line S72 of Figure 7A;
8A is a top view of the structure after forming a plurality of word lines in the structure of FIG. 7A;
Figure 8B is a partial structural perspective view taken along line S81 of Figure 8A;
Figure 8C is a partial structural perspective view taken along line S82 of Figure 8A;
Figure 9 is a schematic cross-sectional view showing a partial hierarchical structure along the XY cross section of the three-dimensional memory element.

【0009】

 The invention provides a three-dimensional memory component and a manufacturing method thereof, which can reduce the series resistance between memory cells without ion implantation doping of the conductive strips of two adjacent memory cells in series. The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

[0010]

 However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

[0011]

 A method of fabricating the stereoscopic memory element 100 includes the steps of first forming a multi-layer stack 110 on the surface of the substrate 101. Referring to FIGS. 1A and 1B, FIG. 1A is a perspective view showing the structure of a multilayer stack structure 110 according to an embodiment of the present invention. FIG. 1B is a structural top view of the multilayer stack structure 110 according to FIG. 1A. In some embodiments of the invention, a multilayer stack structure 110 is formed on a substrate 101. The multilayer stack structure 110 includes a plurality of conductive layers 111-118 and a plurality of insulating layers 121-128. In the present embodiment, the insulating layers 121-128 and the conductive layers 111-118 are staggered on the substrate 101 along the Z-axis direction depicted in FIG. 1A, so that the conductive layer 111 is located in the multilayer stacked structure 110. The bottom layer, while the insulating layer 128 is located on the top layer of the multilayer stack structure 110.

[0012]

The conductive layers 111-118 may be composed of a conductive semiconductor material such as an n-type polysilicon doped with phosphorus or arsenic, or an n-type epitaxial single crystal germanium. Further, the conductive layers 111-118 may also be composed of p-type polycrystalline germanium doped with boron or p-type epitaxial single crystal germanium. On the other hand, the conductive layers 111-118 may also be composed of an undoped semiconductor material such as an undoped polysilicon or an epitaxial single crystal germanium. In the present embodiment, the conductive layers 111-118 are composed of undoped polysilicon. The grain size of the undoped polycrystalline germanium may preferably be substantially between 400 nanometers (nm) and 600 nanometers; the sheet resistance of the undoped polycrystalline germanium may be substantially between 10 ⁷ ohms. /square

Between 10 ¹¹ ohm/square. The thickness of each of the conductive layers 111-118 may be substantially between 5 nm and 40 nm.

[0013]

 The insulating layers 121-128 may be composed of a dielectric material such as an oxide, a nitride, an oxynitride, a silicate or other materials. The thickness of each of the insulating layers 121-128 may be substantially between 10 nm and 50 nm. In some embodiments of the present invention, the conductive layers 111-118 and the insulating layers 121-128 may be fabricated by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) process.

[0014]

 Next, a patterning process is performed on the multilayer stack structure 110 to form a plurality of ridge-shaped multilayer stacks 110b. Referring to FIGS. 2A and 2B, FIG. 2A is a perspective view showing the structure after the patterning process of the multilayer stack structure 110 of FIG. 1A. Figure 2B is a top view of the structure according to Figure 2A. In some embodiments of the invention, the patterning process of the multilayer stack structure 110 includes first forming a patterned hard mask layer 130 on top of the multilayer stack structure 110. In the present embodiment, the patterned hard mask layer 130 is formed on the top surface of the insulating layer 128. Wherein, the patterned hard mask layer 130 includes a plurality of trench openings 130a extending downward along the Z-axis direction. The long axes of the trench openings 130a extend along the X-axis direction and expose a portion of the top surface of the insulating layer 128 to the outside.

[0015]

 In some embodiments of the present invention, the patterned hard mask layer 130 may be an advanced patterned film formed on the top surface of the multilayer stack structure 110 by a Chemical Vapor Deposition (CVD) process ( Advanced Patterning Film, APF). These trench openings 130a are formed by a photolithography process to remove a portion of the advanced patterned film. In this embodiment, each of the trench openings 130a has the same size, and each of the trench openings 130a has a rectangular hole pattern (but not limited thereto).

[0016]

 Then, the patterned hard mask layer 130 is used as an etching mask, and the multilayer stacked structure 110 is etched by an anisotropic etching process, such as a reactive ion etching (RIE) process. By forming the trench 110a extending in the Z-axis direction among the multilayer stacked structures, the multilayer stacked structure 110 is divided into a plurality of ridge-shaped multilayer stacks 110b, and a partial region of the substrate 101 is exposed through the trench 110a. . In this embodiment, each of the ridge multilayer laminates 110b includes a plurality of strip-shaped conductive layers 111-118 which can be used as the same layer of the same ridge multilayer laminate 110b in the serial three-dimensional memory device 100. A plurality of conductive strips 105 of memory cells.

[0017]

 Next, referring to FIG. 3A and FIG. 3B, FIG. 3A is a structural perspective view showing the memory material layer 140 and the conductive material layer 150 formed on the structure of FIG. 2A in sequence. Figure 3B is a top view of the structure according to Figure 3A. In some embodiments of the invention, the memory material layer 140 can be fabricated by a low pressure chemical vapor deposition process. The memory layer 140 may be composed of a composite layer (ie, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a hafnium oxide layer. In the present embodiment, the memory material layer 140 covers the top of the ridge stack 110 and the bottom of the trench 110a (i.e., the substrate 101 exposed by the trench 110a) and the sidewall 110c.

[0018]

 After the memory layer 140 is formed, a conductive material layer 150 is formed on the ridge multilayer laminate 110b, covering the memory material layer 140, and filling the trench 110a. In some embodiments of the invention, the conductive material layer 150 can be fabricated by a low pressure chemical vapor deposition process. The material constituting the conductive material layer 150 may include n-type polycrystalline germanium (or n-type epitaxial single crystal germanium) doped with phosphorus or arsenic, p-type polycrystalline germanium doped with boron (or p-type epitaxial single crystal germanium), Undoped polycrystalline germanium, metal silicides such as titanium telluride (TiSi), cobalt telluride (CoSi) or germanium (SiGe), oxide semiconductors such as indium zinc oxide (InZnO) or indium oxide Gallium zinc (InGaZnO), metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN), tantalum nitride ( TaN) or tantalum aluminum nitride (TaAlN), or a combination of two or more of the above materials.

[0019]

 Next, the conductive material layer 150 and the memory material layer 140 are patterned to form a plurality of via holes 102 in the trench 110a, thereby exposing a portion of the substrate 101 and the conductive strips 105 to the outside, and respectively being patterned. Among the conductive material layer 150 and the patterned memory material layer 140, a plurality of memory layers 103 and a plurality of conductive pillars 104 are defined. Referring to FIG. 4A, FIG. 4B and FIG. 4C, FIG. 4A is a structural top view after patterning the conductive material layer 150 and the memory material layer 140 of FIG. 3B. Fig. 4B is a partial structural perspective view taken along a tangent line S41 of Fig. 4A. Figure 4C is a partial structural perspective view taken along line S42 of Figure 4A.

[0020]

 In some embodiments of the present invention, the via 102 is formed by an anisotropic etching process, such as a reactive ion etching process, removing a portion of the conductive material layer 150 located in the trench 110a and a portion of the memory material layer 140. A portion of the conductive strip 105 is exposed to the outside by the sidewall of the via 102; and a portion of the conductive material layer 150 and the memory material layer 140 remaining in the trench 110a can be formed separately along the Z A strip-shaped memory layer 103 extending in the axial direction and a plurality of conductive pillars 104.

[0021]

 In this embodiment, each of the memory layers 103 is adjacent to a plurality of conductive strips 105 on the sidewalls of the trenches 110a but not exposed by the vias 102; and in each of the memory layers 103 and each of the conductive strips 105 overlapping positions define a memory area 106. Each of the conductive pillars 104 is adjacent to a memory layer 103 and overlaps the memory region 106 of the corresponding memory layer 103. The memory layer 103, the conductive strip 105 and the conductive column 104 overlap with the same memory region 106, and the three can constitute a memory cell. The plurality of memory cells defined by the plurality of memory layers 103, the conductive strips 105 and the conductive pillars 104 can constitute a memory array of the stereo memory device 100.

[0022]

 However, in other embodiments of the present invention, the memory region 106 defined by the conductive strip 105 and the memory layer 103 at the periphery of the memory array may be used as a serial selection transistor or ground of the stereo memory device 100. Selecting an active region of a transistor (not shown), and a corresponding conductive column 104 overlapping the active region, and a string selection line (SSL Select Line, SSL) or a ground selection line (Ground Select Line, GSL) ) (not shown) connection.

[0023]

 Thereafter, a dielectric layer 160 is formed on the sidewall of the via 102 (including the conductive strip 105 exposed through the via 110a) and the substrate 101 exposed through the via 110a. Referring to FIGS. 5A, 5B, and 5C, FIG. 5A is a structural top view after forming the dielectric layer 160 in the structure of FIG. 4A. Figure 5B is a partial structural perspective view taken along line S51 of Figure 5A. Figure 5C is a partial structural perspective view taken along line S52 of Figure 5A.

[0024]

 The dielectric layer 160 can be fabricated by a low pressure chemical vapor deposition process. The material constituting the dielectric layer 160 may be the same as the material constituting the insulating layers 121-128. In some embodiments of the invention, dielectric layer 160 may be comprised of a dielectric material comprising tantalum oxide, hafnium nitride, niobium oxynitride, niobate, or combinations thereof. In the present embodiment, the material constituting the dielectric layer 160 may include ruthenium oxide. In addition, the dielectric layer 160 preferably has a thickness between 3 nm and 10 nm.

[0025]

 Thereafter, a plurality of conductive plugs 108 are formed, partially filled in each of the through holes 102, and each of the conductive plugs 108 is exposed to the outer conductive strip 105 at least with each of the corresponding through holes 102. Partial overlap. Referring to FIGS. 6A, 6B, and 6C, FIG. 6A is a structural top view after forming a plurality of conductive plugs 108 in the structure of FIG. 5A. Fig. 6B is a partial structural perspective view taken along a tangent line S61 of Fig. 6A. Figure 6C is a partial structural perspective view taken along line S62 of Figure 6A. In this embodiment, in order to ensure that each of the conductive plugs 108 partially overlaps each of the conductive strips 105, each of the conductive plugs 108 must fill the corresponding through holes 102 until it is higher than the topmost conductive strips 105. bottom of. In other words, the height of the conductive plug 108, from the substrate 101, must be higher than the top of the conductive layer 118.

[0026]

 Subsequently, a plurality of dielectric plugs 109 are formed on the conductive plugs 108 to fill the vias 102 and are connected to the dielectric layer 160 on the sidewalls of the vias 102. Referring to FIGS. 7A, 7B, and 7C, FIG. 7A is a structural top view after forming a plurality of dielectric plugs 109 in the structure of FIG. 6A. Figure 7B is a partial structural perspective view taken along line S71 of Figure 7A. Figure 7C is a partial structural perspective view taken along line S72 of Figure 7A. In some embodiments of the invention, the dielectric plug 109 can be fabricated by a low pressure chemical vapor deposition process. The material constituting the dielectric plug 109 may be the same as the material constituting the dielectric layer 160. In some embodiments of the invention, the dielectric plug 109 may be comprised of a dielectric material comprising tantalum oxide, tantalum nitride, niobium oxynitride, niobate or combinations thereof. In the present embodiment, the material constituting the dielectric plug 109 may include ruthenium oxide.

[0027]

 Then, the conductive material layer 150 located above the ridge multilayer laminate 110b is subjected to a further patterning process to form a plurality of word lines 170 on the top of the ridge multilayer laminate 110b, extending in the Y-axis direction, and It is in electrical contact with the conductive column 104. Referring to FIGS. 8A, 8B, and 8C, FIG. 8A is a structural top view after forming a plurality of word lines 170 in the structure of FIG. 8A. Fig. 8B is a partial structural perspective view taken along a tangent line S81 of Fig. 8A. Figure 8C is a partial structural perspective view taken along line S82 of Figure 8A. In some embodiments of the invention, a plurality of word lines 170 are formed on top of the ridge multilayer stack 110b; and each word line 170 is in electrical contact with the plurality of conductive pillars 104, respectively. A conductive plug 108 is disposed between two adjacent word lines 170, and the conductive plug 108 is electrically isolated from the two adjacent word lines 170 by the dielectric layer 160 and the dielectric plug 109.

[0028]

 Subsequently, the preparation of the stereo memory element 100 is completed by a series of back-end processes. The memory array of the stereo memory device 100 includes at least a plurality of hierarchical structures formed on the conductive layers 111-118. For example, please refer to FIG. 9. FIG. 9 is a schematic cross-sectional view showing a partial hierarchical structure along the X-Y cross section of the three-dimensional memory device 100. In the present embodiment, the hierarchical structure illustrated in FIG. 9 is located on the conductive layer 115. Wherein each hierarchical structure comprises a plurality of memory cells, such as memory cells 180a, 180b, 180c, 180d, 180e and 180f; and these memory cells 180a, 180b, 180c, 180d, 180e and 180f are via patterned conductive layer 115 The formed conductive strips 105 extend in the X-axis direction and are connected in series with each other.

[0029]

 Each of these memory cells 180a, 180b, 180c, 180d, 180e, and 180f includes a memory layer 103 and a conductive pillar 104. The memory layer 103 extends in the Z-axis (vertical X-Y plane) direction and abuts the conductive strip 105, and defines a memory region 106 at a position overlapping the conductive strip 105. The conductive column 104 also extends in the Z-axis direction and is adjacent to the memory layer 103 and overlaps the memory region 106.

[0030]

 Two adjacent memory cells, such as memory cells 180a and 180b, have a distance D1 parallel to the X-axis direction. A dielectric layer 160 and a conductive plug 108 are disposed between the two. The dielectric layer 160 extends in the Z-axis direction and abuts the conductive strips 105, the memory layer 103 and the conductive pillars 104 of the adjacent two-phase memory cells 180a and 180b, respectively. The conductive plug 108 extends in the Z-axis direction and extends at least partially overlapping a portion of the conductive strips 105 extending in the X direction for concatenating adjacent two-phase memory cells 180a and 180b. The dielectric layer 160 is interposed between the conductive plug 108 and the conductive strip 105 of the two-phase memory cells 180a and 180b, the memory layer 103 and the conductive pillar 104, so that the conductive plug 108 can be through the dielectric layer. 160 is electrically isolated from the conductive strips 105, the memory layer 103, and the conductive pillars 104 of the two adjacent memory cells 180a and 180b. Because the conductive plugs 108 and the conductive strips 105 are electrically isolated from each other, and at least a portion overlaps each other. Thus, the conductive plug 108 can act as a floating gate for the conductive strip 105. When the stereo memory device 100 performs a reading or stylization operation, the conductive plug 108 has an induced voltage due to the conduction of the conductive column 104, and can be connected in the conductive strips 105 of the two adjacent memory cells 180a and 180b. Forming an inversion layer helps to reduce the series resistance between the memory cells 180a and 180b.

[0031]

 It is also worth noting that the hierarchical structure formed on adjacent conductive layers, such as conductive layer 114 under conductive layer 115, also includes the same structure as that depicted in FIG. The memory layer 103 and the conductive pillar 104 extending in the Z-axis direction of the memory cell 180a are also adjacent to and overlap with the conductive strips 105 on the conductive layer 114, thereby defining another memory including the memory region 106. Cell (not shown). Since the two memory cells are blocked by the insulating layer 124 (not shown), there is a distance between the two in the direction parallel to the Z axis (not shown).

[0032]

 According to the above embodiment, the present invention provides a three-dimensional memory element and a method of fabricating the same. The stereo memory element includes at least a plurality of levels; each of the levels includes a plurality of memory cells and is connected in series by conductive strips extending in a first direction. Each of the memory cells includes a memory layer and a conductive column extending in the second direction. Wherein, the memory layer is adjacent to the conductive strip, and a memory area is defined at a position overlapping the conductive strip. The conductive column is adjacent to the memory layer and overlaps the memory region. a conductive plug having a parallel conductive column between the adjacent conductive cells of the two memory cells, at least partially overlapping the conductive strips connected in series with the two memory cells, and the conductive plugs are respectively separated by the dielectric layer The adjacent two memory cells and the conductive strip are electrically isolated.

[0033]

 Due to the arrangement of the conductive plug and the dielectric layer, the conductive plug has the function of a floating gate. When the three-dimensional memory component is operated, the conductive plug has an induced voltage due to the conduction of the conductive column, and Forming an inversion layer in the conductive strips of two adjacent memory cells in series helps to reduce the series resistance between the two memory cells. Therefore, it is not necessary to perform ion implantation doping on the conductive strips of the adjacent two memory cells in series, thereby reducing the series resistance between the memory cells. At the same time, the conventional technology can solve the problems of complicated process steps, increased thermal budget, and interference with reading, stylization and erasing of memory components due to the ion implantation doping process.

[0034]

 While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100: Stereo memory component

103: Memory layer

104: conductive columnar body

105: Conductive strip

108: conductive plug

115: conductive layer

160: dielectric layer

180a-180f: memory cell

D1: distance

106: Memory area

Claims (10)

[Item 1] A memory component, comprising:
a first conductive strip extending in a first direction;
a first memory layer extending along a second direction, overlapping the first conductive strip, and defining a first memory region at an overlap of the first memory layer and the first conductive strip;
a first conductive column extending in the second direction and adjacent to the first memory layer and overlapping the first memory region;
a first dielectric layer extending along the second direction and adjacent to the first conductive strip, the first memory layer and the first conductive pillar; and a first conductive plug along the second direction Extending and at least partially overlapping the first conductive strip and electrically isolated from the first conductive strip, the first memory layer and the first conductive pillar by the first dielectric layer. [Item 2] For example, the memory component described in claim 1 of the patent scope further includes:
a second dielectric layer extending along the second direction and adjacent to the first conductive strip, the first memory layer and the first conductive pillar, and the first conductive pillar is located at the first Between the dielectric layer and the second dielectric layer; and a second conductive plug extending along the second direction, and the first conductive strip and the first memory layer And electrically isolated from the first conductive column. [Item 3] The memory component as described in claim 2 of the patent scope further includes:
a second memory layer extending along the second direction and overlapping the first conductive strip, and defining a second memory area at the second memory layer overlapping the first conductive strip, and the Between the two memory regions and the first memory region, having a distance parallel to the first direction; and a second conductive column extending along the second direction and adjacent to and overlapping the second memory region; The first conductive plug and the second conductive pillar are electrically isolated by the first dielectric layer. [Item 4] The memory component as described in claim 3 of the patent scope further includes:
a second conductive strip extending along the first direction and overlapping with the first memory layer and the second memory layer respectively defining a third memory region and a fourth memory region, and the first conductive pillar The second conductive column and the second conductive column overlap with the third memory region and the fourth memory region, respectively; and an insulating layer extending along the first direction and located at the first conductive strip and the second conductive Between the strips. [Item 5] The memory component as described in claim 4 of the patent scope further includes:
a first word line extending in a third direction and in electrical contact with the first conductive column; and a second word line extending along the third direction and the second conductive column Electrophysical contact
The first conductive plug is located between the first word line and the second word line, and is electrically isolated from the first word line and the second word line. [Item 6] The memory component as described in claim 5, further comprising:
a first dielectric plug on the first conductive plug and in contact with the first dielectric layer and the first conductive plug; and a second dielectric plug on the second conductive plug And contacting the second dielectric layer and the second conductive plug. [Item 7] The memory component as described in claim 5, further comprising:
A plurality of ridged-shaped multi-layer stacks are disposed on a substrate and extending along the first direction, wherein each of the plurality of ridge-shaped multilayer stacks includes a portion of the first conductive strip a strip, the insulating layer and the second conductive strip;
The first memory layer and the second memory layer are respectively located in a trench defined by the plurality of ridge multilayer stacks and cover a sidewall of the trench;
The first conductive column and the second conductive column are located in the trenches, respectively covering the first memory layer and the second memory layer; and the first word line and the second A word line is located on top of the ridge multilayer stack. [Item 8] For example, the memory component described in claim 1 of the patent scope further includes:
a second memory layer extending along the second direction to overlap the first conductive strip, and defining an active region at an overlap of the second memory layer and the first conductive strip; and a second conductive pillar The body extends in the second direction and overlaps the active area and is connected to a String Select Line (SSL). [Item 9] For example, the memory component described in claim 1 of the patent scope further includes:
a second memory layer extending along the second direction to overlap the first conductive strip, and defining an active region at an overlap of the second memory layer and the first conductive strip; and a second conductive pillar The body extends in the second direction and overlaps the first active area and is connected to a Ground Select Line (GSL). [Item 10] A method of fabricating a memory component, comprising:
Forming a multi-layer stack on a substrate;
Patterning the multi-layer stack structure to form a plurality of ridge-like multilayer stacks; wherein each of the ridge-like multilayer stacks includes at least one conductive strip extending along a first direction;
Forming a memory material layer on a bottom and sidewalls of the at least one trench between the ridge multilayer laminates;
Forming a layer of conductive material on the ridge multilayer stack and filling the trench;
Patterning the conductive material layer and the memory material layer to form a plurality of via holes in the trench to expose a portion of the substrate and the conductive strip to the outside; wherein the patterned conductive material layer includes at least a conductive column in the trench; the patterned layer of memory material includes at least one memory layer in the trench; and a memory region is defined between the memory layer and the conductive strip;
Forming a dielectric layer on sidewalls of the via holes and the substrate exposed to the outside;
Forming a plurality of conductive plugs, partially filling the through holes, respectively, and partially overlapping the conductive plugs with the conductive strips;
Forming a plurality of dielectric plugs on the conductive plugs to fill the through holes; and patterning the conductive material layer to form at least one word line on top of the plurality of ridge multilayer stacks, Extending in a third direction and in electrical contact with the conductive column.