CN105826323B - Memory component and preparation method thereof - Google Patents
Memory component and preparation method thereof Download PDFInfo
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- CN105826323B CN105826323B CN201510003971.6A CN201510003971A CN105826323B CN 105826323 B CN105826323 B CN 105826323B CN 201510003971 A CN201510003971 A CN 201510003971A CN 105826323 B CN105826323 B CN 105826323B
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Abstract
The invention discloses a kind of memory component and preparation method thereof, which includes：First conductive strips, the first accumulation layer, the first conductive columns, the first dielectric layer and the first conductive plunger.First conductive strips extend in a first direction.First accumulation layer extends in a second direction, and adjacent first conductive strips, and Chong Die with the first conductive strips, and the first memory block is defined in the first accumulation layer.First conductive columns extend in a second direction, abut and store area overlapping with first.First dielectric layer extends in a second direction, and adjacent first conductive strips, the first accumulation layer and the first conductive columns.First conductive plunger, extends in a second direction, and least partially overlapped with the first conductive strips, and is electrically isolated with the first conductive strips, the first accumulation layer and the first conductive columns by the first dielectric layer.
Description
Technical field
The invention relates to a kind of non-volatile memory devices and preparation method thereof.In particular to a kind of solid
(Three-Dimension, 3D) non-volatile memory device and preparation method thereof.
Background technology
Traditional, nonvolatile memories (non-volatile memory) element, such as nand flash memory element, can generally make
Multiple storage lists between bit line and source electrode line are concatenated with monocrystalline silicon or the conductive strips (stripe) of polycrystalline silicon material
Member.And in order to reduce the series resistor between storage unit (series resistance), it will usually to series winding storage unit it
The monocrystalline silicon or polycrystalline silicon band asked carry out ion implantation doping.However, there is 3-dimensional multi-layered memory array making
Nand flash memory element when, since polysilicon or mono-crystalline epitaxial silicon conductive strips can form a multi-laminate with multiple dielectric layer laminations
Structure, storage unit are then located on the vertical plane of multilayer stack structure；It to be noted in the polycrystalline silicon band between storage unit
Enter ion admixture, can not only processing step be made to complicate, increases the heat budget (thermal budget) of technique, and ion admixture
Diffusion control be not easy, be easy can the reading of disturbance storage element, programming and erasing (program/erase), and then cause
Component failure.
Therefore, a kind of more advanced memory component of offer in need and preparation method thereof, to improve known technology institute face
The problem of facing.
Invention content
According to an embodiment of this specification, a kind of memory component is provided comprising：First conductive strips, first are deposited
Reservoir, the first conductive columns, the first dielectric layer and the first conductive plunger.First conductive strips extend in a first direction.The
One accumulation layer extends in a second direction, and Chong Die with the first conductive strips, and Chong Die with the first conductive strips in the first accumulation layer
Place defines the first memory block.First conductive columns extend in a second direction, and abut the first accumulation layer and stored with first
Area overlapping.First dielectric layer extends in a second direction, and adjacent first conductive strips, the first accumulation layer and the first conductive columns
Body.First conductive plunger, extends in a second direction, and least partially overlapped with the first conductive strips, and passes through the first dielectric layer
And it is electrically isolated with the first conductive strips, the first accumulation layer and the first conductive columns.
According to another embodiment of this specification, a kind of production method of memory component is provided, is included the following steps：It is first
First multilayer laminated (multi-layer stack) structure is formed on the surface of the substrate.Patterned multilayer laminated construction again, with shape
At multiple carinate multilayer laminated (ridge-shaped stacks), make each it is carinate it is multilayer laminated include at least one along
The conductive strips that first direction extends.Then, in the bottom and side wall of these carinate multilayer laminated at least one groove
Form storage material layer.Then at these carinate multilayer laminated upper formation conductive material layers, and fill up groove.Then, patterning is led
Material layer and storage material layer are used the base material of a part and conductive strips is sudden and violent with forming multiple through-holes among groove
It is exposed to outer.Wherein, patterned storage material layer includes at least an accumulation layer being located in groove；Patterned conductive material
Layer includes at least the conductive columns being located in groove, and defines a storage in this accumulation layer and conductive strips overlapping
Area.Later, it in the side wall of through-hole and is exposed on outer base material and forms dielectric layer.Re-form multiple conductive plungers, difference portion
Divide ground to fill these through-holes, and conductive plunger is made at least to partly overlap with conductive strips.Subsequently, in shape on these conductive plungers
At multiple dielectric plugs, to fill up these through-holes.Then, patterning conductive material layer again, in carinate multilayer laminated top
Portion forms at least one wordline, extends along third direction, and in electrical contact with conductive columns.
According to above-described embodiment, the present invention is in a kind of three-dimensional storage element of offer and preparation method thereof.Solid storing
Device element includes at least multiple stratum；Each stratum includes multiple storage units, and the conductive bar by extending in a first direction
Band is contacted.Each storage unit includes the accumulation layer extended in a second direction and conductive columns.Wherein, accumulation layer
Adjacent conductive strips, and in the position be overlapped with conductive strips, define memory block.Conductive columns contiguous storage layer, and with
Store area overlapping.Have the conductive plunger there are one parallel electrically conductive column between the conductive columns of adjacent two storage unit, with
The conductive strips for concatenating two storage units are least partially overlapped, and are stored conductive plunger with adjacent two respectively by dielectric layer
Unit and conductive strips electrically isolate.
Due to the configuration mode of conductive plunger and dielectric layer, conductive plunger is made to have the function of floating grid, works as solid storing
When device element is operated, conductive plunger can have an induced voltage because conductive columns are connected, and can be deposited in series winding adjacent two
Inversion layer is formed in the conductive strips of storage unit, helps to reduce the series resistor between two storage units.Therefore, it is not required to string
Even the conductive strips of adjacent two storage unit carry out ion implantation doping, you can reduce the series resistor between storage unit.Together
When can solve known technology, and because using, the processing step caused by ion implantation doping process is complicated, heat budget increases and interference
The problem of memory component reads, programs and wipes.
Description of the drawings
In order to be clearer and more comprehensible to the above embodiment of the present invention and other objects, features and advantages, spy lift it is several compared with
Good embodiment, and coordinate institute's accompanying drawings, it is described in detail below：
Figure 1A is the structural perspective of the multi-layer laminate structure depicted in an embodiment according to the present invention；
Figure 1B is the structure top view of the multi-layer laminate structure depicted in Figure 1A；
Fig. 2A is to be painted the structural perspective carried out to the multi-layer laminate structure of Figure 1A after Patternized technique；
Fig. 2 B are the structure top views depicted in A according to fig. 2；
Fig. 3 A are to be painted the structure perspective sequentially formed in the structure of Fig. 2A after storage material layer and conductive material layer
Figure；
Fig. 3 B are the structure top views depicted in A according to fig. 3；
Fig. 4 A are the structure top views being painted after being patterned to the conductive material layer and storage material layer of Fig. 3 B；
Fig. 4 B are the part-structure perspective views depicted in the tangent line S41 along Fig. 4 A；
Fig. 4 C are the part-structure perspective views depicted in the tangent line S42 along Fig. 4 A；
Fig. 5 A are to be shown in the structure top view formed in the structure of Fig. 4 B after dielectric layer；
Fig. 5 B are the part-structure perspective views depicted in the tangent line S51 along Fig. 5 A；
Fig. 5 C are the part-structure perspective views depicted in the tangent line S52 along Fig. 5 A；
Fig. 6 A are to be shown in the structure top view formed in the structure of Fig. 5 A after multiple conductive plungers；
Fig. 6 B are the part-structure perspective views depicted in the tangent line S61 along Fig. 6 A；
Fig. 6 C are the part-structure perspective views depicted in the tangent line S62 along Fig. 6 A；
Fig. 7 A are to be shown in the structure top view formed in the structure of Fig. 6 A after multiple dielectric plugs；
Fig. 7 B are the part-structure perspective views depicted in the tangent line S71 along Fig. 7 A；
Fig. 7 C are the part-structure perspective views depicted in the tangent line S72 along Fig. 7 A；
Fig. 8 A are to be shown in the structure top view formed in the structure of Fig. 7 A after a plurality of wordline；
Fig. 8 B are the part-structure perspective views depicted in the tangent line S81 along Fig. 8 A；
Fig. 8 C are the part-structure perspective views depicted in the tangent line S82 along Fig. 8 A；
Fig. 9 is the part hierarchical structure diagrammatic cross-section depicted in the sections X-Y along three-dimensional storage element.
【Symbol description】
100：Three-dimensional storage element 101：Base material
102：Through-hole 103：Accumulation layer
104：Conductive columns 105：Conductive strips
106：Memory block 108：Conductive plunger
109：Dielectric plugs 110：Multi-layer laminate structure
110a：Groove 110b：It is carinate multilayer laminated
110c：The side wall 111-118 of groove：Conductive layer
121-128：Insulating layer 130：Patterning hard mask layer
130a：Groove opening 140：Storage material layer
150：Conductive material layer 160：Dielectric layer
170：Wordline 180a-180f：Storage unit
S51, S52, S61 S62, S71, S72, S81, S82, S91 and S92：Tangent line
Specific implementation mode
A kind of three-dimensional storage element of present invention offer and preparation method thereof, can be not required to two consecutive storage units of contacting
Conductive strips carry out ion implantation doping in the case of, reduce storage unit between series resistor.In order to the present invention's
Above-described embodiment and other objects, features and advantages can be clearer and more comprehensible, several three-dimensional storage elements cited below particularly and its making
Method coordinates institute's accompanying drawings to elaborate as preferred embodiment.
But it must be noted that these specific case study on implementation and method, be not limited to the present invention.The present invention still may be used
It is implemented using other features, element, method and parameter.The it is proposed of preferred embodiment is only to illustrate the present invention
Technical characteristic is not limited to scope of the presently claimed invention.Have usually intellectual in the technical field, it can basis
The description of following description makees impartial modification and variation in the scope for not departing from the present invention.Different embodiments with
Among schema, identical element will be indicated with identical component symbol.
The method for making three-dimensional storage element 100, includes the following steps：It is formed first on the surface of base material 101 more
Layer stacked structure (multi-layer stack) 110.Figure 1A and Figure 1B are please referred to, Figure 1A is an embodiment according to the present invention
The structural perspective of depicted multi-layer laminate structure 110.Figure 1B is the knot of the multi-layer laminate structure 110 depicted in Figure 1A
Structure top view.In some embodiments of the invention, multi-layer laminate structure 110 is formed on base material 101.Multi-layer laminate structure
110 include multiple conductive layer 111-118 and multiple insulating layer 121-128.In the present embodiment, insulating layer 121-128 with lead
Electric layer 111-118 is along the Z-direction depicted in Figure 1A, and the lamination interlaced with each other on base material 101 makes conductive layer 111 be located at
The bottom of multi-layer laminate structure 110, and insulating layer 128 is located at the top layer of multi-layer laminate structure 110.
Conductive layer 111-118 can by conducting semiconductor material, such as doped with the N-shaped polysilicon or N-shaped of phosphorus or arsenic outside
Prolong monocrystalline silicon, is constituted.In addition, conductive layer 111-118 can also be by the p-type or p-type epitaxial monocrystalline silicon doped with boron
It is constituted.On the other hand, conductive layer 111-118 can also by undoped semi-conducting material, such as undoped polysilicon or
Epitaxial monocrystalline silicon is constituted.In the present embodiment, conductive layer 111-118 is made of non-impurity-doped polysilicon.Non-impurity-doped polycrystalline
The crystallite dimension (grain size) of silicon, preferably can be substantially between 400 nanometers (nm) to 600 nanometers；Non-impurity-doped polycrystalline
The sheet resistance (sheet resistance) of silicon can be substantially between 107Ohm/square to 1011Between ohm/square.It is conductive
The thickness of layer 111-118 each can be substantially between 5 nanometers to 40 nanometers.
Insulating layer 121-128 can be by dielectric material, such as Si oxide (oxide), silicon nitride (nitride), silicon
Nitrogen oxides (oxynitride), silicate (silicate) or other materials, are constituted.The thickness of each insulating layer 121-128
Degree can be substantially between 10 nanometers to 50 nanometers.In some embodiments of the invention, conductive layer 111-118 and insulating layer
121-128 can by, for example, low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition,
LPCVD) technique is made.
Then, a Patternized technique is carried out to multi-layer laminate structure 110, to form multiple carinate multilayer laminated 110b.Please
It is the structure perspective being painted after carrying out Patternized technique to the multi-layer laminate structure 110 of Figure 1A with reference to Fig. 2A and Fig. 2 B, Fig. 2A
Figure.Fig. 2 B are the structure top views depicted in A according to fig. 2.In some embodiments of the invention, multi-layer laminate structure 110
Patternized technique, including elder generation form a patterning hard mask layer 130 at 110 top of multi-layer laminate structure.In the present embodiment, scheme
Case hard mask layer 130 is formed at the top surface of insulating layer 128.Wherein, patterning hard mask layer 130 include it is multiple along
The groove opening 130a that Z-direction extends downwardly.The long axis of these groove openings 130a extends along X-direction, and by one
The top surface of the insulating layer 128 of part is exposed to outer.
In some embodiments of the invention, patterning hard mask layer 130 can be that one kind passing through chemical vapor deposition
(Chemical Vapor Deposition, CVD) technique, advanced figure is formed by the top surface of multi-layer laminate structure 110
Case film (Advanced Patterning Film, APF).These groove openings 130a is then to pass through photoetching
(photolithography) technique is formed to remove the advanced patterned film of a part.In the present embodiment, each groove
The 130a that is open has identical size, and each groove opening 130a is all oblong aperture pattern (but not limited to this).
Then, it is etching mask with patterning hard mask layer 130, passes through anisotropic etching technics (anisotropic
Etching process), such as reactive ion etching (Reactive Ion Etching, RIE) technique, to multilayer laminated knot
Structure 110 performs etching.The groove 110a that formation extends along Z-direction among multi-layer laminate structure is used, it will be multilayer laminated
Structure 110 is divided into multiple carinate multilayer laminated 110b, and the subregion of base material 101 is exposed to outside via groove 110a.
In the present embodiment, each carinate multilayer laminated 110b includes the conductive layer 111-118 of a part of strip, and it is vertical to can be used as series winding
Positioned at the conductive strips of multiple storage units of the same stratum of same carinate multilayer laminated 110b in body memory element 100
105。
Then, it is to be painted sequentially to form 140 He of storage material layer in the structure of Fig. 2A to please refer to Fig. 3 A and Fig. 3 B, Fig. 3 A
Structural perspective after conductive material layer 150.Fig. 3 B are the structure top views depicted in A according to fig. 3.In some of the present invention
In embodiment, storage material layer 140 can be made by low-pressure chemical vapor deposition process.Accumulation layer 140 can be by
Including silica (silicon oxide) layer, silicon nitride (silicon nitride) layer and silicon oxide layer composite layer (that is,
ONO layer) it is constituted.In the present embodiment, the covering of storage material layer 140 is positioned at the top of carinate lamination 110 and groove 110a
Bottom (outer base material 101 is exposed to by groove 110a) and side wall 110c on.
It is forming accumulation layer 140 and then in forming conductive material layer 150 on these carinate multilayer laminated 110b, is covering
Storage material layer 140, and fill up groove 110a.In some embodiments of the invention, low-pressure chemical vapor deposition can be passed through
Technique makes conductive material layer 150.The material of conductive material layer 150 is constituted, can include the N-shaped polycrystalline doped with phosphorus or arsenic
Silicon (or N-shaped epitaxial monocrystalline silicon), p-type (or p-type epitaxial monocrystalline silicon), undoped polysilicon, metal doped with boron
Silicide (silicides), such as titanium silicide (TiSi), cobalt silicide (CoSi) or SiGe (SiGe), oxide semiconductor
(oxide semiconductors), such as indium zinc oxide (InZnO) or indium gallium zinc (InGaZnO), metal, such as aluminium
(A1), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN), tantalum nitride (TaN) or tantalum nitride aluminium
(TaAlN) or the composition of two or more above-mentioned materials is constituted.
Then, patterning conductive material layer 150 and storage material layer 140, form multiple through-holes among groove 110a
102, it uses and is exposed to the base material 101 of a part and conductive strips 105 outside, and respectively in the conductive material layer being patterned
150 and the storage material layer 140 that is patterned among, define multiple accumulation layers 103 and multiple conductive columns 104.Please
It is to be painted to pattern the conductive material layer 150 and storage material layer 140 of Fig. 3 B with reference to Fig. 4 A, Fig. 4 B and Fig. 4 C, Fig. 4 A
Structure top view later.Fig. 4 B are the part-structure perspective views depicted in the tangent line S41 along Fig. 4 A.Fig. 4 C are along Fig. 4 A
Tangent line S42 depicted in part-structure perspective view.
In some embodiments of the invention, through-hole 102 is by anisotropic etching technics, such as reactive ion etching work
Skill removes a part of conductive material layer 150 and a part of storage material layer 140 among being located at groove 110a and is formed, made
A part of conductive strips 105 are exposed to outer by the side wall of through-hole 102；And remained in a part of conduction among groove 110a
Material layer 150 and storage material layer 140 can then be respectively formed multiple strip accumulation layers 103 extended along Z-direction and multiple
Conductive columns 104.
In the present embodiment, each accumulation layer 103 is located at multiple on groove 110a side walls, but not by 102 institute of through-hole
Exposed a part of conductive strips 105 abut；And in each accumulation layer 103 position Chong Die with each conductive strips 105
It sets, defines a memory block 106.Each conductive columns 104 abut an accumulation layer 103, and with corresponding storage
The memory block 106 of layer 103 is overlapped.Wherein, the accumulation layer 103 Chong Die with the same memory block 106, conductive strips 105 and conduction
Column 104, three may make up a storage unit.And by multiple accumulation layers 103, conductive strips 105 and conductive columns 104
Multiple storage units that institute's common definition comes out, may make up the memory array of three-dimensional storage element 100.
But in other embodiments of the present invention, it is located at the conductive strips 105 and accumulation layer 103 of memory array periphery
The memory block 106 that overlapping institute common definition goes out, serial selection transistor that can be as three-dimensional storage element 100 or ground connection choosing
Select the active area of transistor (not being painted), and with the corresponding conductive columns 104 of the active area overlapping, then with serial selection line
(String Select Line, SSL) or ground connection selection line (Ground Select Line, GSL) (not being painted) connect.
Later, in the side wall of through-hole 102 (including to be exposed to outer conductive strips 105 via through-hole 110a) and i.e. via
Through-hole 110a, which is exposed on outer base material 101, forms dielectric layer 160.It is to be shown in figure to please refer to Fig. 5 A, Fig. 5 B and Fig. 5 C, Fig. 5 A
The structure top view after dielectric layer 160 is formed in the structure of 4A.Fig. 5 B are the part knots depicted in the tangent line S51 along Fig. 5 A
Structure perspective view.Fig. 5 C are the part-structure perspective views depicted in the tangent line S52 along Fig. 5 A.
Dielectric layer 160 can be made by low-pressure chemical vapor deposition process.The material for constituting dielectric layer 160, can
With with the material identical that is constituted insulating layer 121-128.Among some embodiments of the present invention, dielectric layer 160 can be by wrapping
Oxide containing silicon, silicon nitride, silicon nitrogen oxides, silicate or said combination dielectric material constituted.The present embodiment it
In, the material for constituting dielectric layer 160 may include silica.In addition, 160 preferable thickness of dielectric layer between 3nm to 10nm it
Between.
And then multiple conductive plungers 108 are formed, it is partially filled among each through-hole 102, and make each
Conductive plunger 108 is at least exposed to outer conductive strips 105 by corresponding through-hole 102 with each and partly overlaps.It please refers to
Fig. 6 A, Fig. 6 B and Fig. 6 C, Fig. 6 A are to be shown in the structure top view formed in the structure of Fig. 5 A after multiple conductive plungers 108.
Fig. 6 B are the part-structure perspective views depicted in the tangent line S61 along Fig. 6 A.Fig. 6 C are depicted in the tangent line S62 along Fig. 6 A
Part-structure perspective view.In the present embodiment, in order to ensure each conductive plunger 10g at least with each conductive strips 105
It partly overlaps, each conductive plunger 108 must be filled with corresponding through-hole 102, the conductive strips 105 until exceeding top
Bottom.In other words, the height of conductive plunger 108 is started by base material 101, it is necessary to exceed the top of conductive layer 118.
Subsequently, in forming multiple dielectric plugs 109 on these conductive plungers 108, to fill up these through-holes 102, and with
Dielectric layer 160 on 102 side wall of through-hole connects.It is the structure for being shown in Fig. 6 A to please refer to Fig. 7 A, Fig. 7 B and Fig. 7 C, Fig. 7 A
The middle structure top view formed after multiple dielectric plugs 109.Fig. 7 B are the part-structures depicted in the tangent line S71 along Fig. 7 A
Perspective view.Fig. 7 C are the part-structure perspective views depicted in the tangent line S72 along Fig. 7 A.In some embodiments of the invention,
Dielectric plugs 109 can be made by low-pressure chemical vapor deposition process.Constitute the material of dielectric plugs 109, Ke Yihe
Constitute the material identical of dielectric layer 160.Among some embodiments of the present invention, dielectric plugs 109 can be by comprising silica
Compound, silicon nitride, silicon nitrogen oxides, silicate or said combination dielectric material constituted.Among the present embodiment, constitute
The material of dielectric plugs 109 may include silica.
Then, Patternized technique again is carried out to the conductive material layer 150 above carinate multilayer laminated 110b,
To form a plurality of wordline 170 in the top of carinate multilayer laminated 110b, along Y direction extend, and with conductive columns 104
It is in electrical contact.It is to be shown in the structure of Fig. 8 A to be formed after a plurality of wordline 170 to please refer to Fig. 8 A, Fig. 8 B and Fig. 8 C, Fig. 8 A
Structure top view.Fig. 8 B are the part-structure perspective views depicted in the tangent line S81 along Fig. 8 A.Fig. 8 C are the tangent lines along Fig. 8 A
Part-structure perspective view depicted in S82.Among some embodiments of the present invention, a plurality of wordline 170 is formed in carinate multilayer
On the top of lamination 110b；And each wordline 170 is in electrical contact with multiple conductive columns 104 respectively.Wherein, two is adjacent
A conductive plunger 108 is configured between wordline 170, and conductive plunger 108 passes through dielectric layer 160 and dielectric plugs 109 and two-phase
Adjacent wordline 170 electrically isolates.
Subsequently, then by a succession of last part technology the preparation of three-dimensional storage element 100 is completed.Three-dimensional storage element
In 100 memory array, including at least multiple hierarchical structures being formed on conductive layer 111-118.Such as Fig. 9 is please referred to,
Fig. 9 is the part hierarchical structure diagrammatic cross-section depicted in the sections X-Y along three-dimensional storage element 100.In the present embodiment
In, the hierarchical structure depicted in Fig. 9 is located on conductive layer 115.Wherein, each hierarchical structure includes multiple storage units,
Such as storage unit 180a, 180b, 180c, 180d, 180e and 180f；And these storage units 180a, 180b, 180c, 180d,
It is concatenated with one another along X-direction extension to be formed by conductive strips 105 via patterned conductive layer 115 by 180e and 180f.
The each of these storage units 180a, 180b, 180c, 180d, 180e and 180f all include 103 and of an accumulation layer
One conductive columns 104.Wherein, accumulation layer 103 extends along Z axis (vertical X-Y plane) direction, and adjacent conductive strips 105, and
In the position Chong Die with conductive strips 105, memory block 106 is defined.Conductive columns 104 also extend along Z-direction, and adjacent
Accumulation layer 103, and it is Chong Die with memory block 106.
A distance with paralleled by X axis direction between two adjacent storage units, such as storage unit 180a and 180b
D1.And it is configured with a dielectric layer 160 and a conductive plunger 108 therebetween.Wherein, dielectric layer 160 extends along Z-direction,
And conductive strips 105, accumulation layer 103 and the conductive columns 104 of adjacent two-phase storage unit 180a and 180b are abutted respectively.It leads
Electric plug 108 along Z-direction extend, and with extend in X direction, for concatenating the one of adjacent two-phase storage unit 180a and 180b
Partially electronically conductive band 105 is least partially overlapped.Dielectric layer 160 be located in conductive plunger 108 and two-phase storage unit 180a and
Between 104 three of conductive strips 105, accumulation layer 103 and conductive columns of 180b, make conductive plunger 108 that can pass through dielectric layer
160 and with conductive strips 105, accumulation layer 103 and the conductive columns 104 of two consecutive storage unit 180a and 180b electrically every
From.Since conductive plunger 108 and conductive strips 105 are electrically isolated from one another, and at least part of overlapped.Therefore conductive
Plug 108 can be used as the floating grid of conductive strips 105.It is conductive when three-dimensional storage element 100 is read out or when programming operation
Plug 108 can have induced voltage because conductive columns 104 are connected, and can contact two consecutive storage unit 180a's and 180b
Inversion layer is formed in conductive strips 105, contributes to and reduces the series resistor between storage unit 180a and 180b.
It is otherwise noted that it is formed in adjacent conductive layer, such as on the conductive layer 114 of 115 lower section of conductive layer
Hierarchical structure also include structure identical as depicted in Fig. 9.Wherein, the storage extended along Z-direction in storage unit 180a
Device layer 103 and conductive columns 104 also can be adjacent to each other with the conductive strips 105 on conductive layer 114 and be overlapped, depending on
Justice goes out another storage unit (not being painted) for including memory block 106.Due between two storage units (not by insulating layer 124
It is painted) barrier, therefore there is a distance (not being painted) in the direction of parallel Z axis therebetween.
According to above-described embodiment, the present invention is in a kind of three-dimensional storage element of offer and preparation method thereof.Solid storing
Device element includes at least multiple stratum；Each stratum includes multiple storage units, and the conductive bar by extending in a first direction
Band is contacted.Each storage unit includes the accumulation layer extended in a second direction and conductive columns.Wherein, accumulation layer
Adjacent conductive strips, and in the position be overlapped with conductive strips, define memory block.Conductive columns contiguous storage layer, and with
Store area overlapping.Have the conductive plunger there are one parallel electrically conductive column between the conductive columns of adjacent two storage unit, with
The conductive strips for concatenating two storage units are least partially overlapped, and are stored conductive plunger with adjacent two respectively by dielectric layer
Unit and conductive strips electrically isolate.
Due to the configuration mode of conductive plunger and dielectric layer, conductive plunger is made to have the function of floating grid, works as solid storing
When device element is operated, conductive plunger can have an induced voltage because conductive columns are connected, and can be deposited in series winding adjacent two
Inversion layer is formed in the conductive strips of storage unit, helps to reduce the series resistor between two storage units.Therefore, it is not required to string
Even the conductive strips of adjacent two storage unit carry out ion implantation doping, you can reduce the series resistor between storage unit.Together
When can solve known technology, and because using, the processing step caused by ion implantation doping process is complicated, heat budget increases and interference
The problem of memory component reads, programs and wipes.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention.Skill belonging to the present invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, protection scope of the present invention is subject to be defined depending on appended claims range.
Claims (9)
1. a kind of memory component, including：
One first conductive strips extend along a first direction；
One first accumulation layer extends along a second direction, Chong Die with first conductive strips, and first accumulation layer with this
The overlapping of one conductive strips defines one first memory block；
One first conductive columns extend along the second direction, and adjacent first accumulation layer, and heavy with first memory block
It is folded；
One first dielectric layer extends along the second direction, and adjacent first conductive strips, first accumulation layer and this first lead
Electric column；
One first conductive plunger extends along the second direction, and least partially overlapped with first conductive strips, and by this
One dielectric layer and electrically isolated with first conductive strips, first accumulation layer and first conductive columns；
One second dielectric layer extends along the second direction, and adjacent first conductive strips, first accumulation layer and this first lead
Electric column, and first conductive columns is made to be located between first dielectric layer and second dielectric layer；And
One second conductive plunger extends along the second direction, and by second dielectric layer and first conductive strips, this first
Accumulation layer and first conductive columns electrically isolate；
Wherein, first conductive plunger and second conductive plunger be arranged in parallel in adjacent two storage unit conductive columns it
Between, and it is least partially overlapped with the conductive strips for concatenating two storage units, and by dielectric layer by conductive plunger respectively with it is adjacent
The conductive strips of two storage units electrically isolate.
2. memory component according to claim 1, further includes：
One second accumulation layer extends along the second direction, and Chong Die with first conductive strips, and in second accumulation layer and is somebody's turn to do
First conductive strips overlapping defines one second memory block, and between second memory block and first memory block, has flat
One distance of the row first direction；And
One second conductive columns extend along the second direction, and it is adjacent and with the second storage area overlapping；Wherein, this first
It is to be electrically isolated by first dielectric layer between conductive plunger and second conductive columns.
3. memory component according to claim 2, further includes：
One second conductive strips extend along the first direction, and Chong Die with first accumulation layer and second accumulation layer, fixed respectively
Justice goes out a third memory block and one the 4th memory block, and first conductive columns and second conductive columns respectively with this
Three memory blocks and the 4th storage area overlapping；And
One insulating layer extends along the first direction, and between first conductive strips and second conductive strips.
4. memory component according to claim 3, further includes：
One first wordline extends along a third direction, and in electrical contact with first conductive columns；And
One second wordline extends along the third direction, and in electrical contact with second conductive columns；
Wherein, which is located between first wordline and second wordline, and with first wordline and this second
Wordline electrically isolates.
5. memory component according to claim 4, further includes：
One first dielectric plugs are located on first conductive plunger, and are contacted with first dielectric layer and first conductive plunger；
And
One second dielectric plugs are located on second conductive plunger, and are contacted with second dielectric layer and second conductive plunger.
6. memory component according to claim 4, further includes：
Multiple carinate multilayer laminated (ridged-shaped multi-layer stacks) is located on a base material, along this first
Direction extends, wherein each, these are carinate multilayer laminated, all include first conductive strips of a part, the insulating layer and this
Two conductive strips；
First accumulation layer and second accumulation layer are located at these carinate multilayer laminated defined grooves (trench)
In, and it is covered in the one side wall of the groove；
First conductive columns and second conductive columns are located among these grooves, are covered each by these the first storages
Layer and second accumulation layer；And
First wordline and second wordline are located at these carinate multilayer laminated tops.
7. memory component according to claim 1, further includes：
One second accumulation layer extends along the second direction, Chong Die with first conductive strips, and second accumulation layer with this
One conductive strips overlapping defines an active area；And
One second conductive columns, along the second direction extend, and with the active area overlapping, and with a serial selection line
(String Select Line, SSL) is connected.
8. memory component according to claim 1, further includes：
One second accumulation layer extends along the second direction, Chong Die with first conductive strips, and second accumulation layer with this
One conductive strips overlapping defines an active area；And
One second conductive columns, along the second direction extend, and with the active area overlapping, and with one ground connection selection line
(Ground Select Line, GSL) is connected.
9. a kind of production method of memory component, including：
In forming a multi-layer laminate structure (multi-layer stack) on a base material；
The multi-layer laminate structure is patterned, it is multiple carinate multilayer laminated to be formed；Wherein, it is each these it is carinate it is multilayer laminated at least
Extend along a first direction including a conductive strips；
In these it is carinate it is multilayer laminated between an at least groove a bottom and side wall on form a storage material layer；
In these one conductive material layers of carinate multilayer laminated upper formation, and fill up the groove；
The conductive material layer and the storage material layer are patterned, to form multiple through-holes among the groove, by a part of base
Material and the conductive strips are exposed to outer；Wherein, the patterned conductive material layer includes an at least conductive columns, and being located at should
In groove；The patterned storage material layer includes an at least accumulation layer, is located in the groove；And in the accumulation layer and the conduction
Band overlapping defines a memory block；
In these through-holes side wall and be exposed on the outer base material and form a dielectric layer；
Form multiple conductive plungers, respectively partially fill these through-holes, and make these conductive plungers at least with the conductive bar
Band part is overlapped；
In forming multiple dielectric plugs on these conductive plungers, to fill up these through-holes；And
The conductive material layer is patterned again, to form an at least wordline in these carinate multilayer laminated tops, along a third party
To extension, and it is in electrical contact with the conductive columns.
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| CN106992182B (en) * | 2017-04-24 | 2020-06-09 | 中国科学院微电子研究所 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN107068686B (en) * | 2017-04-24 | 2020-06-09 | 中国科学院微电子研究所 | Memory device, method of manufacturing the same, and electronic apparatus including the same |
| CN109075169A (en) | 2018-05-03 | 2018-12-21 | 长江存储科技有限责任公司 | Run through array contacts (TAC) for three-dimensional storage part |
| US20200119041A1 (en) * | 2018-10-16 | 2020-04-16 | Macronix International Co., Ltd. | Memory device and method for forming the same |
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