TWI549295B - High performance finfet - Google Patents

Description

High performance fin field effect transistor

The present application relates to semiconductor devices such as FinFETs (Fin Field Effect Transistors) (also known as tri-gate transistors).

A conventional field effect transistor (FET) is a substantially planar device having a gate structure extending across a surface of a semiconductor such as a single crystal germanium, and a doped source region and germanium in a semiconductor on both sides of the gate. Polar zone. The gate is insulated from the semiconductor by a thin layer of insulator such as hafnium oxide. The voltage applied to the gate controls the flow of current in the undoped channel extending between the doped source region and the drain region in the semiconductor under the gate.

The switching speed of the FET depends on the amount of current flowing between the source and drain regions. The current flow depends on the width of the gate, where the width is the direction perpendicular to the direction of current flow in the channel. With the ever-increasing demand for higher speed transistors for use in communications and computer equipment, there is continuing interest in fabricating transistor devices with wider gates.

FinFETs have been developed to achieve larger gate widths. The fin is a thin section of semiconductor material that is standing on the edge so that a plurality of surfaces for forming the gate structure can be obtained. The fins have a first major face and a second major face that are opposite each other and are generally symmetrical about a central face of the longitudinally divided fins. These main faces are generally shown as being parallel, for example as described in USP 7,612,405 B2, or the publication number US 2008/0128797 A1, which is incorporated herein by reference; The cross section of the fin is trapezoidal. In some cases, the two major faces intersect at the top. In some embodiments, a separate gate structure can be provided on each surface of each fin. In other embodiments, all surfaces have a common gate structure.

The doped source and drain regions are on opposite sides of the gate. as In a planar FET, the voltage applied to the gate controls the flow of current in the undoped channel extending between the doped source region and the drain region in the lower gate semiconductor.

More details about the FinFET can be found on pages 137-138 NHEWeste and D.Harris of ^{CMOS VLSI Design (Pearson, 3 rd} ed., 2005) , which is included herein by reference.

Although the increased speed is available from the 矽FinFET, it still needs Faster operation. This is obtained by using strain 矽 in the fin instead of 矽 or 矽锗 (SiGe) of the NMOS device and the PMOS device. However, the band gap ratio of germanium and SiGe is smaller, with the result that PMOS devices formed from these materials have significantly higher leakage currents (Iboff). The high leakage current not only increases static leakage, but also produces excessive heating of the semiconductor wafer in which the PMOS transistor is formed. This is especially troublesome in circuits that use a large number of PMOS transistors, such as static random access memory (SRAM) circuits.

The present invention is an integrated circuit for reducing power loss in a FinFET and a method of fabricating the same.

An exemplary FinFET of the present invention includes a plurality of first fins, a plurality of second fins, and a plurality of third fins, the FinFET having a gate structure formed on the fins and a source region and a drain region such that a PMOS transistor is formed at On the plurality of first fins, an NMOS transistor is formed on the plurality of second fins, and a PMOS transistor is formed on the plurality of third fins. In one embodiment, the plurality of first fins and the plurality of second fins are made of strain enthalpy; and the plurality of third fins are made of a material having a higher mobility than the strain enthalpy, such as ruthenium or iridium. . In a second embodiment, the plurality of first fins are made of tantalum, the plurality of second fins are made of strained tantalum, niobium or a group III-V compound; and the plurality of third fins are made of a higher specific strain The material of the hole mobility is made of, for example, tantalum or niobium.

There are several ways to form the fins of a FinFET. Illustratively, through the fin Forming a gate structure thereon, followed by ion implantation using an N-type dopant to form a source region and a drain region of the NMOS transistor, and ion implantation using a P-type dopant to form a source region of the PMOS transistor and The bungee region forms a transistor on the fin.

It has been found that the PMOS transistor formed on the strained skeletal fin The leakage current is as low as or even lower than one-fifth (1/15) of the leakage current of a similar PMOS transistor formed on a germanium or SiGe fin. One application of such PMOS transistors is in static RAM cells such as those used to store configuration bits for switching circuit and logic elements of a field programmable gate array (FPGA). In the current state of technology, such configuration memory may include millions of static RAM cells.

A large number of variations can be implemented in the preferred embodiment.

100‧‧‧Fin field effect transistor

110‧‧‧矽 substrate

120‧‧‧矽锗 strain relaxation obstruction

130‧‧‧First strained fin

140‧‧‧Second strained fin

150‧‧‧third fin

162‧‧‧Main face

164‧‧‧Main face

170‧‧‧ gate

180‧‧‧ source

190‧‧‧汲polar

200‧‧‧Fin field effect transistor

210‧‧‧矽 substrate

220‧‧‧ strain relaxation obstruction

222‧‧‧Part I

224‧‧‧Part II

230‧‧‧The first fin

240‧‧‧Second fin

250‧‧‧third fin

262‧‧‧Main face

264‧‧‧ main face

270‧‧‧ gate

280‧‧‧ source

290‧‧‧汲polar

310‧‧‧RAM

320‧‧‧One unit of RAM

321‧‧‧ PMOS transistor

322‧‧‧NMOS transistor

323‧‧‧PMOS transistor

324‧‧‧NMOS transistor

325‧‧‧NMOS transmission transistor

326‧‧‧NMOS transmission transistor

410‧‧‧Steps

420‧‧ steps

430‧‧ steps

440‧‧‧Steps

450‧‧‧Steps

460‧‧ steps

These and other objects and advantages of the present invention will be apparent to those skilled in the art in the <RTIgt; A perspective view of a second exemplary embodiment; a third diagram depicting a field programmable gate array and its configuration memory; a fourth diagram is a flow chart depicting an exemplary embodiment of the method of the present invention; and a fifth The figure is a graph depicting the electron and hole mobility of various semiconductor materials.

The first figure is a cross-sectional view of the first exemplary embodiment FinFET 100 of the present invention. The FinFET 100 includes a ruthenium substrate 110, a ruthenium strain relaxation inhibitor 120 formed on the ruthenium substrate 110, and a plurality of first responsiveness formed on the strain relaxation inhibitor 120. The skeg fin 130, a plurality of second strained fins 140 formed on the strain relaxation obstruction 120, and a plurality of semiconductor materials formed on the strain relaxation obstruction 120 and having a larger mobility than the strain 矽Third fin 150. Illustratively, the semiconductor material is tantalum or niobium. Each fin has two major faces 162, 164. A gate structure 170 and source and drain regions 180, 190 are formed on the surfaces of the fins 130, 140, and 150 such that a PMOS transistor is formed on the fin 130, an NMOS transistor is formed on the fin 140, and a PMOS transistor Formed on the fin 150.

The second figure is a second exemplary embodiment of the present invention FinFET 200 section. The FinFET 200 includes a germanium substrate 210, a strain relaxation barrier 220 formed on a portion of the substrate 210, a plurality of first fin fins 230 formed on the substrate 210, and a plurality of first fins 222 formed on the strain relaxation obstruction 220. Second strain 矽, 锗 or III-V compound such as fin 240 of InGaAs, and a semiconductor material formed on the second portion 224 of the strain relaxation barrier 220 by a large semiconductor material having a hole mobility greater than strain 矽A plurality of third fins 250. Illustratively, the semiconductor material is tantalum or niobium. Each fin has two major faces 262, 264. A gate structure 270 and source and drain regions 280, 290 are formed on the surfaces of the fins 230, 240, and 250 such that a PMOS transistor is formed on the fin 230, an NMOS transistor is formed on the fin 240, and a PMOS transistor Formed on the fin 250.

It has been found that the PMOS transistor formed on the strained skeletal fin The leakage current is as low as or even lower than one-fifth (1/15) of the leakage current of a similar PMOS transistor formed on a germanium or SiGe fin. One application of such a PMOS transistor is in, for example, a six-transistor static RAM cell for storing configuration bits of a configuration FPGA. The third diagram is a schematic diagram depicting FPGA 300, its configuration RAM 310, and a unit 320 of the configuration RAM. As shown in the third figure, the unit includes a latch having a first pair of series connected PMOS and NMOS cross-coupled with a second pair of PMOS and NMOS transistors 323, 324 connected in series. Transistors 321, 322, and NMOS transfer transistors 325, 326 for connecting the latches to bit lines bit and bit_b. Since the configuration RAM in today's technology may include millions of static RAM cells, the significant drop in leakage current of PMOS transistors used in such cells is of great value. For some For FPGA products, static power requirements are reduced by approximately thirty percent (30%); and total power demand is reduced by approximately ten percent (10%).

Advantageously, the NMOS transistor of the FinFET of the present invention can be used as an NMOS transistor in a static RAM cell in which the RAM 310 is configured.

There are many ways to form the fins of a FinFET. In some of these, fins are formed from the bulk material, using conventional photolithographic methods to remove unwanted material and leaving the final shape of the plurality of fins standing on the edge on the substrate. Typically the substrate is a wafer of germanium semiconductor material; and in today's technology, the wafer may reach a diameter of 12 inches (300 mm).

The fourth figure is a flow chart for fabricating the FinFET transistor shown in the first figure. The method begins with step 410 in which a plurality of fins are formed on the 矽锗 strain relaxation obstruction on the substrate bottom. The steps used to make such structures are well known in the art. At step 420, a gate structure extending across the fin is formed in a direction substantially perpendicular to the ridges and valleys of the fin. Methods for forming such gate structures are well known. At step 430, a first mask is formed over portions of the FinFET to which the PMOS transistors 130 and 150 are to be placed. Next, in step 440, an N-type source and a drain region are formed on the main surface of the fin on the side of the gate not protected by the first mask by ion implantation of an N-type dopant such as arsenic, thereby forming NMOS transistor 140. The first reticle is then removed and at step 450, a second reticle is formed over the portion of the FinFET in which the N-type source and drain regions are formed. Next, at step 460, a P-type source and a drain region are formed on the main surface of the fin on the side of the gate not protected by the second mask by ion implantation of a P-type dopant such as boron, thereby forming PMOS transistors 130, 150. The second mask is then removed.

Numerous variations can be made within the spirit and scope of the invention, as will be apparent to those skilled in the art. For example, a large amount of semiconductor material can be used in the practice of the present invention. The fifth panel is a graph depicting the relationship between electron and hole mobility and band gap for ruthenium, osmium, and various III-V compounds. These materials include large compounds having a hole mobility ratio 矽 that can be used in the practice of the present invention, such as gallium antimonide (GaSb) and indium antimonide (InSb). These materials also include those having a higher electron mobility than 矽 which can be used in the practice of the present invention. Compounds such as GaSb, InSb, indium arsenide (InAs), and indium gallium arsenide (InGaAs). Many other III-V compounds not indicated in the figures but well known in the art can also be used. Although a method of forming a FinFET is described, other methods can be used; and a large number of variations in these methods can also be implemented. Different materials can be used as cap layers, photomask layers, etc.; and a wide variety of etchants and etching methods can be used to remove these materials.

100‧‧‧Fin field effect transistor

110‧‧‧矽 substrate

120‧‧‧矽锗 strain relaxation obstruction

130‧‧‧First strained fin

140‧‧‧Second strained fin

150‧‧‧third fin

162‧‧‧Main face

164‧‧‧Main face

170‧‧‧ gate

180‧‧‧ source

190‧‧‧汲polar

Claims (20)

A fin field effect transistor (FinFET) comprising: a plurality of first fins, the first fins having opposite first and second main faces, and being made of a first semiconductor material; at least one a PMOS transistor formed on the first main surface and the second main surface of the first fin; a plurality of second fins, the second fin having opposite third main surfaces and a fourth main surface, and made of the first semiconductor material; at least one first NMOS transistor formed on the third main surface and the fourth main surface of the second fin; a plurality of third a fin, the third fin having a fifth major surface and a sixth major surface, and being made of a second semiconductor material having a hole migration greater than a strain 矽 hole mobility And a second PMOS transistor formed on the fifth main surface and the sixth main surface of the third fin. The FinFET of claim 1, wherein the first semiconductor material is a strain enthalpy. The FinFET of claim 2, wherein the first fin, the second fin, and the third fin are formed on a 矽锗 strain relaxation obstruction formed on a ruthenium substrate. The FinFET of claim 2, wherein the semiconductor material having a hole mobility greater than a strain 矽 hole mobility is 锗 or 矽锗. The FinFET of claim 2, wherein the semiconductor material having a hole mobility greater than the mobility of the strain 矽 is a III-V compound. The FinFET of claim 5, wherein the III-V compound is indium antimonide or gallium antimonide. The FinFET of claim 1, wherein the opposing first major surface and second major surface are substantially parallel, the opposing third major surface and the fourth major surface are substantially parallel, and the opposing The fifth major surface and the sixth major surface are substantially parallel. A fin field effect transistor (FinFET) comprising: a substrate; at least one first fin formed on the germanium substrate, the fins having opposite first and second main faces; at least one first MOS transistor formed at the first a first main surface and a second main surface of the fin; a strain relaxation obstruction formed on the crucible substrate in which the first fin is not formed; at least one second fin formed in the On the strain relaxation obstruction, the second fin has opposite third major faces and fourth major faces and is made of a first semiconductor material having a higher electron mobility than erbium; at least one NMOS a crystal formed on the third main surface and the fourth main surface of the second fin; at least one third fin formed on the strain relaxation obstruction, the third fin having a relative a fifth major surface and a sixth major surface and made of a second semiconductor material having a mobility of a hole having a larger mobility than a hole of the crucible; and at least one PMOS transistor formed in the third fin a fifth main surface and the sixth main surface. The FinFET of claim 8, wherein the first semiconductor material having an electron mobility greater than the electron mobility of ruthenium is a ruthenium, osmium, or III-V compound. The FinFET of claim 8, wherein the second semiconductor material having a hole mobility greater than a hole mobility of ruthenium is a ruthenium, osmium, or III-V compound. The FinFET of claim 8, wherein the first MOS transistor is a PMOS transistor. The FinFET of claim 8, wherein the first MOS transistor is an NMOS transistor. The FinFET of claim 8, comprising a plurality of first fins, a plurality of second fins, and a plurality of third fins. A method for forming a fin field effect transistor (FinFET) structure, comprising: forming a plurality of first thin segments of a first semiconductor material, each segment having an opposite first a major surface and a second major surface; forming a plurality of second thin segments of the second semiconductor material, each segment having opposing third major faces and fourth major faces; forming a gate on the thin segments; Injecting ions of a first conductivity type into a plurality of first thin segments of the first semiconductor material; and implanting a first conductivity type ion in the plurality of second thin segments of the second semiconductor material In at least one thin section of the first semiconductor material, ions of the second conductivity type are implanted. The method of claim 14, wherein the first semiconductor material has an electron mobility that is different from an electron mobility of the second semiconductor material. The method of claim 14, wherein the first semiconductor material is stress 矽, and the second semiconductor material is 锗, 矽 having a hole mobility greater than a hole mobility of 矽锗, or a III-V compound. The method of claim 16, wherein the group III-V compound is indium antimonide or gallium antimonide. The method of claim 14, wherein the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity. The method of claim 14, wherein the plurality of first thin segments and the plurality of second thin segments are formed on a strain relaxation obstruction formed on a tantalum substrate. A fin field effect transistor (FinFET) comprising: the first fin having opposite first main faces and second main faces, and being made of a first semiconductor material; at least one first PMOS transistor formed On the first main surface and the second main surface of the first fin; a plurality of second fins, the second fins having opposite third main surfaces and fourth main surfaces, and The first semiconductor material is formed; at least one first NMOS transistor is formed on the third main surface and the fourth main surface of the second fin; a plurality of third fins, the first a triple fin having a fifth major surface and a sixth major surface And being made of a second semiconductor material having a hole mobility greater than a strain 矽 hole mobility; and at least one second PMOS transistor formed at the third fin The fifth main surface and the sixth main surface, wherein the first semiconductor material is a strain enthalpy, wherein the first fin, the second fin, and the third fin are formed on a germanium substrate The 矽锗 strain is relaxed on the obstruction.