JP2006210453A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the driving ability of a transistor by optimizing the lay out of the active region of the transistor, the source and drain length (X) from an active edge in the drain to a gate edge. <P>SOLUTION: It is a semiconductor device 1 in which a plurality of NMOS transistors 21 are arranged in the direction of a gate length of a transistor and a plurality of PMOS transistors 41 are arranged in the direction of the gate length of the transistor and a plurality of PMOS transistors 41 are arranged by a column other than the column in which the above NMOS transistors 21 are arranged. The active region 22 of the plurality of the NMOS transistors 21 is set to one formed in the direction of the gate length of the above NMOS transistor 21 from the active region. A shield gate 61 is formed between the above NMOS transistors 21, and the plurality of the PMOS transistors 41 each has an active region 42 separated every PMOS transistor 41. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that can easily improve the capability of a MOS transistor.

  As the degree of integration increases, conventionally, the gate oxide film (Tox) is thinned, the threshold voltage (Vth) is set to a low voltage, and the gate length (L) is reduced to optimize the MOSFET according to the generation. I have been trying to improve my ability, but when it comes to the 65nm generation and beyond, that rule of thumb is no longer valid and it becomes difficult to improve my ability. Since the gate oxide thickness reaches below 1.5 nm, an increase in the gate tunnel current becomes a device problem, and the gate oxide thickness is almost the same as the natural oxide thickness. The formation of the thin gate oxide film itself is difficult. With regard to Vth, an increase in off current (Ioff) due to a decrease in Vth is immediately effective as an increase in standby current (Istb) of the LSI. It is becoming more and more important to control the variation in gate length (L), which is the main factor in increasing the current (Ioff). Therefore, it is difficult to improve the capacity on the conventional extension line, and it is necessary to realize the capacity improvement by a new method.

  In addition, it has been known that MOSFET characteristics change due to STI stress after STI (Shallow Trench Isolation) is used for element isolation, and since the 90 nm generation, the amount of change has been affected to a degree that cannot be ignored. ing. In particular, the influence of the source and drain length (X) from the active end to the gate end of the source and drain of the transistor is large in design. When X is small, the stress increases and the mobility fluctuates. The PMOSFET changes to increase its capacity. This amount of fluctuation has increased to the extent that it accounts for 10% or more of the whole, and has an effect on the device performance of the LSI (see, for example, Non-Patent Documents 1 and 2).

  An example of a conventional flip-flop circuit using a PMOS transistor and an NMOS transistor will be described with reference to a plan layout diagram of FIG.

  As shown in FIG. 9, the drain line (Vdd) power supply line 111 and the source voltage (Vss) ground line 112 are arranged in the row direction (x direction) with each NMOS transistor (NMOSFET) 121 and each PMOS transistor (PMOSFET) 141 interposed therebetween. ). Further, the gate electrode 123 of each NMOS transistor and the gate electrode 143 of each PMOS transistor are laid out with one wiring in the vertical (y) direction. A flip-flop circuit 105 is formed by wiring a set of NMOS transistors 121 and 121 and a set of PMOS transistors 141 and 141 arranged in the vertical direction. Here, the ratio of the gate width (W) length between the NMOS transistor 121 and the PMOS transistor 141 is laid out in a ratio of 1: 2, and the NMOS transistor 121 is located on the upper side of the drawing near the ground line 112, and the drawing is located near the power supply line 111. A PMOS transistor 141 is disposed on the lower side. A plurality of the flip-flop circuits 105 are arranged in the row (x) direction.

  The active areas 122 and 142 are separated between the flip-flop circuits 105. In one flip-flop circuit 105, two gate electrodes 123 (123a) and 123 (123b) are laid out on the active region 122, and two gate electrodes 143 (143a) and 143 (143b) are formed on the active region 142. ), A power line 111 is connected to the active region 142 between the gate electrodes 143a and 143b, and a ground line 112 is connected to the active region 122 between the gate electrodes 123a and 123b. The extraction parts 124a, 144a (124b, 144b) located on both sides of each active region 122, 142 are gate electrodes 123b, 143b (123a, 143a) located on the opposite side of the extraction parts 124a, 144a (124b, 144b). ) To form a flip-flop circuit 105. At this time, the NMOS transistor 121 and the PMOS transistor 141 have basically the same layout except that there is a difference in gate width (W), and the drawings in which the flip-flop circuits 105 are regularly arranged are shown. Show. This is the basic layout of the flip-flop circuit in the SRAM memory cell.

Victor Chan, Rajesh Rengarajan, Nivo Rovedo, Wei Jin, Terence Hook, Phung Nguyen, Jia Chen, Ed Nowak, Xiang-Dong Chen, Dallas Lea, Ashima Chakravarti, Victor Ku, Sam Yang, An Steegen, Christopher Baiocco, Padraic Shafer, Hung Ng, Shih-Fen Huang, Clement Wann, "High Speed 45nm Gate Length CMOSFETs Integrated Into a 90nm Bulk Technology Incorporating Strain Engineering" 2003 IEEE 2003 Co-authored by Gregory Scott, Jeffrey Lutze, Mark Rubin, Faran Nouri, and Martin Manley `` NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress '' 1999 IEEE 1999

  The problem to be solved is that there is a limit to improving the capability of the transistor in the conventional extended war, so that the gate oxide film (Tox) is thinned and the threshold voltage (Vth) is set to a low voltage as in the prior art. However, the optimization of the reduction of the gate length (L) or the like cannot improve the capability of the MOSFET according to the generation. In addition, the fluctuation of MOSFET characteristics due to the stress of STI used for element isolation cannot be ignored. In particular, the influence of the source and drain length (X) from the active end to the gate end of the source and drain of the transistor is in terms of design. When X is small and stress is increased, the mobility fluctuates, and the capability of the PMOSFET is improved, but the capability of the NMOSFET is decreased.

  In the first semiconductor device of the present invention, a plurality of NMOS transistors are arranged in the gate length direction of the transistors, and a plurality of PMOS transistors are arranged in a row different from the row in which the NMOS transistors are arranged. In the semiconductor device, an active region of the plurality of NMOS transistors includes one active region formed in a gate length direction of the transistors, a shield gate is provided between the NMOS transistors, and the plurality of NMOS transistors The PMOS transistor is characterized by having an active region separated for each PMOS transistor.

  In the second semiconductor device of the present invention, a plurality of NMOS transistors are arranged in the gate length direction of the transistors, and a plurality of PMOS transistors are arranged in a row different from the row in which the NMOS transistors are arranged. In the semiconductor device, the NMOS transistors arranged in the row direction include two NMOS transistors as a set, each set having one active region, and the active regions of each set are separated from each other. The plurality of PMOS transistors have an active region for each PMOS transistor, and the active region of the NMOS transistor is formed such that the length from the active region end to the gate end in the row direction is the maximum length of the design rule. Active region of the PMOS transistor , The most important feature that the length to the gate terminal from the active region edge in the row direction is formed in the minimum length of the design rule.

  In the first semiconductor device of the present invention, the active region of the plurality of NMOS transistors is formed of one active region formed in the gate length direction of the transistor, and the plurality of PMOS transistors has an active region for each PMOS transistor. Since the source and drain length (X) from the active end to the gate end of the source and drain of the NMOS transistor can be maximized, the STI structure is used for element isolation to reduce the cell area. However, it is possible to suppress a decrease in the capacity of the NMOS transistor, and there is an advantage that the mobility can be improved as compared with the conventional one. Also, since each PMOS transistor has an active region, the source and drain length (X) from the active end to the gate end of the source and drain of the PMOS transistor can be minimized, so that the capability of the PMOS transistor can be reduced. There is an advantage that it can be improved. In addition, since the first semiconductor device is provided with the shield gate between the NMOS transistors, charge transport between the NMOS transistors does not occur, so that an independent circuit, for example, a flip-flop circuit, is formed between the shield gates. Can do.

  In the second semiconductor device of the present invention, the NMOS transistors arranged in the row direction have two NMOS transistors as one set, each set has one active region, and the active regions of each set are separated. The active region of this NMOS transistor has a length from the active region end to the gate end in the row direction that is the maximum length of the design rule, so the cell area is reduced by adopting the STI structure for element isolation. Even if the reduction is achieved, there is an advantage that the capability reduction of the NMOS transistor can be suppressed and the mobility can be improved as compared with the conventional one. The plurality of PMOS transistors have an active region for each PMOS transistor, and the active region of the PMOS transistor is formed such that the length from the active region end to the gate end in the row direction is the minimum length of the design rule. Therefore, there is an advantage that the capability of the PMOS transistor can be improved. In addition, since two NMOS transistors are made into one set, each set has one active region, and since the active regions of each set are separated, charge transport does not occur between each set of NMOS transistors. An independent circuit such as a flip-flop circuit can be configured for each group.

  The purpose of improving the driving capability of the transistor is to optimize the layout of the active region of the transistor and the source and drain length (X) from the active end to the gate end of the source and drain without changing the process. It was realized only by changing the design.

  An embodiment according to the first semiconductor device of the present invention will be described with reference to a plan layout diagram of FIG. FIG. 1 shows a basic layout of a flip-flop circuit in an SRAM memory cell as an example.

  As shown in FIG. 1, the power supply line 11 for the drain voltage (Vdd) and the ground line 12 for the source voltage (Vss) are arranged in the row direction across a plurality of NMOS transistors (NMOSFET) 21 and a plurality of PMOS transistors (PMOSFET) 41. They are arranged in the (x direction).

  In addition, a plurality of NMOS transistors (NMOSFET) 21 and a plurality of PMOS transistors (PMOSFET) 41 provided between the power supply line 11 and the ground line 12 are arranged such that the arrangement of the NMOS transistors 21 is aligned with the power supply line 11 side. Thus, the PMOS transistors 41 are arranged along the ground line 12 side.

  The active region 22 of the NMOS transistor 21 is formed as one active region in the gate length direction (row direction) of the transistor. Therefore, the active region 22 is formed such that the length X from the active region end to the gate end in the row direction of each NMOS transistor 21 is the maximum length of the design rule. The NMOS transistors 21 arranged in the row direction share the active region 22 between the two NMOS transistors 21 and 21 with the two NMOS transistors 21 as a set.

  The active region 42 of the PMOS transistor 41 is formed for each PMOS transistor 41. Therefore, each active region 42 of the PMOS transistor 41 can be formed with a minimum length of the design rule from the active region end to the gate end in the row direction.

  The active regions 22 and 42 are electrically isolated from each other by an element isolation region. This element isolation region is formed, for example, in an STI (Shallow Trench Isolation) structure.

  The gate electrode 23 of each NMOS transistor and the gate electrode 43 of each PMOS transistor are arranged in the column direction (y direction). The gate electrodes 23 and 43 arranged in the y direction are formed of one gate electrode. Here, the ratio of the gate widths (W) of the gate electrodes 23 and 43 is laid out in a 1: 2 layout.

  The flip-flop circuit 5 is composed of two adjacent NMOS transistors 21 and two adjacent PMOS transistors 42. An array of NMOS transistors 21 is arranged on the upper side of the drawing near the ground line 12, and an arrangement of PMOS transistors 41 is arranged on the lower side of the drawing near the power supply line 11. A plurality of the flip-flop circuits 5 are arranged in the row (x) direction.

  In one flip-flop circuit 5, two gate electrodes 23a and 23b and two gate electrodes 43a and 43b are laid out on the active regions 22 and 42, and the gate power supplies 23a and 43a are formed by one gate electrode. The gate power supplies 23b and 43b are composed of one gate electrode. The active region 22 between the gate electrodes 43a and 43b is shared by the adjacent NMOS transistor 21, and the ground line 12 is connected thereto. A common power line 11 is connected to the independent active regions 42a and 42b between the gate electrodes 23a and 23b. Accordingly, with respect to the contacts, the PMOS transistor 41 side extracts the source and drain for each of the left and right transistors, and the power supply from the power supply line 11 is also wired to each source region. In addition, extraction portions 24a and 44a are provided in the active regions 22a and 42a located between the gate electrodes 23a and 23b and on the outer side between the gate electrodes 43a and 43b, and the extraction portions 24a and 44a are connected to each other. In addition, it is connected to gate electrodes 23b and 43b located on the opposite side. Similarly, extraction portions 24b and 44b are provided in the active regions 22b and 42b located between the gate electrodes 23a and 23b and the other outside between the gate electrodes 43a and 43b, and the extraction portions 24b and 44b are connected to each other. And connected to gate electrodes 23a and 43a located on the opposite side. Thus, the flip-flop circuit 5 is configured.

  Since one flip-flop circuit 5 has an active region 42 for every two PMOS transistors 41, STI isolation is introduced into the space between the gate electrodes 43a and 43b. Therefore, the space between the gates is slightly wider than the formation region of the NMOS transistor.

  Further, a shield gate 61 is provided so as to cross only the active region 22 of the NMOS transistor 21 between the flip-flop circuits 5 and 2. In other words, the shield gate 61 is disposed between each pair of two NMOS transistors among the NMOS transistors arranged in the row direction. The ground line 12 is connected to the shield gate 61.

  Therefore, there is a difference between the gate width (W) of the gate electrode 23 of the NMOS transistor 21 and the gate width (W) of the gate electrode 43 of the PMOS transistor 41, and the active region 22 of the NMOS transistor 21 and the active region 42 of the PMOS transistor 41. The layout is basically the same as the conventional circuit configuration except that there is a difference between them and the shield gate 61 is provided.

  Next, FIG. 2 and FIG. 3 are used to explain the experimental results of the capability variation (relation between the on-current Ion and the threshold voltage Vth) of the single MOSFET depending on the source and drain length (X). FIG. 2 shows an NMOS transistor, and FIG. 3 shows a PMOS transistor.

  As shown in FIGS. 2 and 3, the comparison was made with the source and drain lengths X = 0.24 μm and X = 2 μm from the active region end to the gate electrode end. When X = 2 μm was reduced to 0.24 μm, the on-current (Ion) of the NMOS transistor was reduced by 17%. On the other hand, in the PMOSFET, when X = 2 μm is reduced to 0.24 μm, the on-current (Ion) is increased by 8%. As can be seen from this result, it is preferable for the NMOS transistor to be laid out in the direction in which the source and drain lengths (X) become longer in order to improve the transistor performance, and the PMOS transistor is laid out in the direction in which the source and drain lengths (X) become shorter. It can be seen that it is preferable to improve the transistor capability. With this layout, the NMOS transistor is in a stress-relieved state and the PMOS transistor is in a stress-strengthened state, so that the mobility is increased, and the current capability of both is about 10% larger than the conventional one. As a result, the operation speed of the device is increased.

  Next, FIG. 4 shows changes in the threshold voltage Vth in the NMOS transistor in the range of source and drain lengths: X = 0.23 μm to X = 10 μm, and ON in the range of X = 0.23 μm to X = 10 μm. The change of the current Ion is shown in FIG. FIG. 6 shows the change of the threshold voltage Vth in the range of the source and drain lengths: X = 0.23 μm to X = 10 μm in the PMOS transistor, and the on-current in the range of X = 0.23 μm to X = 10 μm. The change of Ion is shown in FIG. Here, X = 10 μm is a size that eliminates the influence of STI (Shallow Trench Isolation) stress, and X = 0.23 μm is an X dependency that can occur in the 90 nm generation design rule (fluctuation in MOSFET characteristics due to STI stress). The minimum value in the 90 nm generation design rule.

  As shown in FIGS. 4 to 7, when the source / drain length X is reduced from 10 μm toward X = 0.23 μm, the threshold voltage Vth increases by 35 mV in the NMOS transistor, and the on-current Ion is It decreased by 18%. In the PMOS transistor, the threshold voltage Vth increased by 33 mV, and the on-current Ion decreased by 12%. In addition, as the generation progresses (the value of X becomes further smaller), the variation amount becomes larger. Furthermore, the smaller X is, the greater the influence of stress is, and the characteristic variation amount of the MOS transistor becomes more prominent as X is smaller.

  In the first embodiment, the active region 22 of the NMOS transistor 21 is formed as one active region in the gate length direction (row direction) of the transistor, so that the active region 22 is active in the row direction of each NMOS transistor 21. The length X from the region end to the gate end is formed to the maximum length of the design rule. Therefore, the current capability of the NMOS transistor 21 can be improved. Further, by forming the active region 42 of the PMOS transistor 41 for each PMOS transistor 41, the length from the active region end to the gate end in the row direction of each PMOS transistor 41 is set to the minimum length of the design rule. Can be done. Therefore, the current capability of the PMOS transistor 41 can be improved.

  In the first semiconductor device, since the shield gate 61 is provided between the flip-flop circuits 5 in the arrangement of the NMOS transistors 21, charge transport between the flip-flop circuits 5 does not occur. Thus, a flip-flop circuit can be configured.

  Next, an embodiment of the second semiconductor device according to the present invention will be described with reference to the plan layout diagram of FIG. FIG. 8 shows a basic layout of the flip-flop circuit in the SRAM memory cell as an example.

  As shown in FIG. 8, the power supply line 11 for the drain voltage (Vdd) and the ground line 12 for the source voltage (Vss) are arranged in the row direction across a plurality of NMOS transistors (NMOSFET) 21 and a plurality of PMOS transistors (PMOSFET) 41. They are arranged in the (x direction).

  In addition, a plurality of NMOS transistors (NMOSFET) 21 and a plurality of PMOS transistors (PMOSFET) 41 provided between the power supply line 11 and the ground line 12 are arranged such that the arrangement of the NMOS transistors 21 is aligned with the power supply line 11 side. Thus, the PMOS transistors 41 are arranged along the ground line 12 side.

  The NMOS transistor 21 has two NMOS transistors 21 as a set in the gate length direction (row direction) of the transistor, each set has one active region 22, and the active regions 22 in each set are separated. Yes. Moreover, the active region 22 is formed such that the length X from the active region end to the gate end in the row direction is the maximum length of the design rule. A set of NMOS transistors arranged in the row direction shares an active region 22 between the NMOS transistors 21 and 21.

  The active region 42 of the PMOS transistor 41 is formed for each PMOS transistor 41. Therefore, each active region 42 of the PMOS transistor 41 can be formed with a minimum length of the design rule from the active region end to the gate end in the row direction.

  The active regions 22 and 42 are electrically isolated from each other by an element isolation region. This element isolation region is formed, for example, in an STI (Shallow Trench Isolation) structure.

  The gate electrode 23 of each NMOS transistor and the gate electrode 43 of each PMOS transistor are arranged in the column direction (y direction). The gate electrodes 23 and 43 arranged in the y direction are formed of one gate electrode. Here, the ratio of the gate widths (W) of the gate electrodes 23 and 43 is laid out in a 1: 2 layout.

  The flip-flop circuit 5 is composed of two adjacent NMOS transistors 21 and two adjacent PMOS transistors 42. An array of NMOS transistors 21 is arranged on the upper side of the drawing near the ground line 12, and an arrangement of PMOS transistors 41 is arranged on the lower side of the drawing near the power supply line 11. A plurality of the flip-flop circuits 5 are arranged in the row (x) direction.

  In one flip-flop circuit 5, two gate electrodes 23a and 23b and two gate electrodes 43a and 43b are laid out on the active regions 22 and 42, and the gate power supplies 23a and 43a are formed by one gate electrode. The gate power supplies 23b and 43b are composed of one gate electrode. The active region 22 between the gate electrodes 43a and 43b is shared by the adjacent NMOS transistor 21, and the ground line 12 is connected thereto. A common power line 11 is connected to the independent active regions 42a and 42b between the gate electrodes 23a and 23b. Accordingly, with respect to the contacts, the PMOS transistor 41 side extracts the source and drain for each of the left and right transistors, and the power supply from the power supply line 11 is also wired to each source region. Further, the active regions 22 and 42 located between the gate electrodes 23a and 23b and on the outer side between the gate electrodes 43a and 43b are provided with extraction portions 24a and 44a, and the extraction portions 24a and 44a are connected to each other. In addition, it is connected to gate electrodes 23b and 43b located on the opposite side. Similarly, the active regions 22 and 42 located between the gate electrodes 23a and 23b and the other outside between the gate electrodes 43a and 43b are provided with extraction portions 24b and 44b, and the extraction portions 24b and 44b are connected to each other. And connected to gate electrodes 23a and 43a located on the opposite side. Thus, the flip-flop circuit 5 is configured.

  Since one flip-flop circuit 5 has an active region 42 for every two PMOS transistors 41, STI isolation is introduced into the space between the gate electrodes 43a and 43b. Therefore, the space between the gates is slightly wider than the formation region of the NMOS transistor.

  Therefore, there is a difference between the gate width (W) of the gate electrode 23 of the NMOS transistor 21 and the gate width (W) of the gate electrode 43 of the PMOS transistor 41, and the active region 22 of the NMOS transistor 21 and the active region 42 of the PMOS transistor 41. The layout is basically the same as the conventional circuit configuration except that there is a difference.

  In the second embodiment, the NMOS transistors 21 arranged in the row direction have two NMOS transistors 21 as one set, each set has one active region 22, and each set of active regions 22 is separated. The active region 22 of the NMOS transistor 21 has a length from the active region end to the gate end in the row direction that is the maximum length of the design rule. Even if the area is reduced, the current capability (on current Ion) of the NMOS transistor 21 can be prevented from being lowered, and there is an advantage that the mobility can be improved compared to the conventional one. Each of the PMOS transistors 41 has an active region 42 for each PMOS transistor 41, and the active region 42 of the PMOS transistor 41 has a minimum length of the design rule from the active region end to the gate end in the row direction. Therefore, there is an advantage that the current capability (ON current Ion) of the PMOS transistor 41 can be improved. Therefore, the operation speed can be improved. In addition, since two NMOS transistors 21 are set as one set, each set has one active region 22, and the active regions 22 of each set are separated from each other, so that charge transport is performed between the sets of NMOS transistors 21. Since this does not occur, an independent circuit such as a flip-flop circuit 5 can be configured for each group.

  Further, unlike the first semiconductor device 1, the second semiconductor device 2 does not have a shield gate, and thus has a structure that is less susceptible to noise.

  In the semiconductor devices 1 and 2, it is possible to improve the current capability of about 17% for the NMOS transistor 21 and about 8% for the PMOS transistor 41 as a single transistor by changing the layout design without changing the manufacturing process. In addition, the flip-flop circuit 5 can improve the current capability by about 10%. Further, by applying the flip-flop circuit 5 to an SRAM flip-flop, it is possible to contribute to an increase in memory access speed.

  The semiconductor device of the present invention is preferably applied to various integrated circuit devices composed of NMOS transistors and PMOS transistors, particularly SRAM.

FIG. 3 is a plan layout view showing an embodiment of the first semiconductor device of the present invention. FIG. 6 is a relationship diagram between an on-current Ion and a threshold voltage Vth of an NMOS transistor using the source and drain lengths X as parameters. FIG. 4 is a relationship diagram between an on-current Ion of a PMOS transistor and a threshold voltage Vth using a source / drain length X as a parameter. It is a relationship diagram between the source and drain length X of the NMOS transistor and the threshold voltage Vth. FIG. 5 is a relationship diagram between source and drain lengths X of an NMOS transistor and an on-current Ion. FIG. 4 is a relationship diagram between a source / drain length X of a PMOS transistor and a threshold voltage Vth. FIG. 5 is a relationship diagram between a source / drain length X of a PMOS transistor and an on-current Ion. It is the plane layout figure which showed one Example which concerns on the 2nd semiconductor device of this invention. It is the plane layout figure which showed an example of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 21 ... NMOS transistor, 22, 42 ... Active region, 41 ... PMOS transistor, 61 ... Shield gate

Claims (13)

A semiconductor device in which a plurality of NMOS transistors are arranged in the gate length direction of the transistors, and a plurality of PMOS transistors are arranged in a row different from the row in which the NMOS transistors are arranged,
The active region of the plurality of NMOS transistors is composed of one active region formed in the gate length direction of the transistors,
A shield gate is provided between the NMOS transistors,
The semiconductor device, wherein the plurality of PMOS transistors have active regions separated for each PMOS transistor. 2. The semiconductor device according to claim 1, wherein the NMOS transistors arranged in the row direction include two NMOS transistors as a set, and the shield gate is disposed between the sets. 2. The semiconductor device according to claim 1, wherein the active region of the NMOS transistor is formed such that a length from an active region end to a gate end in the row direction is a maximum length of a design rule. 2. The semiconductor device according to claim 1, wherein the active region of the PMOS transistor is formed such that a length from an active region end to a gate end in the row direction is a minimum length of a design rule. 2. The semiconductor device according to claim 1, wherein the NMOS transistors arranged in the row direction share an active region between the two NMOS transistors by setting two adjacent NMOS transistors as a set. . The semiconductor device according to claim 1, wherein the PMOS transistors arranged in the row direction have source and drain contacts for each PMOS transistor. The semiconductor device according to claim 1, wherein a flip-flop circuit is configured by the two adjacent NMOS transistors and the two adjacent PMOS transistors. The semiconductor device according to claim 7, wherein the shield gate is provided between the flip-flop circuits in the arrangement of the NMOS transistors arranged in the row direction. The semiconductor device according to claim 1, wherein each active region is separated by shallow trench isolation. A semiconductor device in which a plurality of NMOS transistors are arranged in the gate length direction of the transistors, and a plurality of PMOS transistors are arranged in a row different from the row in which the NMOS transistors are arranged,
The NMOS transistors arranged in the row direction have two NMOS transistors as one set, each set has one active region, and the active regions of each set are separated,
The plurality of PMOS transistors have an active region for each PMOS transistor,
The active region of the NMOS transistor is formed such that the length from the active region end to the gate end in the row direction is the maximum length of the design rule,
The active region of the PMOS transistor is formed such that the length from the active region end to the gate end in the row direction is the minimum length of the design rule. The semiconductor device according to claim 10, wherein the PMOS transistors arranged in the row direction have source and drain contacts for each PMOS transistor. The semiconductor device according to claim 10, wherein a flip-flop circuit is configured by two adjacent NMOS transistors of the NMOS transistors and two adjacent PMOS transistors of the PMOS transistors. The semiconductor device according to claim 10, wherein each active region is separated by shallow trench isolation.

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