TWI547948B - Memory device and programming method thereof - Google Patents
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Description
本發明是有關於一種記憶體裝置與其程式化方法,且特別是有關於一種平面式記憶體裝置與其程式化方法。 The present invention relates to a memory device and a stylized method thereof, and more particularly to a planar memory device and a stylized method thereof.
非揮發性記憶體的種類甚多,目前又以快閃記憶體(flash memory)為主流商品。現有的快閃記憶體大多採用非平面式(non-planar)結構,以藉此增加閘極耦合率(gate-coupling ratio,簡稱GCR)。此外,隨著記憶胞的尺寸逐漸地縮減,快閃記憶體可能需採用平面式(planar)結構來加以實現。然而,平面式快閃記憶體(planar flash memory)具有較低的閘極耦合率。因此,現有的程式化方法應用在平面式快閃記憶體時往往會導致平面式快閃記憶體的程式化速度大幅地下降。 There are many types of non-volatile memory, and currently flash memory is the mainstream product. Most existing flash memories use a non-planar structure to increase the gate-coupling ratio (GCR). In addition, as the size of the memory cell is gradually reduced, the flash memory may need to be implemented using a planar structure. However, planar flash memory has a lower gate coupling ratio. Therefore, the existing stylized method used in flat flash memory tends to cause the stylized speed of the planar flash memory to drop drastically.
本發明提供一種記憶體裝置與其程式化方法,用以提升記憶體裝置的程式化速度。 The present invention provides a memory device and a stylized method for increasing the stylized speed of a memory device.
本發明提出一種記憶體裝置的程式化方法。其中,記憶體裝置包括相互串接的第一電晶體、記憶胞串與第二電晶體,記憶胞串包括目標記憶胞、與目標記憶胞相鄰的第一與第二周邊記憶胞以及與目標記憶胞不相鄰的多個非目標記憶胞,且記憶體裝置的程式化方法包括下列步驟。導通第一電晶體並關閉第二電晶體。利用傳遞電壓開啟所述多個非目標記憶胞,並利用輔助電壓開啟第一周邊記憶胞與第二周邊記憶胞。以及,利用程式化電壓對目標記憶胞進行程式化。其中,輔助電壓大於傳遞電壓,且輔助電壓小於程式化電壓。 The present invention proposes a stylized method of a memory device. The memory device includes a first transistor, a memory cell string and a second transistor connected in series, and the memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a target The plurality of non-target memory cells that are not adjacent to the memory cell, and the stylized method of the memory device includes the following steps. The first transistor is turned on and the second transistor is turned off. The plurality of non-target memory cells are turned on by the transfer voltage, and the first peripheral memory cells and the second peripheral memory cells are turned on by the auxiliary voltage. And, stylize the target memory cell with a stylized voltage. Wherein, the auxiliary voltage is greater than the transfer voltage, and the auxiliary voltage is less than the stylized voltage.
本發明還提出一種記憶體裝置,包括記憶體陣列與電路。記憶體陣列包括相互串接的第一電晶體、記憶胞串與第二電晶體,且記憶胞串包括目標記憶胞、與目標記憶胞相鄰的第一與第二周邊記憶胞、以及與目標記憶胞不相鄰的多個非目標記憶胞。電路電性連接記憶體陣列。在程式化期間,電路導通第一電晶體並關閉第二電晶體。此外,電路利用傳遞電壓開啟所述多個非目標記憶胞,並利用輔助電壓開啟第一周邊記憶胞與第二周邊記憶胞。再者,電路利用程式化電壓對目標記憶胞進行程式化。其中,輔助電壓大於傳遞電壓,且輔助電壓小於程式化電壓。 The invention also proposes a memory device comprising a memory array and circuitry. The memory array includes a first transistor, a memory cell string and a second transistor connected in series, and the memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a target A plurality of non-target memory cells whose memory cells are not adjacent. The circuit is electrically connected to the memory array. During stylization, the circuit turns on the first transistor and turns off the second transistor. In addition, the circuit turns on the plurality of non-target memory cells by using a transfer voltage, and turns on the first peripheral memory cell and the second peripheral memory cell by using the auxiliary voltage. Furthermore, the circuit uses a stylized voltage to program the target memory cell. Wherein, the auxiliary voltage is greater than the transfer voltage, and the auxiliary voltage is less than the stylized voltage.
基於上述,本發明是利用輔助電壓來開啟與目標記憶胞相鄰的第一周邊記憶胞與第二周邊記憶胞。此外,輔助電壓大於傳遞電壓,且輔助電壓小於程式化電壓。藉此,輔助電壓將可用以提升目標記憶胞之浮置閘的電壓的上升速度,進而有助於提升 記憶體裝置的程式化速度。 Based on the above, the present invention utilizes an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell adjacent to the target memory cell. In addition, the auxiliary voltage is greater than the transfer voltage and the auxiliary voltage is less than the stylized voltage. Thereby, the auxiliary voltage will be used to increase the rising speed of the voltage of the floating gate of the target memory cell, thereby contributing to the improvement. The stylized speed of the memory device.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100‧‧‧記憶體裝置 100‧‧‧ memory device
110‧‧‧記憶體陣列 110‧‧‧Memory array
120‧‧‧電路 120‧‧‧ Circuitry
121‧‧‧列解碼器 121‧‧‧ column decoder
122‧‧‧行解碼器 122‧‧‧ line decoder
SW1‧‧‧第一電晶體 SW1‧‧‧First transistor
SW2‧‧‧第二電晶體 SW2‧‧‧second transistor
10‧‧‧記憶胞串 10‧‧‧ memory string
101~106‧‧‧記憶胞 101~106‧‧‧ memory cells
BL1‧‧‧位元線 BL1‧‧‧ bit line
CSL‧‧‧共源極線 CSL‧‧‧Common source line
SSL‧‧‧串選擇線 SSL‧‧‧string selection line
GSL‧‧‧接地選擇線 GSL‧‧‧ Grounding selection line
WL1~WL6‧‧‧字元線 WL1~WL6‧‧‧ character line
GND‧‧‧接地電壓 GND‧‧‧ Grounding voltage
Vsl、Vgl‧‧‧選擇電壓 Vsl, Vgl‧‧‧Select voltage
Vps‧‧‧傳遞電壓 Vps‧‧‧Transfer voltage
Vas‧‧‧輔助電壓 Vas‧‧‧Auxiliary voltage
Vpm‧‧‧程式化電壓 Vpm‧‧‧Standard voltage
S210~S230‧‧‧圖2實施例中的各步驟 S210~S230‧‧‧ steps in the embodiment of Fig. 2
310‧‧‧通道 310‧‧‧ channel
S410~S450‧‧‧圖4實施例中的各步驟 S410~S450‧‧‧Steps in the embodiment of Figure 4
L51、L71、L101、L121‧‧‧第一位準 L51, L71, L101, L121‧‧‧ first standard
L52、L72、L102、L122‧‧‧第二位準 L52, L72, L102, L122‧‧‧ second level
L53、L73、L103、L123‧‧‧第三位準 L53, L73, L103, L123‧‧‧ third standard
T5、T7、T10、T12‧‧‧程式化期間 T5, T7, T10, T12‧‧‧ stylized period
S610~S650‧‧‧圖6實施例中的各步驟 S610~S650‧‧‧ steps in the embodiment of Fig. 6
810、820、1310、1320‧‧‧曲線 810, 820, 1310, 1320‧‧‧ curves
S910~S950‧‧‧圖9實施例中的各步驟 S910~S950‧‧‧ steps in the embodiment of Fig. 9
S1110~S1150‧‧‧圖11實施例中的各步驟 S1110~S1150‧‧‧ steps in the embodiment of Fig. 11
圖1為依據本發明一實施例之記憶體裝置的示意圖。 1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.
圖2為依據本發明一實施例之記憶體裝置的程式化方法流程圖。 2 is a flow chart of a stylized method of a memory device in accordance with an embodiment of the present invention.
圖3為依據本發明一實施例之記憶體陣列的佈局剖面示意圖。 3 is a cross-sectional view showing the layout of a memory array in accordance with an embodiment of the present invention.
圖4為依據本發明一實施例之用以說明步驟S220與S230之細部步驟的流程圖。 4 is a flow chart for explaining the detailed steps of steps S220 and S230 in accordance with an embodiment of the present invention.
圖5為用以說明圖4實施例的波形圖。 Figure 5 is a waveform diagram for explaining the embodiment of Figure 4.
圖6為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖。 FIG. 6 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention.
圖7為用以說明圖6實施例的波形圖。 Figure 7 is a waveform diagram for explaining the embodiment of Figure 6.
圖8為依據本發明一實施例之程式化電壓與目標記憶胞之臨界電壓的變動量的曲線圖。 FIG. 8 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell in accordance with an embodiment of the present invention.
圖9為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖。 FIG. 9 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention.
圖10為用以說明圖9實施例的波形圖。 Figure 10 is a waveform diagram for explaining the embodiment of Figure 9.
圖11為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖。 Figure 11 is a flow chart showing the detailed steps of steps S220 and S230 in accordance with another embodiment of the present invention.
圖12為用以說明圖11實施例的波形圖。 Figure 12 is a waveform diagram for explaining the embodiment of Figure 11.
圖13為依據本發明另一實施例之程式化電壓與目標記憶胞之臨界電壓的變動量的曲線圖。 FIG. 13 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell according to another embodiment of the present invention.
在說明記憶體裝置的程式化方法之前,以下將先列舉記憶體裝置的結構。 Before explaining the stylization method of the memory device, the structure of the memory device will be listed below.
圖1為依據本發明一實施例之記憶體裝置的示意圖。參照圖1,記憶體裝置100包括記憶體陣列110與電路120。此外,電路120包括列解碼器121與行解碼器122,且記憶體陣列110包括多個相互串接的第一電晶體、記憶胞串與第二電晶體。舉例來說,記憶體陣列110包括第一電晶體SW1、記憶胞串10與第二電晶體SW2。其中,第一電晶體SW1、記憶胞串10與第二電晶體SW2串接在位元線BL1與共源極線CSL之間。記憶胞串10包括相互串接的多個記憶胞101~106。 1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory device 100 includes a memory array 110 and a circuit 120. In addition, the circuit 120 includes a column decoder 121 and a row decoder 122, and the memory array 110 includes a plurality of first transistors, a memory cell string and a second transistor that are connected in series. For example, the memory array 110 includes a first transistor SW1, a memory cell string 10, and a second transistor SW2. The first transistor SW1, the memory cell string 10 and the second transistor SW2 are connected in series between the bit line BL1 and the common source line CSL. The memory cell string 10 includes a plurality of memory cells 101 to 106 connected in series.
列解碼器121透過串選擇線SSL電性連接記憶體陣列110中的每一第一電晶體,例如:第一電晶體SW1。此外,列解碼器121透過接地選擇線GSL電性連接記憶體陣列110中的每一第二電晶體,例如:第二電晶體SW2。再者,列解碼器121透過字元線WL1~WL6電性連接記憶體陣列110中的記憶胞,例如:記憶 胞101~106。行解碼器122則是透過多個位元線,例如:位元線BL1,電性連接至記憶體陣列110。 The column decoder 121 is electrically connected to each of the first transistors in the memory array 110 through the string selection line SSL, for example, the first transistor SW1. In addition, the column decoder 121 is electrically connected to each of the second transistors in the memory array 110 through the ground selection line GSL, for example, the second transistor SW2. Furthermore, the column decoder 121 is electrically connected to the memory cells in the memory array 110 through the word lines WL1 WL WL6, for example, memory. Cells 101~106. The row decoder 122 is electrically connected to the memory array 110 through a plurality of bit lines, for example, the bit line BL1.
在操作上,電路120中的列解碼器121與行解碼器122會依據位址資料提供對應的電壓至記憶體陣列110,以程式化記憶體陣列110中的至少一記憶胞。舉例來說,記憶體裝置100可針對記憶胞串10中的記憶胞103進行程式化。此外,在對記憶胞103進行程式化操作的過程中,記憶胞103將相當於目標記憶胞,且與記憶胞103相鄰的兩記憶胞102與104將相當於第一周邊記憶胞與第二周邊記憶胞,且與記憶胞103不相鄰的記憶胞101、105、106將相當於非目標記憶胞。 In operation, the column decoder 121 and the row decoder 122 in the circuit 120 provide corresponding voltages to the memory array 110 according to the address data to program at least one memory cell in the memory array 110. For example, the memory device 100 can be programmed for the memory cells 103 in the memory cell string 10. In addition, in the process of programming the memory cell 103, the memory cell 103 will be equivalent to the target memory cell, and the two memory cells 102 and 104 adjacent to the memory cell 103 will be equivalent to the first peripheral memory cell and the second. The memory cells 101, 105, 106 that are peripheral memory cells and are not adjacent to the memory cell 103 will correspond to non-target memory cells.
為了致使本領域具有通常知識者能更加瞭解本實施利,圖2為依據本發明一實施例之記憶體裝置的程式化方法流程圖,且以下將參照圖1與圖2來進一步地說明目標記憶胞103的程式化操作。 FIG. 2 is a flowchart of a stylized method of a memory device according to an embodiment of the present invention, and the target memory will be further described below with reference to FIG. 1 and FIG. 2 in order to make the present invention more familiar to those skilled in the art. FIG. Stylized operation of cell 103.
如步驟S210所示,在程式化期間,電路120會導通(turn on)第一電晶體SW1並關閉(turn off)第二電晶體SW2。例如,行解碼器122會提供接地電壓GND至電性連接記憶胞串10的位元線BL1,且共源極線CSL會維持在接地電壓GND。再者,列解碼器121會提供選擇電壓Vsl至電性連接第一電晶體SW1的串選擇線SSL,並提供選擇電壓Vgl至電性連接第二電晶體SW2的接地選擇線GSL。此外,如步驟S220所示,在程式化期間,電路120會利用傳遞電壓Vps開啟非目標記憶胞101、105、106,並利用輔 助電壓Vas開啟第一周邊記憶胞102與第二周邊記憶胞104。再者,如步驟S230所示,在程式化期間,電路120會利用程式化電壓Vpm對目標記憶胞103進行程式化。 As shown in step S210, during stylization, the circuit 120 turns on the first transistor SW1 and turns off the second transistor SW2. For example, the row decoder 122 supplies the ground voltage GND to the bit line BL1 electrically connected to the memory cell string 10, and the common source line CSL is maintained at the ground voltage GND. Furthermore, the column decoder 121 provides the selection voltage Vs1 to the string selection line SSL electrically connected to the first transistor SW1, and provides the selection voltage Vgl to the ground selection line GSL electrically connected to the second transistor SW2. In addition, as shown in step S220, during the stylization, the circuit 120 turns on the non-target memory cells 101, 105, 106 by using the transfer voltage Vps, and utilizes the auxiliary The boost voltage Vas turns on the first peripheral memory cell 102 and the second peripheral memory cell 104. Furthermore, as shown in step S230, during the stylization, the circuit 120 programs the target memory cell 103 with the stylized voltage Vpm.
舉例來說,圖3為依據本發明一實施例之記憶體陣列的佈局剖面示意圖。如圖3所示,隨著第一電晶體SW1的導通以及第二電晶體SW2的關閉,記憶胞串10的一端會維持在接地電壓GND,且記憶胞串10的另一端將浮接(floating)。此外,記憶胞串10會反應於電路120所提供的電壓而形成一通道310。 For example, FIG. 3 is a schematic cross-sectional view showing a layout of a memory array according to an embodiment of the invention. As shown in FIG. 3, with the conduction of the first transistor SW1 and the closing of the second transistor SW2, one end of the memory cell string 10 is maintained at the ground voltage GND, and the other end of the memory cell string 10 is floated (floating ). In addition, the memory cell string 10 will react to the voltage provided by the circuit 120 to form a channel 310.
再者,施加在目標記憶胞103的程式化電壓Vpm可耦合至目標記憶胞103的浮置閘。因此,程式化電壓Vpm耦合至目標記憶胞103之浮置閘的電壓量將可產生一大電場橫跨目標記憶胞103的氧化層,進而引發通道310中的電子以Fowler-Nordheim(簡稱FN)穿隧的方式注入到目標記憶胞103的浮置閘。 Furthermore, the stylized voltage Vpm applied to the target memory cell 103 can be coupled to the floating gate of the target memory cell 103. Thus, the amount of voltage that the programmed voltage Vpm is coupled to the floating gate of the target memory cell 103 will produce a large electric field across the oxide layer of the target memory cell 103, thereby inducing electrons in the channel 310 to Fowler-Nordheim (FN). The floating gate of the target memory cell 103 is injected in a tunneling manner.
值得注意的是,施加在兩周邊記憶胞102與104的輔助電壓Vas也可耦合至目標記憶胞103的浮置閘。此外,輔助電壓Vas耦合至目標記憶胞103之浮置閘的電壓量將可以提高位在目標記憶胞103之浮置閘的電壓,進而協助通道310中的電子可以更快速的注入到目標記憶胞103的浮置閘,進而有助於提升目標記憶胞103的程式化速度。據此,將可以避免因應閘極耦合率較低而導致記憶胞之程式化速度大幅地下降的問題。換言之,圖2所示的程式化方法除了適用於具有非平面式結構的記憶體陣列110以外,也適用於具有平面式結構的記憶體陣列110。亦即,在一實 施例中,記憶體陣列110可採用平面式結構,進而有助於縮減記憶體裝置100的尺寸。 It is to be noted that the auxiliary voltage Vas applied to the two peripheral memory cells 102 and 104 can also be coupled to the floating gate of the target memory cell 103. In addition, the amount of voltage of the auxiliary voltage Vas coupled to the floating gate of the target memory cell 103 can increase the voltage of the floating gate of the target memory cell 103, thereby facilitating the faster injection of electrons in the channel 310 to the target memory cell. The floating gate of 103, in turn, helps to increase the stylized speed of the target memory cell 103. Accordingly, it is possible to avoid the problem that the stylized speed of the memory cells is greatly lowered in response to the low gate coupling ratio. In other words, the stylized method shown in FIG. 2 is applicable to the memory array 110 having a planar structure, in addition to the memory array 110 having a non-planar structure. That is, in a real In the embodiment, the memory array 110 can adopt a planar structure, thereby helping to reduce the size of the memory device 100.
舉例來說,第一周邊記憶胞102的控制閘與目標記憶胞103的浮置閘之間可產生一寄生電容,進而致使施加在第一周邊記憶胞102的輔助電壓Vas可以耦合至目標記憶胞103的浮置閘。相似地,第二周邊記憶胞104的控制閘與目標記憶胞103的浮置閘之間也會產生另一寄生電容,進而致使施加在第二周邊記憶胞104的輔助電壓Vas也可耦合至目標記憶胞103的浮置閘。 For example, a parasitic capacitance can be generated between the control gate of the first peripheral memory cell 102 and the floating gate of the target memory cell 103, thereby causing the auxiliary voltage Vas applied to the first peripheral memory cell 102 to be coupled to the target memory cell. 103 floating gate. Similarly, another parasitic capacitance is generated between the control gate of the second peripheral memory cell 104 and the floating gate of the target memory cell 103, thereby causing the auxiliary voltage Vas applied to the second peripheral memory cell 104 to be coupled to the target. The floating gate of the memory cell 103.
此外,由於輔助電壓Vas大於傳遞電壓Vps,因此輔助電壓Vas除了可以開啟兩周邊記憶胞102與104以外,輔助電壓Vas耦合至目標記憶胞103之浮置閘的電壓量還可以加速通道310中的電子注入到目標記憶胞103的浮置閘。藉此,將可提升目標記憶胞103之浮置閘的電壓的上升速度,進而有助於提升記憶體裝置100的程式化速度。此外,電路120所提供的輔助電壓Vas需小於程式化電壓Vpm的最低位準(亦即,最低可程式化電壓),以藉此避免輔助電壓Vas造成兩周邊記憶胞102與104各自本身被程式化。 In addition, since the auxiliary voltage Vas is greater than the transfer voltage Vps, the auxiliary voltage Vas can open the two peripheral memory cells 102 and 104, and the voltage of the auxiliary voltage Vas coupled to the floating gate of the target memory cell 103 can also accelerate the channel 310. The electrons are injected into the floating gate of the target memory cell 103. Thereby, the rising speed of the voltage of the floating gate of the target memory cell 103 can be increased, thereby contributing to the increase in the stylized speed of the memory device 100. In addition, the auxiliary voltage Vas provided by the circuit 120 needs to be lower than the lowest level of the stylized voltage Vpm (ie, the lowest programmable voltage), thereby preventing the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be programmed by themselves. Chemical.
圖4為依據本發明一實施例之用以說明步驟S220與S230之細部步驟的流程圖,且圖5為用以說明圖4實施例的波形圖。以下請同時參照圖1、圖4與圖5來看記憶體裝置100之程式化操作的細部流程。 4 is a flow chart for explaining the detailed steps of steps S220 and S230 according to an embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the embodiment of FIG. 4. Hereinafter, the detailed flow of the stylized operation of the memory device 100 will be described with reference to FIGS. 1, 4, and 5.
在開啟記憶胞的操作上,列解碼器121會產生選擇電壓 Vgl、選擇電壓Vsl、傳遞電壓Vps、輔助電壓Vas與程式化電壓Vpm,且選擇電壓Vgl相等於接地電壓GND。此外,如步驟S410所示,在程式化期間T5內,列解碼器121提供傳遞電壓Vps至電性連接非目標記憶胞101、105、106的字元線(亦即,第一字元線)WL1、WL5、WL6。此外,列解碼器121會提供輔助電壓Vas至電性連接第一周邊記憶胞102的字元線(亦即,第二字元線)WL2以及電性連接第二周邊記憶胞104的字元線(亦即,第三字元線)WL4。此外,如步驟S420與S430所示,在程式化期間T5內,列解碼器121會將傳遞電壓Vps維持在第一位準L51,並將輔助電壓Vas維持在第二位準L52。 The column decoder 121 generates a selection voltage in the operation of turning on the memory cell. Vgl, the selection voltage Vsl, the transfer voltage Vps, the auxiliary voltage Vas, and the stylized voltage Vpm, and the selection voltage Vgl is equal to the ground voltage GND. In addition, as shown in step S410, during the stylization period T5, the column decoder 121 provides the transfer voltage Vps to the word line electrically connected to the non-target memory cells 101, 105, 106 (ie, the first word line). WL1, WL5, WL6. In addition, the column decoder 121 provides the auxiliary voltage Vas to the word line (ie, the second word line) WL2 electrically connected to the first peripheral memory cell 102 and the word line electrically connected to the second peripheral memory cell 104. (ie, the third word line) WL4. Further, as shown in steps S420 and S430, during the staging period T5, the column decoder 121 maintains the transfer voltage Vps at the first level L51 and maintains the auxiliary voltage Vas at the second level L52.
另一方面,就目標記憶胞103而言,如步驟S440與S450所示,列解碼器121會提供程式化電壓Vpm至電性連接目標記憶胞103的字元線(亦即,第四字元線)WL3,並將程式化電壓Vpm維持在第三位準L53。藉此,記憶體裝置100將可進行目標記憶胞103的程式化操作。值得注意的是,第二位準L52大於第一位準L51,以致使輔助電壓Vas除了可以開啟兩周邊記憶胞102與104以外,還有助於提升目標記憶胞103之浮置閘的電壓的上升速度。此外,第二位準L52小於第三位準L53(亦即,最低可程式化電壓),以避免輔助電壓Vas造成兩周邊記憶胞102與104各自本身被程式化(即為,程式化干擾)。 On the other hand, in the case of the target memory cell 103, as shown in steps S440 and S450, the column decoder 121 supplies the stylized voltage Vpm to the word line electrically connected to the target memory cell 103 (ie, the fourth character). Line) WL3 and maintain the programmed voltage Vpm at the third level L53. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the second level L52 is greater than the first level L51, so that the auxiliary voltage Vas can increase the voltage of the floating gate of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104. The rate of rise. In addition, the second level L52 is smaller than the third level L53 (ie, the lowest programmable voltage) to prevent the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, stylized interference). .
雖然圖4與圖5實施例是將輔助電壓Vas與程式化電壓Vp分別維持在一固定位準,但其並非用以限定本發明。例如,在 另一實施例中,輔助電壓Vas與程式化電壓Vp之其一也可以步階方式逐漸上升,以進一步地提升記憶體裝置100的程式化速度。 Although the embodiment of FIGS. 4 and 5 maintains the auxiliary voltage Vas and the stylized voltage Vp at a fixed level, respectively, it is not intended to limit the present invention. For example, in In another embodiment, one of the auxiliary voltage Vas and the stylized voltage Vp may be gradually increased in a stepwise manner to further increase the stylized speed of the memory device 100.
舉例來說,圖6為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖,且圖7為用以說明圖6實施例的波形圖。其中,圖6實施例是將輔助電壓Vas維持在一固定位準,並以步階方式來調整程式化電壓Vpm。 For example, FIG. 6 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 7 is a waveform diagram for explaining the embodiment of FIG. 6. In the embodiment of FIG. 6, the auxiliary voltage Vas is maintained at a fixed level, and the stylized voltage Vpm is adjusted in a stepwise manner.
具體而言,圖6中的步驟S610~S630與圖4中的步驟S410~S430相似。例如,在程式化期間T7內,列解碼器121會提供傳遞電壓Vps至字元線WL1、WL5、WL6,並提供輔助電壓Vas至字元線WL2與WL4。此外,列解碼器121會將傳遞電壓Vps維持在第一位準L71,並將輔助電壓Vas維持在第二位準L72。藉此,將可開啟非目標記憶胞101、105、106以及兩周邊記憶胞102與104。 Specifically, steps S610 to S630 in FIG. 6 are similar to steps S410 to S430 in FIG. 4. For example, during the staging period T7, the column decoder 121 provides the transfer voltage Vps to the word lines WL1, WL5, WL6 and provides the auxiliary voltage Vas to the word lines WL2 and WL4. Further, the column decoder 121 maintains the transfer voltage Vps at the first level L71 and maintains the auxiliary voltage Vas at the second level L72. Thereby, the non-target memory cells 101, 105, 106 and the two peripheral memory cells 102 and 104 can be turned on.
另一方面,就步驟S640來看,在程式化期間T7內,列解碼器121會提供程式化電壓Vpm至字元線WL3。此外,就步驟S650來看,在程式化期間T7內,列解碼器121會調整程式化電壓Vpm,進而致使程式化電壓Vpm以步階方式從第三位準L73開始逐漸上升。藉此,記憶體裝置100將可進行目標記憶胞103的程式化操作。值得注意的是,第二位準L72小於第三位準L73(亦即,最低可程式化電壓),以避免輔助電壓Vas造成兩周邊記憶胞102與104各自本身被程式化(即為,程式化干擾)。此外,第二位準L72大於第一位準L71,以致使輔助電壓Vas可用以提升目標 記憶胞103之浮置閘的電壓的上升速度。 On the other hand, as seen in step S640, during the staging period T7, the column decoder 121 supplies the stylized voltage Vpm to the word line WL3. In addition, as seen in step S650, during the staging period T7, the column decoder 121 adjusts the stylized voltage Vpm, thereby causing the stylized voltage Vpm to gradually rise from the third level L73 in a stepwise manner. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It is worth noting that the second level L72 is smaller than the third level L73 (ie, the lowest programmable voltage) to avoid the auxiliary voltage Vas causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, the program Interference). In addition, the second level L72 is greater than the first level L71, so that the auxiliary voltage Vas can be used to raise the target. The rising speed of the voltage of the floating gate of the memory cell 103.
舉例來說,圖8為依據本發明一實施例之程式化電壓與目標記憶胞之臨界電壓的變動量的曲線圖。在圖8實施例中,記憶體陣列110為一平面式NAND型記憶體陣列,且曲線810用以表示平面式NAND型記憶體陣列在採用傳統遞增步階脈衝程式化(incremental step pulse programming,簡稱ISPP)方法下之臨界電壓的變動量,且曲線820用以表示平面式NAND型記憶體陣列在採用圖6之程式化方法下之臨界電壓的變動量。比對曲線810與曲線820來看,可以明顯地看出,平面式NAND型記憶體陣列在採用圖6之程式化方法的情況下,單位步階增量的程式化電壓所造成之臨界電壓的變動量將可以大幅地提升,進而有助於增加記憶體裝置100的程式化速度。 For example, FIG. 8 is a graph of the variation of the threshold voltage of the stylized voltage and the target memory cell in accordance with an embodiment of the present invention. In the embodiment of FIG. 8, the memory array 110 is a planar NAND type memory array, and the curve 810 is used to indicate that the planar NAND type memory array is in the form of incremental step pulse programming. The variation of the threshold voltage under the ISPP) method, and the curve 820 is used to indicate the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. Comparing the curve 810 with the curve 820, it can be clearly seen that the planar NAND type memory array has a threshold voltage caused by a stylized voltage of a step increment in the case of the stylized method of FIG. The amount of variation can be greatly increased, which in turn helps to increase the stylized speed of the memory device 100.
圖9為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖,且圖10為用以說明圖9實施例的波形圖。其中,圖9實施例是將程式化電壓Vpm維持在一固定位準,並以步階方式來調整輔助電壓Vas。 FIG. 9 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 10 is a waveform diagram for explaining the embodiment of FIG. 9. In the embodiment of FIG. 9, the stylized voltage Vpm is maintained at a fixed level, and the auxiliary voltage Vas is adjusted in a stepwise manner.
就步驟S910來看,在程式化期間T10內,列解碼器121會提供傳遞電壓Vps至字元線WL1、WL5、WL6,並提供輔助電壓Vas至字元線WL2與WL4。此外,就步驟S920來看,在程式化期間T10內,列解碼器121會將傳遞電壓Vps維持在第一位準L101。再者,就步驟S930來看,在程式化期間T10內,列解碼器121會調整輔助電壓Vas,以致使輔助電壓Vas以步階方式從第一 位準L101逐漸上升至第二位準L102。 As seen in step S910, during the staging period T10, the column decoder 121 supplies the transfer voltage Vps to the word lines WL1, WL5, WL6 and supplies the auxiliary voltage Vas to the word lines WL2 and WL4. Further, as seen in step S920, during the stylization period T10, the column decoder 121 maintains the transfer voltage Vps at the first level L101. Furthermore, as seen in step S930, during the stylization period T10, the column decoder 121 adjusts the auxiliary voltage Vas to cause the auxiliary voltage Vas to be stepped from the first The level L101 gradually rises to the second level L102.
另一方面,圖9中的步驟S940~S950與圖4中的步驟S440~S450相似。例如,在程式化期間T10內,列解碼器121會提供程式化電壓Vpm至字元線WL3,並將程式化電壓Vpm維持在第三位準L103。藉此,記憶體裝置100將可進行目標記憶胞103的程式化操作。值得注意的是,輔助電壓Vas除了可以開啟兩周邊記憶胞102與104以外,還有助於提升目標記憶胞103之浮置閘的電壓的上升速度。此外,第二位準L102小於第三位準L103(亦即,最低可程式化電壓),以避免輔助電壓Vas造成兩周邊記憶胞102與104各自本身被程式化(即為,程式化干擾)。 On the other hand, steps S940 to S950 in FIG. 9 are similar to steps S440 to S450 in FIG. For example, during the stylization period T10, the column decoder 121 provides the stylized voltage Vpm to the word line WL3 and maintains the programmed voltage Vpm at the third level L103. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the auxiliary voltage Vas can also increase the rising speed of the floating gate voltage of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104. In addition, the second level L102 is smaller than the third level L103 (ie, the lowest programmable voltage) to prevent the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, stylized interference). .
圖11為依據本發明另一實施例之用以說明步驟S220與S230之細部步驟的流程圖,且圖12為用以說明圖11實施例的波形圖。其中,圖11實施例是以步階方式來調整程式化電壓Vpm與輔助電壓Vas。 FIG. 11 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 12 is a waveform diagram for explaining the embodiment of FIG. The embodiment of FIG. 11 adjusts the stylized voltage Vpm and the auxiliary voltage Vas in a stepwise manner.
具體而言,圖11中的步驟S1110~S1130與圖9中的步驟S910~S930相似。例如,在程式化期間T12內,列解碼器121會提供傳遞電壓Vps至字元線WL1、WL5、WL6,並提供輔助電壓Vas至字元線WL2與WL4。此外,列解碼器121會將傳遞電壓Vps維持在第一位準L121,且列解碼器121會調整輔助電壓Vas,以致使輔助電壓Vas以步階方式從第一位準L121上升至第二位準L122。 Specifically, steps S1110 to S1130 in FIG. 11 are similar to steps S910 to S930 in FIG. 9. For example, during the staging period T12, the column decoder 121 provides the transfer voltage Vps to the word lines WL1, WL5, WL6 and provides the auxiliary voltage Vas to the word lines WL2 and WL4. In addition, the column decoder 121 maintains the transfer voltage Vps at the first level L121, and the column decoder 121 adjusts the auxiliary voltage Vas to cause the auxiliary voltage Vas to rise from the first level L121 to the second position in a stepwise manner. Quasi L122.
再者,圖11中的步驟S1140~S1150與圖6中的步驟 S640~S650相似。例如,在程式化期間T12內,列解碼器121會提供程式化電壓Vpm至字元線WL3。此外,列解碼器121會調整程式化電壓Vpm,以致使程式化電壓Vpm以步階方式從第三位準L123開始逐漸上升。藉此,記憶體裝置100將可進行目標記憶胞103的程式化操作。值得注意的是,第二位準L122小於第三位準L123(亦即,最低可程式化電壓),以避免輔助電壓Vas造成兩周邊記憶胞102與104各自本身被程式化(即為,程式化干擾)。此外,輔助電壓Vas除了可以開啟兩周邊記憶胞102與104以外,還有助於提升目標記憶胞103之浮置閘的電壓的上升速度。 Furthermore, steps S1140 to S1150 in FIG. 11 and steps in FIG. S640~S650 are similar. For example, during the stylization period T12, the column decoder 121 provides the stylized voltage Vpm to the word line WL3. In addition, the column decoder 121 adjusts the stylized voltage Vpm such that the stylized voltage Vpm gradually rises from the third level L123 in a stepwise manner. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the second level L122 is smaller than the third level L123 (ie, the lowest programmable voltage) to avoid the auxiliary voltage Vas causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, the program Interference). In addition, the auxiliary voltage Vas can also increase the rising speed of the voltage of the floating gate of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104.
值得一提的是,與圖6實施例中的具有固定位準的輔助電壓Vas相較之下,採用步階方式增加的輔助電壓Vas可更進一步地提升記憶體裝置100的程式化速度。舉例來說,圖13為依據本發明另一實施例之程式化電壓與目標記憶胞之臨界電壓的變動量的曲線圖。在圖13實施例中,記憶體陣列110為一平面式NAND型記憶體陣列,且曲線1310用以表示平面式NAND型記憶體陣列在採用圖6之程式化方法下之臨界電壓的變動量,且曲線1320用以表示平面式NAND型記憶體陣列在採用圖9之程式化方法下之臨界電壓的變動量。比對曲線1310與曲線1320來看,可以明顯地看出,採用步階方式增加的輔助電壓Vas可更進一步地提升記憶體裝置100的程式化速度。 It is worth mentioning that, compared with the auxiliary voltage Vas having a fixed level in the embodiment of FIG. 6, the auxiliary voltage Vas increased in a stepwise manner can further increase the stylized speed of the memory device 100. For example, FIG. 13 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell according to another embodiment of the present invention. In the embodiment of FIG. 13, the memory array 110 is a planar NAND type memory array, and the curve 1310 is used to represent the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. The curve 1320 is used to indicate the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. As seen from the comparison curve 1310 and the curve 1320, it can be clearly seen that the auxiliary voltage Vas increased in a stepwise manner can further increase the stylized speed of the memory device 100.
綜上所述,本發明是利用輔助電壓來開啟與目標記憶胞相鄰的兩周邊記憶胞。此外,輔助電壓大於傳遞電壓,且輔助電 壓小於程式化電壓。藉此,輔助電壓除了可以開啟兩周邊記憶胞以外,輔助電壓還可用以提升目標記憶胞之浮置閘的電壓的上升速度,進而有助於提升目標記憶胞的程式化速度。 In summary, the present invention utilizes an auxiliary voltage to turn on two peripheral memory cells adjacent to the target memory cell. In addition, the auxiliary voltage is greater than the transfer voltage, and the auxiliary power The voltage is less than the stylized voltage. In addition to the auxiliary voltage, in addition to opening the two peripheral memory cells, the auxiliary voltage can also be used to increase the rising speed of the floating gate voltage of the target memory cell, thereby helping to increase the stylized speed of the target memory cell.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
S210~S230‧‧‧圖2實施例中的各步驟 S210~S230‧‧‧ steps in the embodiment of Fig. 2
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