TWI547948B - Memory device and programming method thereof - Google Patents

Description

Memory device and its stylized method

The present invention relates to a memory device and a stylized method thereof, and more particularly to a planar memory device and a stylized method thereof.

There are many types of non-volatile memory, and currently flash memory is the mainstream product. Most existing flash memories use a non-planar structure to increase the gate-coupling ratio (GCR). In addition, as the size of the memory cell is gradually reduced, the flash memory may need to be implemented using a planar structure. However, planar flash memory has a lower gate coupling ratio. Therefore, the existing stylized method used in flat flash memory tends to cause the stylized speed of the planar flash memory to drop drastically.

The present invention provides a memory device and a stylized method for increasing the stylized speed of a memory device.

The present invention proposes a stylized method of a memory device. The memory device includes a first transistor, a memory cell string and a second transistor connected in series, and the memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a target The plurality of non-target memory cells that are not adjacent to the memory cell, and the stylized method of the memory device includes the following steps. The first transistor is turned on and the second transistor is turned off. The plurality of non-target memory cells are turned on by the transfer voltage, and the first peripheral memory cells and the second peripheral memory cells are turned on by the auxiliary voltage. And, stylize the target memory cell with a stylized voltage. Wherein, the auxiliary voltage is greater than the transfer voltage, and the auxiliary voltage is less than the stylized voltage.

The invention also proposes a memory device comprising a memory array and circuitry. The memory array includes a first transistor, a memory cell string and a second transistor connected in series, and the memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a target A plurality of non-target memory cells whose memory cells are not adjacent. The circuit is electrically connected to the memory array. During stylization, the circuit turns on the first transistor and turns off the second transistor. In addition, the circuit turns on the plurality of non-target memory cells by using a transfer voltage, and turns on the first peripheral memory cell and the second peripheral memory cell by using the auxiliary voltage. Furthermore, the circuit uses a stylized voltage to program the target memory cell. Wherein, the auxiliary voltage is greater than the transfer voltage, and the auxiliary voltage is less than the stylized voltage.

Based on the above, the present invention utilizes an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell adjacent to the target memory cell. In addition, the auxiliary voltage is greater than the transfer voltage and the auxiliary voltage is less than the stylized voltage. Thereby, the auxiliary voltage will be used to increase the rising speed of the voltage of the floating gate of the target memory cell, thereby contributing to the improvement. The stylized speed of the memory device.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧ memory device

110‧‧‧Memory array

120‧‧‧ Circuitry

121‧‧‧ column decoder

122‧‧‧ line decoder

SW1‧‧‧First transistor

SW2‧‧‧second transistor

10‧‧‧ memory string

101~106‧‧‧ memory cells

BL1‧‧‧ bit line

CSL‧‧‧Common source line

SSL‧‧‧string selection line

GSL‧‧‧ Grounding selection line

WL1~WL6‧‧‧ character line

GND‧‧‧ Grounding voltage

Vsl, Vgl‧‧‧Select voltage

Vps‧‧‧Transfer voltage

Vas‧‧‧Auxiliary voltage

Vpm‧‧‧Standard voltage

S210~S230‧‧‧ steps in the embodiment of Fig. 2

310‧‧‧ channel

S410~S450‧‧‧Steps in the embodiment of Figure 4

L51, L71, L101, L121‧‧‧ first standard

L52, L72, L102, L122‧‧‧ second level

L53, L73, L103, L123‧‧‧ third standard

T5, T7, T10, T12‧‧‧ stylized period

S610~S650‧‧‧ steps in the embodiment of Fig. 6

810, 820, 1310, 1320‧‧‧ curves

S910~S950‧‧‧ steps in the embodiment of Fig. 9

S1110~S1150‧‧‧ steps in the embodiment of Fig. 11

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

2 is a flow chart of a stylized method of a memory device in accordance with an embodiment of the present invention.

3 is a cross-sectional view showing the layout of a memory array in accordance with an embodiment of the present invention.

4 is a flow chart for explaining the detailed steps of steps S220 and S230 in accordance with an embodiment of the present invention.

Figure 5 is a waveform diagram for explaining the embodiment of Figure 4.

FIG. 6 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention.

Figure 7 is a waveform diagram for explaining the embodiment of Figure 6.

FIG. 8 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell in accordance with an embodiment of the present invention.

FIG. 9 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention.

Figure 10 is a waveform diagram for explaining the embodiment of Figure 9.

Figure 11 is a flow chart showing the detailed steps of steps S220 and S230 in accordance with another embodiment of the present invention.

Figure 12 is a waveform diagram for explaining the embodiment of Figure 11.

FIG. 13 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell according to another embodiment of the present invention.

Before explaining the stylization method of the memory device, the structure of the memory device will be listed below.

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. Referring to FIG. 1, the memory device 100 includes a memory array 110 and a circuit 120. In addition, the circuit 120 includes a column decoder 121 and a row decoder 122, and the memory array 110 includes a plurality of first transistors, a memory cell string and a second transistor that are connected in series. For example, the memory array 110 includes a first transistor SW1, a memory cell string 10, and a second transistor SW2. The first transistor SW1, the memory cell string 10 and the second transistor SW2 are connected in series between the bit line BL1 and the common source line CSL. The memory cell string 10 includes a plurality of memory cells 101 to 106 connected in series.

The column decoder 121 is electrically connected to each of the first transistors in the memory array 110 through the string selection line SSL, for example, the first transistor SW1. In addition, the column decoder 121 is electrically connected to each of the second transistors in the memory array 110 through the ground selection line GSL, for example, the second transistor SW2. Furthermore, the column decoder 121 is electrically connected to the memory cells in the memory array 110 through the word lines WL1 WL WL6, for example, memory. Cells 101~106. The row decoder 122 is electrically connected to the memory array 110 through a plurality of bit lines, for example, the bit line BL1.

In operation, the column decoder 121 and the row decoder 122 in the circuit 120 provide corresponding voltages to the memory array 110 according to the address data to program at least one memory cell in the memory array 110. For example, the memory device 100 can be programmed for the memory cells 103 in the memory cell string 10. In addition, in the process of programming the memory cell 103, the memory cell 103 will be equivalent to the target memory cell, and the two memory cells 102 and 104 adjacent to the memory cell 103 will be equivalent to the first peripheral memory cell and the second. The memory cells 101, 105, 106 that are peripheral memory cells and are not adjacent to the memory cell 103 will correspond to non-target memory cells.

FIG. 2 is a flowchart of a stylized method of a memory device according to an embodiment of the present invention, and the target memory will be further described below with reference to FIG. 1 and FIG. 2 in order to make the present invention more familiar to those skilled in the art. FIG. Stylized operation of cell 103.

As shown in step S210, during stylization, the circuit 120 turns on the first transistor SW1 and turns off the second transistor SW2. For example, the row decoder 122 supplies the ground voltage GND to the bit line BL1 electrically connected to the memory cell string 10, and the common source line CSL is maintained at the ground voltage GND. Furthermore, the column decoder 121 provides the selection voltage Vs1 to the string selection line SSL electrically connected to the first transistor SW1, and provides the selection voltage Vgl to the ground selection line GSL electrically connected to the second transistor SW2. In addition, as shown in step S220, during the stylization, the circuit 120 turns on the non-target memory cells 101, 105, 106 by using the transfer voltage Vps, and utilizes the auxiliary The boost voltage Vas turns on the first peripheral memory cell 102 and the second peripheral memory cell 104. Furthermore, as shown in step S230, during the stylization, the circuit 120 programs the target memory cell 103 with the stylized voltage Vpm.

For example, FIG. 3 is a schematic cross-sectional view showing a layout of a memory array according to an embodiment of the invention. As shown in FIG. 3, with the conduction of the first transistor SW1 and the closing of the second transistor SW2, one end of the memory cell string 10 is maintained at the ground voltage GND, and the other end of the memory cell string 10 is floated (floating ). In addition, the memory cell string 10 will react to the voltage provided by the circuit 120 to form a channel 310.

Furthermore, the stylized voltage Vpm applied to the target memory cell 103 can be coupled to the floating gate of the target memory cell 103. Thus, the amount of voltage that the programmed voltage Vpm is coupled to the floating gate of the target memory cell 103 will produce a large electric field across the oxide layer of the target memory cell 103, thereby inducing electrons in the channel 310 to Fowler-Nordheim (FN). The floating gate of the target memory cell 103 is injected in a tunneling manner.

It is to be noted that the auxiliary voltage Vas applied to the two peripheral memory cells 102 and 104 can also be coupled to the floating gate of the target memory cell 103. In addition, the amount of voltage of the auxiliary voltage Vas coupled to the floating gate of the target memory cell 103 can increase the voltage of the floating gate of the target memory cell 103, thereby facilitating the faster injection of electrons in the channel 310 to the target memory cell. The floating gate of 103, in turn, helps to increase the stylized speed of the target memory cell 103. Accordingly, it is possible to avoid the problem that the stylized speed of the memory cells is greatly lowered in response to the low gate coupling ratio. In other words, the stylized method shown in FIG. 2 is applicable to the memory array 110 having a planar structure, in addition to the memory array 110 having a non-planar structure. That is, in a real In the embodiment, the memory array 110 can adopt a planar structure, thereby helping to reduce the size of the memory device 100.

For example, a parasitic capacitance can be generated between the control gate of the first peripheral memory cell 102 and the floating gate of the target memory cell 103, thereby causing the auxiliary voltage Vas applied to the first peripheral memory cell 102 to be coupled to the target memory cell. 103 floating gate. Similarly, another parasitic capacitance is generated between the control gate of the second peripheral memory cell 104 and the floating gate of the target memory cell 103, thereby causing the auxiliary voltage Vas applied to the second peripheral memory cell 104 to be coupled to the target. The floating gate of the memory cell 103.

In addition, since the auxiliary voltage Vas is greater than the transfer voltage Vps, the auxiliary voltage Vas can open the two peripheral memory cells 102 and 104, and the voltage of the auxiliary voltage Vas coupled to the floating gate of the target memory cell 103 can also accelerate the channel 310. The electrons are injected into the floating gate of the target memory cell 103. Thereby, the rising speed of the voltage of the floating gate of the target memory cell 103 can be increased, thereby contributing to the increase in the stylized speed of the memory device 100. In addition, the auxiliary voltage Vas provided by the circuit 120 needs to be lower than the lowest level of the stylized voltage Vpm (ie, the lowest programmable voltage), thereby preventing the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be programmed by themselves. Chemical.

4 is a flow chart for explaining the detailed steps of steps S220 and S230 according to an embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the embodiment of FIG. 4. Hereinafter, the detailed flow of the stylized operation of the memory device 100 will be described with reference to FIGS. 1, 4, and 5.

The column decoder 121 generates a selection voltage in the operation of turning on the memory cell. Vgl, the selection voltage Vsl, the transfer voltage Vps, the auxiliary voltage Vas, and the stylized voltage Vpm, and the selection voltage Vgl is equal to the ground voltage GND. In addition, as shown in step S410, during the stylization period T5, the column decoder 121 provides the transfer voltage Vps to the word line electrically connected to the non-target memory cells 101, 105, 106 (ie, the first word line). WL1, WL5, WL6. In addition, the column decoder 121 provides the auxiliary voltage Vas to the word line (ie, the second word line) WL2 electrically connected to the first peripheral memory cell 102 and the word line electrically connected to the second peripheral memory cell 104. (ie, the third word line) WL4. Further, as shown in steps S420 and S430, during the staging period T5, the column decoder 121 maintains the transfer voltage Vps at the first level L51 and maintains the auxiliary voltage Vas at the second level L52.

On the other hand, in the case of the target memory cell 103, as shown in steps S440 and S450, the column decoder 121 supplies the stylized voltage Vpm to the word line electrically connected to the target memory cell 103 (ie, the fourth character). Line) WL3 and maintain the programmed voltage Vpm at the third level L53. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the second level L52 is greater than the first level L51, so that the auxiliary voltage Vas can increase the voltage of the floating gate of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104. The rate of rise. In addition, the second level L52 is smaller than the third level L53 (ie, the lowest programmable voltage) to prevent the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, stylized interference). .

Although the embodiment of FIGS. 4 and 5 maintains the auxiliary voltage Vas and the stylized voltage Vp at a fixed level, respectively, it is not intended to limit the present invention. For example, in In another embodiment, one of the auxiliary voltage Vas and the stylized voltage Vp may be gradually increased in a stepwise manner to further increase the stylized speed of the memory device 100.

For example, FIG. 6 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 7 is a waveform diagram for explaining the embodiment of FIG. 6. In the embodiment of FIG. 6, the auxiliary voltage Vas is maintained at a fixed level, and the stylized voltage Vpm is adjusted in a stepwise manner.

Specifically, steps S610 to S630 in FIG. 6 are similar to steps S410 to S430 in FIG. 4. For example, during the staging period T7, the column decoder 121 provides the transfer voltage Vps to the word lines WL1, WL5, WL6 and provides the auxiliary voltage Vas to the word lines WL2 and WL4. Further, the column decoder 121 maintains the transfer voltage Vps at the first level L71 and maintains the auxiliary voltage Vas at the second level L72. Thereby, the non-target memory cells 101, 105, 106 and the two peripheral memory cells 102 and 104 can be turned on.

On the other hand, as seen in step S640, during the staging period T7, the column decoder 121 supplies the stylized voltage Vpm to the word line WL3. In addition, as seen in step S650, during the staging period T7, the column decoder 121 adjusts the stylized voltage Vpm, thereby causing the stylized voltage Vpm to gradually rise from the third level L73 in a stepwise manner. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It is worth noting that the second level L72 is smaller than the third level L73 (ie, the lowest programmable voltage) to avoid the auxiliary voltage Vas causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, the program Interference). In addition, the second level L72 is greater than the first level L71, so that the auxiliary voltage Vas can be used to raise the target. The rising speed of the voltage of the floating gate of the memory cell 103.

For example, FIG. 8 is a graph of the variation of the threshold voltage of the stylized voltage and the target memory cell in accordance with an embodiment of the present invention. In the embodiment of FIG. 8, the memory array 110 is a planar NAND type memory array, and the curve 810 is used to indicate that the planar NAND type memory array is in the form of incremental step pulse programming. The variation of the threshold voltage under the ISPP) method, and the curve 820 is used to indicate the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. Comparing the curve 810 with the curve 820, it can be clearly seen that the planar NAND type memory array has a threshold voltage caused by a stylized voltage of a step increment in the case of the stylized method of FIG. The amount of variation can be greatly increased, which in turn helps to increase the stylized speed of the memory device 100.

FIG. 9 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 10 is a waveform diagram for explaining the embodiment of FIG. 9. In the embodiment of FIG. 9, the stylized voltage Vpm is maintained at a fixed level, and the auxiliary voltage Vas is adjusted in a stepwise manner.

As seen in step S910, during the staging period T10, the column decoder 121 supplies the transfer voltage Vps to the word lines WL1, WL5, WL6 and supplies the auxiliary voltage Vas to the word lines WL2 and WL4. Further, as seen in step S920, during the stylization period T10, the column decoder 121 maintains the transfer voltage Vps at the first level L101. Furthermore, as seen in step S930, during the stylization period T10, the column decoder 121 adjusts the auxiliary voltage Vas to cause the auxiliary voltage Vas to be stepped from the first The level L101 gradually rises to the second level L102.

On the other hand, steps S940 to S950 in FIG. 9 are similar to steps S440 to S450 in FIG. For example, during the stylization period T10, the column decoder 121 provides the stylized voltage Vpm to the word line WL3 and maintains the programmed voltage Vpm at the third level L103. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the auxiliary voltage Vas can also increase the rising speed of the floating gate voltage of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104. In addition, the second level L102 is smaller than the third level L103 (ie, the lowest programmable voltage) to prevent the auxiliary voltage Vas from causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, stylized interference). .

FIG. 11 is a flow chart for explaining the detailed steps of steps S220 and S230 according to another embodiment of the present invention, and FIG. 12 is a waveform diagram for explaining the embodiment of FIG. The embodiment of FIG. 11 adjusts the stylized voltage Vpm and the auxiliary voltage Vas in a stepwise manner.

Specifically, steps S1110 to S1130 in FIG. 11 are similar to steps S910 to S930 in FIG. 9. For example, during the staging period T12, the column decoder 121 provides the transfer voltage Vps to the word lines WL1, WL5, WL6 and provides the auxiliary voltage Vas to the word lines WL2 and WL4. In addition, the column decoder 121 maintains the transfer voltage Vps at the first level L121, and the column decoder 121 adjusts the auxiliary voltage Vas to cause the auxiliary voltage Vas to rise from the first level L121 to the second position in a stepwise manner. Quasi L122.

Furthermore, steps S1140 to S1150 in FIG. 11 and steps in FIG. S640~S650 are similar. For example, during the stylization period T12, the column decoder 121 provides the stylized voltage Vpm to the word line WL3. In addition, the column decoder 121 adjusts the stylized voltage Vpm such that the stylized voltage Vpm gradually rises from the third level L123 in a stepwise manner. Thereby, the memory device 100 can perform the stylized operation of the target memory cell 103. It should be noted that the second level L122 is smaller than the third level L123 (ie, the lowest programmable voltage) to avoid the auxiliary voltage Vas causing the two peripheral memory cells 102 and 104 to be themselves programmed (ie, the program Interference). In addition, the auxiliary voltage Vas can also increase the rising speed of the voltage of the floating gate of the target memory cell 103 in addition to the two peripheral memory cells 102 and 104.

It is worth mentioning that, compared with the auxiliary voltage Vas having a fixed level in the embodiment of FIG. 6, the auxiliary voltage Vas increased in a stepwise manner can further increase the stylized speed of the memory device 100. For example, FIG. 13 is a graph showing the amount of fluctuation of the threshold voltage of the stylized voltage and the target memory cell according to another embodiment of the present invention. In the embodiment of FIG. 13, the memory array 110 is a planar NAND type memory array, and the curve 1310 is used to represent the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. The curve 1320 is used to indicate the variation of the threshold voltage of the planar NAND type memory array under the stylized method of FIG. As seen from the comparison curve 1310 and the curve 1320, it can be clearly seen that the auxiliary voltage Vas increased in a stepwise manner can further increase the stylized speed of the memory device 100.

In summary, the present invention utilizes an auxiliary voltage to turn on two peripheral memory cells adjacent to the target memory cell. In addition, the auxiliary voltage is greater than the transfer voltage, and the auxiliary power The voltage is less than the stylized voltage. In addition to the auxiliary voltage, in addition to opening the two peripheral memory cells, the auxiliary voltage can also be used to increase the rising speed of the floating gate voltage of the target memory cell, thereby helping to increase the stylized speed of the target memory cell.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

S210~S230‧‧‧ steps in the embodiment of Fig. 2

Claims (4)

A method for staging a memory device, wherein the memory device comprises a first transistor, a memory string and a second transistor connected in series, the memory string comprising a target memory cell and the target memory a first and a second peripheral memory cell adjacent to the cell and a plurality of non-target memory cells not adjacent to the target memory cell, and the staging method of the memory device includes: turning on the first transistor and turning off The second transistor; using a transfer voltage to turn on the non-target memory cells, and using an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell, wherein the non-target memory cells are turned on by using the transfer voltage And the step of using the auxiliary voltage to turn on the first and second peripheral memory cells comprises: providing the transfer voltage to a plurality of first word lines electrically connected to the non-target memory cells, and providing the auxiliary voltage to Electrically connecting a second word line of the first peripheral memory cell and a third word line electrically connected to the second peripheral memory cell; and maintaining the transfer voltage at a first level, and The boost voltage is maintained at a second level, wherein the second level is greater than the first level; and the target memory cell is programmed with a programmed voltage that is greater than the transfer voltage and the auxiliary voltage Less than the stylized voltage, wherein the step of programming the target memory cell by using the stylized voltage comprises: providing the stylized voltage to a fourth character line electrically connected to the target memory cell; and adjusting the stylized Voltage so that the stylized voltage is in a stepwise manner Gradually rising from a third level, and the second level is less than the third level. A memory device includes: a memory array including a first transistor, a memory string and a second transistor connected in series, and the memory string includes a target memory cell and the target memory cell An adjacent first and a second peripheral memory cell, and a plurality of non-target memory cells not adjacent to the target memory cell; and a circuit electrically connected to the memory array, wherein during a stylization period, The circuit: turning on the first transistor and turning off the second transistor; using a transfer voltage to turn on the non-target memory cells, and using an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell; a stylized voltage is programmed to the target memory cell, wherein the auxiliary voltage is greater than the transfer voltage, and the auxiliary voltage is less than the programmed voltage; maintaining the transfer voltage at a first level and maintaining the auxiliary voltage At a second level, wherein the second level is greater than the first level; and adjusting the stylized voltage such that the stylized voltage gradually rises from a third level in a stepwise manner And the second level is less than the third level. A method for staging a memory device, wherein the memory device comprises a first transistor, a memory string and a second transistor connected in series, the memory string comprising a target memory cell and the target memory a first and a second peripheral memory cell adjacent to the cell and a plurality of non-target memory cells not adjacent to the target memory cell, and the stylized method of the memory device includes: Turning on the first transistor and turning off the second transistor; using a transfer voltage to turn on the non-target memory cells, and using an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell, wherein the transfer is utilized The step of turning on the non-target memory cells and using the auxiliary voltage to turn on the first and second peripheral memory cells comprises: providing the transfer voltage to a plurality of first characters electrically connected to the non-target memory cells And providing the auxiliary voltage to a second word line electrically connected to the first peripheral memory cell and a third word line electrically connected to the second peripheral memory cell; maintaining the transfer voltage at a And adjusting the auxiliary voltage such that the auxiliary voltage rises from the first level to a second level in a stepwise manner; and programming the target memory cell with a stylized voltage, the auxiliary The voltage is greater than the transfer voltage, and the auxiliary voltage is less than the programmed voltage, wherein the step of programming the target memory cell by using the programmed voltage comprises: providing the programmed voltage to the power Connecting a fourth character line of the target memory cell; and adjusting the stylized voltage such that the stylized voltage gradually rises from a third level in the step manner, and the second level is smaller than the third level Level. A memory device includes: a memory array including a first transistor, a memory string and a second transistor connected in series, and the memory string includes a target memory cell and the target memory cell Adjacent one of the first and second peripheral memory cells, and the target memory cell An adjacent plurality of non-target memory cells; and a circuit electrically connected to the memory array, wherein during a stylization, the circuit: turning on the first transistor and turning off the second transistor; using a transfer voltage Turning on the non-target memory cells, and using an auxiliary voltage to turn on the first peripheral memory cell and the second peripheral memory cell; and programming the target memory cell by using a stylized voltage, wherein the auxiliary voltage is greater than the transfer voltage And the auxiliary voltage is less than the stylized voltage; maintaining the transfer voltage at a first level; adjusting the auxiliary voltage to cause the auxiliary voltage to rise from the first level to a second level in a stepwise manner And adjusting the stylized voltage such that the stylized voltage gradually rises from a third level in the step manner, and the second level is less than the third level.