CN104934063B

CN104934063B - Semiconductor memory device and erasing method

Info

Publication number: CN104934063B
Application number: CN201410097177.8A
Authority: CN
Inventors: 妹尾真言
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2014-03-17
Filing date: 2014-03-17
Publication date: 2020-04-03
Anticipated expiration: 2034-03-17
Also published as: CN104934063A

Abstract

The invention discloses a semiconductor storage device with high reliability and data erasing method. The erasing method is to erase a semiconductor memory device formed with a memory array having NAND strings. A predetermined level is applied to the gate of the select transistor of the NAND string and a predetermined level is applied to the word line of the memory cell of the NAND string. An erase voltage is applied to a substrate region where a NAND string is formed at time 1, and a gate of a selection transistor is floated at time 2 after a fixed time from time 1. The invention can reduce the influence of the electric field on the memory cell adjacent to the selection transistor.

Description

Semiconductor memory device and erasing method

Technical Field

The present invention relates to a semiconductor memory device of a NAND flash memory (NAND flash memory), and more particularly, to a semiconductor memory device and an erasing method thereof.

Background

A NAND type flash memory is known to have a memory cell array including NAND strings in which a plurality of memory cells are connected in series, and to program or erase binary data or multi-data in the memory cells. As the device is refined, the distance between the bit line select transistor or the source line select transistor of the NAND string and the memory cell becomes smaller, and the capacitive coupling between the devices or with the substrate becomes larger, so that an unintended operation may occur. For example, patent document 1 discloses the following technique: in order to prevent the channel level of the NAND string boosted by coupling at the time of write operation from being transmitted to the bit line selection transistor, a dummy memory cell is inserted between the bit line selection transistor and the memory cell, and at the time of write operation, the dummy memory cell is used to block the connection between the bit line selection transistor and the memory cell.

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2011-192349

Disclosure of Invention

Fig. 1 is a circuit diagram showing an example of a NAND string array in which dummy memory cells are inserted. As shown in this figure, n + 1 NAND strings NU connecting a plurality of memory cells in series are arranged in the row direction in 1 block. The 1 NAND string NU includes a plurality of memory cells MCi (i =0, 1, …, 63) connected in series, a pair of dummy memory cells DMC connected at both ends of the memory cells, a bit line selection transistor TD connected to a drain of one dummy memory cell DMC, and a source line selection transistor TS connected to a source of another dummy memory cell DMC, and the drain of the bit line selection transistor TD is connected to the corresponding 1 bit line GBL, and the source of the source line selection transistor TS is connected to a common source line SL. The NAND strings NU constituting a block are formed in a P-well.

The control gates of memory cells MCi are connected to word line WLi, the control gates of dummy memory cells DMC are connected to dummy word line DWL, and the gates of select transistors TD and TS are connected to select gate lines SGD and SGS that are aligned with word line WL. The dummy memory cell DMC is configured similarly to the memory cell MC, and is biased similarly to the memory cell MC, but is excluded from the data program object.

Table 1 is a table showing an example of bias voltages applied in each operation of the flash memory. The read operation is performed by applying a positive voltage to the bit line, applying a voltage (e.g., 0V) to the selected word line, applying a read path voltage (e.g., 4.5V) to the unselected word line, applying a positive voltage (e.g., 4.5V) to the select gate lines SGD and SGS, turning on the bit line select transistor TD and the source line select transistor TS, and applying 0V to the common source line. A voltage equal to, for example, the read path voltage is applied to the dummy word line DWL. In the programming (writing) operation, a high-voltage programming voltage Vprog (15 to 20V) is applied to a selected word line, an intermediate level (for example, 10V) is applied to a non-selected word line, the bit line selection transistor TD is turned on, the source line selection transistor TS is turned off, and a level corresponding to "0" or "1" data is supplied to the bit line GBL. The dummy word line is applied with a voltage equal to, for example, the intermediate level. The erase operation applies 0V to the selected word line in the block and applies a high voltage (e.g., 18V) to the P-well to float the select gate lines SGD and SGS. The dummy word line DWL is applied with 0V as in the selected word line. Therefore, electrons of the floating gate are extracted to the substrate, and data erasing is performed by taking the block as a unit.

TABLE 1

Fig. 2 shows a flow of an erase operation of a conventional flash memory. 0V is applied to the dummy word line DWL and the word lines WL 0-WL 63 of the selected block (S100), and then the bit line selection transistor TD and the source line selection transistor TS are floated (S110). Next, an erase voltage is applied to the P-well in the substrate (S120), and a fixed time is waited to elapse for erasing (S130). An erase voltage is applied between the control gates of the memory cell MCi and the dummy memory cell DMC and the P-well, electrons in the floating gate are extracted into the P-well by FN tunneling, and the threshold (threshold) of the memory cell MCi and the dummy memory cell DMC is shifted to be negative.

Fig. 3 is a schematic diagram showing voltage changes of the P-well, the selection transistor TD/TS, the memory cell MC, and the dummy memory cell DMC during an erase operation. V_PWIs the voltage of the P well, V_TD、V_TSIs the gate voltage of the bit line select transistor TD and the source line select transistor TS. At time t0, 0V is applied to the word line WL and the dummy word line DWL, and the bit line selection transistor TD and the source line selection transistor TS are set to a floating state. At time t1, an erase voltage is applied to the P-well. For example, an erase pulse in which a voltage becomes large in stages is applied to the P-well. Voltage V of P well_PWThe boosting is started in response to the application of the erase pulse. Simultaneously, the gate voltage V of the selection transistors TD and TS capacitively coupled to the P-well is set_TD、V_TSBoosting as indicated by the dashed line in the figure. At time t2, the voltage V of the P-well is set_PWThe voltage is raised to about 18V, and a fixed time required for erasing is ensured to pass during the period from t2 to t3 (S130 of fig. 2), and electrons are extracted from the floating gate to the P-well.

In the erasing period t2 to t3, the gate voltage V of the selection transistors TD and TS is set by the coupling ratio with the P-well_TD、V_TSSet to a fixed level or less. That is, as shown in FIG. 3, if the voltage V of the P-well is not applied_PWAnd the gate voltage V of the selection transistors TD, TS_TD、V_TSWhen the level difference Va of (a) is equal to or less than a fixed value, the selection transistors TD and TS are likely to be broken down by Time Dependent Dielectric Breakdown (TDDB). TDDB is a phenomenon in which a transistor breaks down when a voltage is applied for a long time even when a high voltage is not applied to the gate of the transistor. Due to the fact thatSo as to satisfy Va < V_PWTDDB, the coupling ratio between the selection transistors TD, TS and the P-well is set. For example, the gate voltage V of the transistors TD, TS is to be selected_TD、V_TSBoosting to about 17V, and setting Va to 18V-17V to 1V.

However, if the gate voltage V of the transistors TD, TS is selected_TD、V_TSA high voltage results in the dummy memory cell DMC adjacent thereto being affected by the high voltage of the select transistors TD, TS. If the distances between the selection transistors TD and TS and the dummy memory cells DMC are reduced due to the refinement, the dummy memory cells DMC are boosted due to the capacitive coupling with the selection transistors TD and TS, and the threshold values of the dummy memory cells DMC may not be sufficiently shifted to a negative value during erasing. The threshold value of the dummy memory cell DMC is preferably the same as the threshold value of the memory cell MC, and if the threshold value of the dummy memory cell DMC is not stabilized, the variation in the threshold value distribution of the memory cell MC becomes large, or the read operation or the program operation becomes unstable.

The invention provides a data erasing method and a semiconductor memory device with high reliability.

In an erasing method of a semiconductor memory device of the present invention, a predetermined level is applied to a gate of a selection transistor of a NAND string, a predetermined level is applied to a word line of a memory cell of the NAND string, an erasing voltage is applied to a substrate region where the NAND string is formed at a 1 st timing, and the gate of the selection transistor is floated at a 2 nd timing after a fixed time from the 1 st timing. Preferably, the NAND string includes a dummy memory cell between the selection transistor and the memory cell, and the dummy word line of the dummy memory cell is floated at a 3 rd timing after a fixed time from the 2 nd timing. Preferably, the gate of the select transistor is boosted to a 1 st level by capacitive coupling with the substrate region, and the 1 st level is less than the erase voltage. Preferably, the 1 st level is boosted to a voltage above which the select transistor is not broken down by TDDB. Preferably, the dummy word line of the dummy memory cell is boosted to a level 2 by capacitive coupling with the substrate region, and the level 2 is less than the level 1.

The semiconductor memory device of the present invention includes: a memory array in which a NAND string is formed, the NAND string including a plurality of memory cells connected in series, a 1 st selection transistor connecting one memory cell to a bit line, and a 2 nd selection transistor connecting the other memory cell to a source line; and an erase element to select a block from the memory array and erase data of memory cells within the selected block; the erasing element applies an erasing voltage to the substrate area of the selected block at a 1 st time after a predetermined voltage is applied to the selection gate lines of the 1 st and 2 nd selection transistors and the word lines of the plurality of memory cells in the selected block, and floats the selection gate lines of the 1 st and 2 nd selection transistors at a 2 nd time after a fixed time from the 1 st time. Preferably, the NAND string includes a 1 st dummy memory cell between the 1 st select transistor and the memory cell and a 2 nd dummy memory cell between the 2 nd select transistor and the memory cell, and the erase element floats a dummy word line of the dummy memory cell at a 3 rd timing after a fixed time from the 2 nd timing. Preferably, the gates of the 1 st and 2 nd select transistors are boosted to a 1 st level by capacitive coupling with the substrate region, and the 1 st level is less than the erase voltage. Preferably, the 1 st level is boosted to a voltage at which the 1 st and 2 nd selection transistors are not broken down by TDDB or more. Preferably, the dummy word lines of the 1 st and 2 nd dummy memory cells are boosted to a 2 nd level by capacitive coupling with the substrate region, and the 2 nd level is less than the 1 st level.

According to the present invention, compared to the case where the selection transistor is boosted by capacitive coupling when the erase voltage is applied in the conventional manner, the boosting level of the selection transistor can be suppressed, and thereby the influence of the electric field on the memory cell adjacent to the selection transistor can be reduced.

Drawings

Fig. 1 is a circuit diagram showing a configuration of a NAND string of a flash memory.

Fig. 2 is a flowchart showing an erase operation of a conventional flash memory.

Fig. 3 is a schematic diagram showing voltage changes of the P-well, the selection transistor, the memory cell, and the dummy memory cell in the conventional erase.

Fig. 4 is a block diagram showing an example of the configuration of the flash memory according to the embodiment of the present invention.

FIG. 5 is a flow chart showing an erase operation of the flash memory according to the embodiment of the present invention.

Fig. 6 is a schematic diagram showing voltage changes of the P-well, the selection transistor, the memory cell, and the dummy memory cell in the erasing operation of the present embodiment.

Fig. 7 is a schematic cross-sectional view showing a NAND string of the present embodiment.

Fig. 8 is a block diagram showing an example of the word line driving circuit of the present embodiment.

Wherein the reference numerals are as follows:

100: flash memory

110: memory array

120: input/output buffer

130: address temporary storage

140: data temporary storage

150: controller

160: word line selection circuit

162: driving circuit

164: selection circuit

170: page buffer/sensing circuit

180: column selection circuit

190: internal voltage generating circuit

200: p well

Ax: line address information

Ay: column address information

C1, C2, C3: control signal

BL, GBL: bit line

BLK (0), BLK (1), …, BLK (m): block

DMC: virtual memory unit

DWL: dummy word line

F: floating body

M1-M68: transmission transistor

MC 0-MC 63: memory cell

NU: NAND string

S100, S110, S120, S130, S200, S210, S220, S230, S240, S250, S260, S270: step (ii) of

SGD, SGS: select gate line

SL: source line

SGD, SGS: select gate line

t0, t1, t2, t2', t3, t3', t4, t 5: time of day

TD, TS: selection transistor

Va: level difference

V1, V2, Vers, Vpass, Vprog, VPW, Vread, VTD, VTS: voltage of

WL, WL 0-WL 63: word line

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the drawings emphatically show the respective parts for ease of understanding the description, so it should be noted that the scale is different from that of the actual apparatus.

[ examples ]

Fig. 4 is a block diagram showing the configuration of a flash memory according to an embodiment of the present invention. However, the configuration of the flash memory shown here is an example, and the present invention is not necessarily limited to this configuration.

The flash memory 100 of the present embodiment includes: a memory array 110 in which a plurality of memory cells are arranged in a matrix; an Input/Output buffer 120 connected to an external Input/Output (I/O) terminal and storing Input/Output data; an address register 130 for receiving address data from the input/output buffer 120; a data register 140 for storing input/output data; a controller 150 for supplying control signals C1, C2, C3, and the like, wherein the control signals C1, C2, C3, and the like control the respective sections based on Command data from the input/output buffer 120 and an external control signal (a Command Latch Enable (CLE) signal or an Address Latch Enable (ALE) signal, and the like, which are not shown); a word line selection circuit 160 for selecting the word line from the address register 130Decoding the column address information Ax, and selecting a block, a word line, and the like based on the decoding result; a page buffer/sensing circuit 170 for storing data read from the page selected by the word line selecting circuit 160 or storing data written to the selected page; a column selection circuit 180 for decoding the column address information Ay from the address register 130 and selecting column data in the page buffer 170 based on the decoding result; and an internal voltage generation circuit 190 for generating voltages (programming voltage V) necessary for reading data, programming, erasing, and the like_progPath voltage V_passA read path voltage V_readErase voltage V_ersEtc.).

The memory array 110 has a plurality of blocks BLK (0), BLK (1), …, BLK (m) arranged in a column direction. At one end of the block, a page buffer/sensing circuit 170 is disposed. However, the page buffer/sensing circuit 170 may be disposed at the other end of the block or at both ends. In the 1 block, for example, as shown in fig. 1, a plurality of NAND string cells NU in which a plurality of memory cells are connected in series are formed.

Memory cell MC_iThe control gate of the transistor is connected to a word line WL_iThe control gates of the dummy memory cells DMC are connected to a dummy word line DWL, and the gates of the select transistors TD and TS are connected to select gate lines SGD and SGS arranged in parallel with the word line WL and the dummy word line DWL. The word line selection circuit 160 selects a block and word lines WL/dummy word lines DWL based on the row address Ax, and selectively drives the selection transistors TD and TS by selection gate signals SGS and SGD.

Typically, a memory cell has a MOS (metal-oxide-semiconductor) structure including source/drain electrodes of N-type diffusion regions formed in a P-well, a tunnel oxide film formed on a channel between the source/drain electrodes, a floating gate (charge storage layer) formed on the tunnel oxide film, and a control gate formed on the floating gate with a dielectric film interposed therebetween. The P-well is formed in an N-well formed in, for example, a P-type silicon substrate. When no charge is stored in the floating gate, i.e., when data "1" is written, the threshold is in a negative state and the memory cell is normally on. When electrons are stored in the floating gate, i.e., when data "0" is written, the threshold shift is positive and the memory cell is normally off. The storage unit may store binary data or multivariate data.

Next, an erase operation of the flash memory of the present embodiment will be described. Fig. 5 is a flowchart showing an erase operation, fig. 6 is a schematic diagram showing a voltage change of each portion at the time of erase, and fig. 7 is a schematic cross-sectional view of a NAND string.

Preferably, when the controller 150 receives an erase command or the like from a host side (not shown), the erase operation is performed. First, the word line selection circuit 160 selects a block to be erased based on the column address information Ax under the control of the controller 150, and applies the selected block to the memory cells MC in the selected block_iThe word lines WL0 to WL63 and the dummy word line DWL of the dummy memory cell DMS are applied with 0V (S200), and 0V is applied to the select gate lines SGD and SGS of the bit line select transistor TD and the source line select transistor TS of the selected block (S210). The source line SL and the bit line BL are floating. The operations of step S200 and step S210 may be performed simultaneously, or step S210 may be performed before step S200. Steps S200 and S210 are performed to apply a voltage at time t0 in fig. 6.

Subsequently, the erase voltage V is applied to the P-well 200 (see fig. 7)_ers(S220). Erase voltage V_ersIs generated by the internal voltage generating circuit 190 and applied to the P-well by a circuit not shown. It is preferable to apply an erase pulse of which voltage gradually increases to the P well a plurality of times to raise the P well to an erase voltage V_ers. The erasing voltage V_ersApplication is started at time t1 of fig. 6. At time t1, the select gate lines SGD and SGS and the word line WL are connected to each other_iThe dummy word line DWL is applied with 0V, so that the bit line selection transistor TD, the source line selection transistor TS, and the memory cell MC are formed_iAnd the control gate of the dummy memory cell DMC is not capacitively coupled to the P-well and remains fixed at 0V.

Then, at time t2 after a fixed time has elapsed from time t1,the selection gate lines SGD and SGS of the bit line selection transistor TD and the source line selection transistor TS are turned on, and the selection transistors TD and TS are floated (S230 and S240). Thus, the gates 210 (fig. 7) of the bit line select transistor TD and the source line select transistor TS are capacitively coupled to the P-well 200, and the boosting of the select transistors TD/TS is started. The dotted line in FIG. 6 indicates the voltage V of the selection transistor TD/TS_TD、V_TSCoupled with P-well voltage V due to capacitance_PWRising proportionally.

Next, at time t3 after a fixed time has elapsed from time t2, the dummy word line DWL of the dummy memory cell DMC is turned on, and the dummy memory cell DMC is floated (S250 and S260). Thereby, the control gate 220 of the dummy memory cell DMC is capacitively coupled to the P-well 200, and boosting starts. The dashed line in FIG. 6 indicates that the dummy word line DWL is capacitively coupled to the P-well voltage V_PWRising proportionally. Then, the self-P well voltage V_PWTo an erase voltage V_ersUntil time t4 to time t5, it waits for a fixed time required for erasing to elapse (S270), thereby ending part or all of the erasing operation.

As shown in FIG. 6, an erase voltage V is applied to the P-well 200_esrAt time t0, the gate voltage V of transistors TD and TS is selected_TD、V_TSFixed to 0V, and at time t2 delayed from time t1, selection transistors TD and TS are floated. As a result, the selection transistor TD/TS and the P well 200 are capacitively coupled with each other with a delay time, and the gate voltage V is set to be lower than the threshold voltage_TD、V_TSIs suppressed. For example, the gate voltage V_TD、V_TSThe voltage is increased to about 13V, which is lower than the voltage 17V in the conventional case shown in fig. 3.

If the gate voltage V of the transistors TD, TS is selected_TD、V_TSAs in the conventional case, when the voltage is increased to about 17V, the control gate 220 of the dummy memory cell DMC is boosted by the capacitive coupling with the selection transistors TD and TS, and a constant electric field is generated in the floating gate, so that the erase of the dummy memory cell DMC is insufficient, and the threshold value cannot be shifted to a negative value sufficiently. The dummy memory cell DMC is a select transistor TD,TS suppresses the over-erasing or over-programming of the memory cell MC due to the electric field influence of the dummy memory cell DMC, and the threshold value of the dummy memory cell DMC is preferably equal to the threshold value of the memory cell MC. In this embodiment, the gate voltage V of the selection transistors TD and TS is suppressed_TD、V_TSThe influence of the selection transistors TD and TS on the dummy memory cell DMC is suppressed, and the threshold value of the dummy memory cell DMC is sufficiently shifted in the negative direction.

On the other hand, if the gate voltage V of the transistors TD, TS is selected_TD、V_TSBecome small, the gate voltage V will be reduced_TD、V_TSAnd P well voltage V_PWLevel difference V of_aBecomes too large, V will not be satisfied_a＜V_PWTDDB, causing the selection transistors TD, TS to break down due to TDDB. Due to V_a＝V_PW－（V_TD、V_TS）＜V_PWTDDB, so that (V) is satisfied_TD、V_TS) Is more than TDDB. Assuming TDDB is about 5V, the gate voltage V is set_TD、V_TSRaising the pressure to more than 5V.

Gate voltage V_TD、V_TSMay be adjusted by time t2 at which the select transistors TD, TS are floated. As shown in fig. 6, when the selection transistors TD and TS are floated at time t2' later than time t2, the start time of capacitive coupling between the selection transistors TD and TS and the P-well is delayed, and therefore, the gate voltage V is increased_TD、V_TSThe pressure rise of (2) is suppressed and becomes smaller by V1 than that at the time of pressure rise at time t 2. By adjusting the timing at which the selection transistors TD, TS are floated in this manner, the gate voltage V corresponding to TDDB can be set_TD、V_TSAnd (4) boosting the voltage.

Further, in this embodiment, the control gate 220 of the dummy memory cell DMC can be boosted to a fixed level lower than the boosting levels of the selection transistors TD and TS by floating the dummy word line DWL from 0V at time t 3. Thus, the adjacent memory cells MC63 and MC0 are partially capacitively coupled, and the control gates of the memory cells MC63 and MC0 are set to have the same levelThe memory cells MC63 and MC0 are prevented from being excessively erased due to the dry rise, and variation in the threshold value is suppressed. Preferably, dummy word line DWL is floated after select transistors TD and TS (after time t 2) and P-well voltage V is applied_PWTo reach the erasing voltage V_ersBefore (18V) (before time t 3), floating. Thus, the voltage V of the dummy word line DWL and the P well can be increased_PWAnd is boosted proportionally. As described above, when the floating of the dummy word line DWL is delayed from time t3 to time t3', the start time of capacitive coupling with the P-well is delayed, and therefore, the boosted voltage is lower by V2 than the boosted voltage at time t 3.

This is done. In this embodiment, the time t2 at which the selection transistors TD and TS are brought into a floating state is delayed from the time t1 at which the erase voltage is applied, and the start time of capacitive coupling between the selection transistors TD and TS and the P-well is delayed, so that the boosting levels of the selection transistors TD and TS at the time of erasing are kept constant or less, thereby reducing the influence on the dummy memory cells DMC. Further, the selection transistors TD and TS are capacitively coupled to the P-well voltage V_PWThe voltage is boosted in proportion, so that the damage of the boosting to the selection transistors TD and TS can be reduced.

The selection gate signals SDG and SGS of the selection transistors TD and TS and the driving control of the dummy word line DWL of the dummy memory cell DMC are performed by the word line selection circuit 160. The word line selection circuit 160 can accurately control the floating time of the selection transistors TD and TS or the dummy word line DWL based on a predetermined setting by using a well-known circuit technique such as a clock control or a delay circuit.

Fig. 8 is a diagram showing an internal configuration example of the word line driving circuit. As shown in this figure, the driver circuit 162 supplies predetermined voltages to the select gate lines SGD and SGS, the dummy word line DWL, and the word line WL via the transfer transistors M1 to M68 having nMOS (n-channel metal-oxide-semiconductor) structures. The selection circuit 164 supplies a selection control signal to the gates of the transfer transistors M1 to M68, and controls the transfer transistors M1 to M68 to be turned on and off.

While performing the selection of the memory arrayWhen erasing the selected block, the drive circuit 162 supplies 0V to the select gate lines SGD and SGS, the dummy word line DWL, and the word line WL, and the select circuit 164 supplies the select control signal of H level (H level) to the transfer transistors M1 to M68, thereby turning on the transfer transistors M1 to M68. Next, at time t1, the erasing voltage V starts to be applied to the P-well 200 by a circuit not shown in the figure_ersApplication of (1). Next, at time t2, the selection circuit 164 supplies a selection control signal at the L level (lllevel) to turn off the transfer transistors M1 and M68 connected to the selection gate lines SGD and SGS. At time t3, the selection circuit 164 supplies the L-level selection control signal to turn off the transfer transistors M2 and M67 connected to the dummy word line DWL.

The embodiment is an example showing that the NAND string includes dummy memory cells on both end sides, but the present invention may also be a NAND string without dummy memory cells. That is, the present invention can also be applied to a NAND string in which the memory cell MC63 is connected to the bit line select transistor TD and the memory cell MC0 is connected to the source line select transistor TS. In the above embodiment, 0V is applied to the select gate lines SGD and SGS of the select transistors TD and TS or the gates thereof before the erase voltage is applied to the P-well region, but the select transistors TD and TS may be fixed to a voltage that is not boosted by the capacitive coupling with the P-well. Further, in the above embodiment, the N-well region is formed on the P-type semiconductor substrate, and the P-well region is formed in the N-well region, but this case is merely an example, and the NAND string may be formed on the P-type semiconductor substrate.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the spirit of the present invention described in the scope of claims.

Claims

1. An erasing method of a semiconductor memory device in which a memory array having a nand string is formed, the erasing method comprising:

applying a predetermined level to a gate of a select transistor of the NAND string, applying the predetermined level to a word line of memory cells of the NAND string, the NAND string including a dummy memory cell between the select transistor and the memory cells, and applying the predetermined level to the dummy memory cell,

applying an erase voltage to a substrate region where the NAND string is formed at a 1 st timing after the predetermined level is applied to the gate of the selection transistor, the word line of the memory cell, and the dummy memory cell, and

floating the gate of the selection transistor at a 2 nd time after a fixed time from the 1 st time, boosting a dummy word line of the dummy memory cell to a 2 nd level by capacitive coupling with the substrate region, and the 2 nd level being less than the erase voltage.

2. An erasing method as claimed in claim 1, characterized in that: floating the dummy word line of the dummy memory cell at a 3 rd time after a fixed time from the 2 nd time.

3. An erasing method as claimed in claim 1, characterized in that: the gate of the select transistor is boosted to a 1 st level with capacitive coupling to the substrate region, and the 1 st level is less than the erase voltage.

4. An erasing method according to claim 3, characterized in that: the 1 st level is boosted to a voltage higher than a voltage at which the selection transistor is not broken down by the time-dependent dielectric layer breakdown.

5. An erasing method according to claim 3, characterized in that: the 2 nd level is less than the 1 st level.

6. A semiconductor memory device, comprising:

a memory array in which a nand string including a plurality of memory cells connected in series, a 1 st selection transistor connecting one of the memory cells to a bit line, and a 2 nd selection transistor connecting the other of the memory cells to a source line is formed, the nand string including a 1 st dummy memory cell between the 1 st selection transistor and the memory cell, and a 2 nd dummy memory cell between the 2 nd selection transistor and the memory cell; and

an erase element to select a block from the memory array and erase data of the memory cells within the selected block,

the erase element applies an erase voltage to a substrate area of the selected block at a 1 st timing after a predetermined voltage is applied to a select gate line of the 1 st and 2 nd select transistors, word lines of the plurality of memory cells, the 1 st dummy memory cell, and the 2 nd dummy memory cell in the selected block, and floats the select gate line of the 1 st and 2 nd select transistors at a 2 nd timing after a fixed time from the 1 st timing, the dummy word lines of the 1 st and 2 nd dummy memory cells are boosted to a 2 nd level by capacitive coupling with the substrate area, and the 2 nd level is less than the erase voltage.

7. The semiconductor memory device according to claim 6, wherein: the erasing element makes the virtual word line of the 1 st and 2 nd virtual memory cells float at the 3 rd time after the fixed time from the 2 nd time.

8. The semiconductor memory device according to claim 6, wherein: the gates of the 1 st and 2 nd select transistors are boosted to a 1 st level by capacitive coupling with the substrate region, and the 1 st level is less than the erase voltage.

9. The semiconductor memory device according to claim 8, wherein: the 1 st level is boosted to a voltage at which the 1 st and 2 nd selection transistors are not broken down by the time-dependent dielectric breakdown.

10. The semiconductor memory device according to claim 8, wherein: the 2 nd level is less than the 1 st level.