TWI546923B - Package substrate, semiconductor package and method for forming the same - Google Patents

Description

Package substrate, semiconductor package and method of manufacturing same

The present invention relates to a package substrate, a semiconductor package, and a method of fabricating the same. More specifically, the present invention is a flip chip package substrate, a semiconductor package, and a method of fabricating the same.

Nowadays, with the development of science and technology, the manufacturers of electronic products have developed higher quality semiconductor packaging technology to follow the footsteps of technological development.

Flip Chip is one of the mainstream technologies of today's semiconductor packaging, which has the active side of the wafer facing down and is electrically connected to the substrate by bumps. In the early flip chip technology, the bumps were placed on the electrical connection pads of the circuit of the substrate; however, as the electronic products became more compact, shorter, and more functional, the wiring density of the chips became higher and higher. Crystal technology is no longer sufficient, so a bump-on-trace (BOT) type flip chip technology has been developed that attaches the bumps to smaller traces rather than areas. The larger electrical connection pads allow for the high line density of electronic products.

Please refer to FIGS. 1A to 1C' for a cross-sectional view of a conventional semiconductor package of a bump type above the trace and a method for fabricating the same, wherein the first C' The plan view is a plan view of Fig. 1C, and the 1Cth view is a partial enlarged view of the 1C' chart.

As shown in FIG. 1A, a substrate body 10 is provided, and a surface 101 is defined on a surface 101. The inner edge of the crystallographic region 11 defines an annular junction region 111 (see FIGS. 1A and 1C'). And forming a first circuit layer 12 on the surface in the middle of the crystallizing region 11, and the first circuit layer 12 has a plurality of first electrical contact pads 121 extending into the bonding region 111, and additionally, the crystal is formed. A second wiring layer 13 is formed on the surface of the edge of the region 11, and the second wiring layer 13 has a plurality of second electrical contact pads 131 extending into the bonding region 111, and then, in the middle of the crystallographic region 11 A first insulating protective layer 14 is formed on the first wiring layer 12, and then a second insulating protective layer 15 is formed on the surface of the edge of the crystalline region 11 and the second wiring layer 13.

As shown in FIG. 1B, an underfill material 16 is formed on the intermediate surface of the first insulating protective layer 14.

As shown in FIGS. 1C, 1C' and 1C", a semiconductor wafer 17 is provided, and the semiconductor wafer 17 has a plurality of conductive elements 18, and the semiconductor wafer 17 is overlaid by the conductive elements 18. On the substrate body 10, each of the conductive elements 18 is disposed on the first electrical contact pads 121 and the second electrical contact pads 131 in the bonding region 111, and the underfill material 16 is pressed by the semiconductor wafer 17. Flowing and distributed between the substrate body 10 and the semiconductor wafer 17, and the underfill material 16 covers the first circuit layer 12, the second circuit layer 13, the first insulating protective layer 14, and the second insulating layer a protective layer 15 and the conductive elements 18; wherein, for convenience The first semiconductor layer 17 is omitted, and only the first wiring layer 12 and the second wiring layer 13 are illustrated. However, as shown in FIG. 1C, the semiconductor wafer is When the substrate body 10 is attached to the substrate body 10, the underfill material 16 on the substrate body 10 is squeezed and distributed between the substrate body 10 and the semiconductor wafer 17, and the underfill material 16 is in the process of flowing. Air is entrapped, and finally a void 19 is formed between the adjacent two conductive elements 18 of the bottom insulating material 16 adjacent to the edge of the first insulating protective layer 14 and the second insulating protective layer 15, resulting in a subsequent Adjacent two conductive elements 18 are easily bridged through the air holes 19, thereby affecting the overall semiconductor package yield.

Therefore, how to overcome various problems of the prior art is an important issue.

In order to solve the problems of the above-mentioned prior art, the present invention discloses a package substrate, comprising: a substrate body; a first insulating protective layer is formed on a surface of the substrate body, wherein a surface of the substrate body defines a surrounding a bonding region of the first insulating protective layer, and a distance between the outer edge of the first insulating protective layer and the bonding region is greater than or equal to 0.05 mm; and the first circuit layer is formed in the first insulating protection On the surface of the substrate body under the layer, and having a plurality of first electrical contact pads extending into the bonding region.

In the foregoing package substrate, a second circuit layer is formed on the surface outside the bonding region, and has a plurality of second electrical contact pads extending into the bonding region.

The present invention further provides a semiconductor package, comprising: a substrate body; a first insulating protective layer formed on a surface of the substrate body, wherein a surface of the substrate body defines a bonding region surrounding the first insulating protective layer And the distance between the outer edge of the first insulating protective layer and the bonding region is greater than or equal to 0.05 mm; the first circuit layer is formed on the surface of the substrate body under the first insulating protective layer, and a first electrical contact pad having a plurality of extending to the bonding region; a plurality of conductive elements, each of the conductive elements being disposed on the first electrical contact pad in the bonding region; and a semiconductor wafer by the plurality of conductive elements The flip chip is disposed on the substrate body; and an underfill material is formed between the substrate body and the semiconductor wafer, and covers the first circuit layer, the first insulating protective layer and the conductive elements.

In the foregoing semiconductor package, the second circuit layer is formed on the surface outside the bonding region, and has a plurality of second electrical contact pads extending into the bonding region.

The invention further provides a method for fabricating a semiconductor package, comprising: providing a package substrate, comprising: a substrate body; a first insulating protective layer formed on a surface of the substrate body, wherein a surface definition of the substrate body a joint region surrounding the first insulating protective layer, and a distance between the outer edge of the first insulating protective layer and the joint region is greater than or equal to 0.05 mm; and a first circuit layer is formed on the first a surface of the substrate body under the insulating protective layer, and having a plurality of first electrical contact pads extending to the bonding region; forming an underfill on the first insulating protective layer; and a semiconductor by using a plurality of conductive elements Wafer flip chip placement On the substrate body, each of the conductive elements is disposed on a corresponding first electrical contact pad in the bonding region, and the underfill material is pressed by the semiconductor wafer and distributed between the substrate body and the semiconductor wafer, so that The underfill material encapsulates the first circuit layer, the first insulating protective layer, and the conductive elements.

In the above method of fabricating a semiconductor package, the package substrate further includes a second wiring layer formed on a surface outside the bonding region and having a plurality of second electrical contact pads extending into the bonding region.

According to the above, the present invention is such that the distance between the outer edge of the first insulating protective layer and the bonding region is greater than or equal to 0.05 mm, and the second insulating protective layer is not disposed to prevent the gas hole from finally remaining in the same. Between the conductive elements; or a second insulating protective layer is disposed on the surface of the package substrate outside the bonding region and the second circuit layer, but the underfill material does not cover the second insulating protective layer, and the gas can be avoided. a hole is formed in the vicinity of the second insulating protective layer; or a second insulating protective layer is disposed on the surface of the edge of the crystallographic region of the package substrate and the second circuit layer, and the underfill material covers the second insulating protective layer However, if the distance between the inner edge of the second insulating protective layer and the bonding region is greater than or equal to 0.3 mm, it is also possible to prevent the gas hole from remaining between the conductive members. Therefore, the invention can effectively avoid the bridging phenomenon of the conductive elements, thereby improving the product yield.

10, 20, 30‧‧‧ substrate body

101, 201, 301‧‧‧ surface

11, 21, 31‧‧ ‧ crystal area

111, 211, 311‧‧‧ joint area

12, 22, 32‧‧‧ first line layer

121, 221, 321‧‧‧ first electrical contact pads

13, 23, ‧ ‧ second circuit layer

131, 231, 331‧‧‧ second electrical contact pads

14, 24, 34‧‧‧ first insulating protective layer

241, 341‧‧‧ outer edge sidewall

15, 35‧‧‧Second insulation protection layer

16, 25, 36, 36'‧‧‧ bottom filler

17, 26, 37‧‧‧ semiconductor wafer

18, 27, 38‧‧‧ conductive elements

19‧‧‧ gas tunnel

351‧‧‧ inner edge sidewall

D1, d2, d3‧‧‧ distance

1A to 1C' are schematic cross-sectional views showing a conventional semiconductor package of a bump type above the trace and a method for fabricating the same, wherein the 1C' is a plan view of the 1Cth, and the 1C' is a 1C 'A partial enlarged view of the figure; 2A and 2B are the package substrate and the semiconductor package of the present invention. And a schematic view of a first embodiment of the method, wherein the second drawing is a cross-sectional view, and the second drawing is a top view of the second drawing; 3A and 3B are schematic views of a second embodiment of a package substrate, a semiconductor package, and a method for fabricating the same according to the present invention, wherein the 3A and 3A' views are cross-sectional views of different embodiments, and FIG. 3B is a A top view of Figure 3A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "upper", "side", "outside", "edge", "inner edge", "middle", "one" and "two" cited in this manual are also for convenience only. The description is not intended to limit the scope of the invention, and the changes or adjustments of the relative relationship are also considered to be within the scope of the invention.

First embodiment

Hereinafter, a schematic diagram of a first embodiment of a package substrate, a semiconductor package, and a method of fabricating the same according to the present invention will be described in detail with reference to FIGS. 2A and 2B, wherein Fig. 2A is a cross-sectional view, and Fig. 2B is a plan view of Fig. 2A.

As shown in the figure, a substrate body 20 is provided, and a surface 201 is defined on a surface 201, and an annular junction region 211 is defined in the crystal region 21, and a surface is formed on the surface of the crystal region 21. a circuit layer 22, and the first circuit layer 22 has a plurality of first electrical contact pads 221 extending into the bonding region 211 on the surface near the edge of the crystallizing region 21, that is, outside the bonding region 211 A second wiring layer 23 is formed on the surface 201, and the second wiring layer 23 has a plurality of second electrical contact pads 231 extending into the bonding region 211. Moreover, in this context, the boundary of the land 211 is determined by the conductive elements 27 formed on the first circuit layer 22 and/or the second circuit layer 23, respectively.

Then, a first insulating protective layer 24 is formed on the surface in the middle of the crystallizing region 21 and the first wiring layer 22, so that the bonding region 211 surrounds the first insulating protective layer 24, and the first insulating protective layer The distance d1 between the outer edge side wall 241 and the joint area 211 is greater than or equal to 0.05 mm.

Then, an underfill material such as an underfill or a non-conductive paste (NCP) is formed on the first insulating protective layer 24, and the semiconductor wafer 26 is over-crystallized by a plurality of conductive elements 27. The substrate is disposed on the substrate body 20, and each of the conductive elements 27 is disposed on the corresponding first electrical contact pad 221 and the second electrical contact pad 231 in the bonding region 211, and the underfill material 25 is received by the semiconductor wafer. 26 is extruded and distributed between the substrate body 20 and the semiconductor wafer 26, and the underfill material 25 covers the first circuit layer 22, the second circuit layer 23, the first insulating protective layer 24, and the like. Conductive element 27, in addition, the The conductive element 27 is a solder bump.

It is to be noted that, for convenience of explanation, FIG. 2B omits the first wiring layer 22, the second wiring layer 23, the underfill material 25, the semiconductor wafer 26, and the conductive member 27.

Second embodiment

A schematic diagram of a second embodiment of a package substrate, a semiconductor package, and a method for fabricating the same according to the present invention will be described in detail with reference to FIGS. 3A and 3B, wherein FIGS. 3A and 3A' are cross-sectional views of different embodiments. The 3B diagram is a top view of the 3A diagram.

As shown in FIGS. 3A and 3B, a substrate body 30 is provided, and a surface 301 defines a crystal region 31 defining an annular land 311 in the middle of the crystal region 31. A first circuit layer 32 is formed thereon, and the first circuit layer 32 has a plurality of first electrical contact pads 321 extending into the bonding region 311 on a surface close to the edge of the crystallizing region 31, that is, the bonding A second wiring layer 33 is formed on the surface 301 outside the region 311, and the second wiring layer 33 has a plurality of second electrical contact pads 331 extending into the bonding region 311.

Next, a first insulating protective layer 34 is formed on the surface of the intermediate portion 31 and the first wiring layer 32. The bonding region 311 surrounds the first insulating protective layer 34, and the first insulating protective layer 34 The distance d2 between the outer edge sidewall 341 and the joint region 311 is greater than or equal to 0.05 mm. Further, a second insulating protective layer 35 is formed on the surface 301 outside the joint region 311 and the second wiring layer 33.

Further, for example, a primer is formed on the first insulating protective layer 34. Underfill or underfill material 36 of Non-Conductive Paste (NCP), and semiconductor wafer 37 is flip-chip bonded to the substrate body 30 by a plurality of conductive elements 38, and each of the conductive elements 38 is The first electrical contact pad 321 and the second electrical contact pad 331 are disposed in the bonding region 311, and the underfill material 36 is pressed by the semiconductor wafer 37 to flow and distributed on the substrate body 30 and the semiconductor wafer. 37, and the underfill material 36 covers the first circuit layer 32, the second circuit layer 33, the first insulating protective layer 34 and the conductive elements 38, and the underfill material 36 does not cover the second The insulating protective layer 35, in addition, the conductive member 38 is a solder bump.

In addition, please refer to FIG. 3A′, which differs from FIG. 3A in that the distance d3 between the inner edge sidewall 351 of the second insulating protective layer 35 and the joint region 311 is greater than or equal to 0.3 mm, and the bottom portion The filler material 36' covers the second insulating protective layer 35. As for other related processes, they are similar, so they will not be described again.

It is to be noted that, for convenience of explanation, the first wiring layer 32, the second wiring layer 33, the underfill material 36, the semiconductor wafer 37, and the conductive member 38 are omitted in FIG. 3B.

The present invention further provides a package substrate, comprising: a substrate body 20, a first circuit layer 22, a second circuit layer 23, and a first insulating protective layer 24. A surface 201 is defined on a surface 201 of the substrate body 20. The inner edge of the crystallizing region 21 defines a bonding region 211 surrounding the first insulating protective layer 24, and the first wiring layer 22 is formed on the surface 201 of the substrate body 20 under the first insulating protective layer 24. Having a plurality of extensions to the junction area The first electrical contact pad 221 and the second circuit layer 23 are formed on the surface outside the bonding region 211 and have a plurality of second electrical contact pads 231 extending into the bonding region 211. In addition, the first insulating protective layer 24 is formed on the surface 201 of the substrate body 20, and the distance d1 between the outer edge sidewall 241 of the first insulating protective layer 24 and the joint region 211 is greater than or equal to 0.05 mm. .

In addition, the foregoing package substrate may be another implementation manner, and a second insulating protective layer 35 may be formed on the surface outside the bonding region 311 and the second wiring layer 33, and the inner edge sidewall 351 of the second insulating protective layer 35. The distance d3 from the land 311 is greater than or equal to 0.3 mm.

The present invention further provides a semiconductor package comprising: a substrate body 20, a first wiring layer 22, a second wiring layer 23, a first insulating protective layer 24, a semiconductor wafer 26, and an underfill material 25, the substrate body 20 A surface 201 is defined on a surface 201. The inner edge of the crystal region 21 defines a bonding region 211 surrounding the first insulating protective layer 24. The first wiring layer 22 is formed on the first insulating protective layer 24. On the surface 201 of the substrate body 20, and having a plurality of first electrical contact pads 221 extending into the bonding region 211, the second circuit layer 23 is formed on the surface outside the bonding region 211, and has The plurality of second electrical contact pads 231 extend into the junction region 211.

Moreover, the first insulating protective layer 24 is formed on the surface 201 of the substrate body 20, and the distance d1 between the outer edge sidewall 241 of the first insulating protective layer 24 and the joint region 211 is greater than or equal to 0.05. Millimeter.

The semiconductor wafer 26 is flip-chip mounted by a plurality of conductive elements 27. On the substrate body 20, each of the conductive elements 27 is disposed on the first electrical contact pad 221 or the second electrical contact pad 231 in the bonding region 211, and an underfill or a non-conductive paste is used, for example. The underfill material 25 is formed between the substrate body 20 and the semiconductor wafer 26 and covers the first circuit layer 22, the second circuit layer 23, and the first insulating protective layer 24 (Non-Conductive Paste, NCP). In addition to the conductive elements 27, the conductive elements 27 are solder bumps.

In addition, the present invention further provides another semiconductor package, which is different from the foregoing semiconductor package in that a second insulating protective layer 35 can be formed on the surface outside the bonding region 311 and the second wiring layer 33, and the first The distance d3 between the inner edge side wall 351 of the second insulating protective layer 35 and the joint region 311 is greater than or equal to 0.3 mm. As for other related processes, they are similar, so they will not be described again.

In the above semiconductor package, the underfill material 36 is formed between the substrate body 30 and the semiconductor wafer 37, and covers the first circuit layer 32, the second circuit layer 33, and the first insulating protective layer 34. The conductive material 38, the underfill material 36 does not cover the second insulating protective layer 35; or, in another embodiment, the underfill material 36 covers the first circuit layer 32 and the second circuit layer 33. The first insulating protective layer 34, a portion of the second insulating protective layer 35 and the conductive members 38, that is, the underfill material 36 covers the second insulating protective layer 35. Further, the conductive member 38 is solder bump. Piece.

In summary, the present invention is such that the distance between the outer edge of the first insulating protective layer and the joint region is greater than or equal to 0.05 mm, and the first Separating the protective layer to prevent the gas hole from remaining between the conductive elements; or providing a second insulating protective layer on the surface of the package substrate outside the bonding region and the second wiring layer, but the underfill is The material does not cover the second insulating protective layer, and the air hole is also prevented from being generated in the vicinity of the second insulating protective layer; or the second insulating protective layer is disposed on the surface of the edge of the crystallographic region of the package substrate and the second circuit layer. And covering the second insulating protective layer with the underfill material, but the distance between the sidewall of the inner insulating edge of the second insulating protective layer and the bonding region is greater than or equal to 0.3 mm, thereby preventing the gas hole from remaining in the same Between conductive elements. Therefore, the invention can effectively avoid the bridging phenomenon of the conductive elements, thereby improving the product yield.

The above embodiments are merely illustrative of the effects of the present invention and are not intended to limit the present invention, and those skilled in the art can practice the above embodiments without departing from the spirit and scope of the present invention. Make modifications and changes. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

20‧‧‧Substrate body

201‧‧‧ surface

21‧‧‧Setting area

211‧‧‧ junction area

22‧‧‧First circuit layer

221‧‧‧First electrical contact pads

23‧‧‧Second circuit layer

231‧‧‧Second electrical contact pads

24‧‧‧First insulation protection layer

241‧‧‧ outer edge sidewall

25‧‧‧Bottom filler

26‧‧‧Semiconductor wafer

27‧‧‧Conducting components

D1‧‧‧ distance

Claims (12)

A package substrate includes: a substrate body; a first insulating protective layer is formed on a surface of the substrate body, wherein a surface of the substrate body defines a bonding region surrounding the first insulating protective layer, and the first The distance between the outer edge of the insulating protective layer and the side of the first insulating protective layer is greater than or equal to 0.05 mm; the first circuit layer is formed on the substrate body under the first insulating protective layer a surface of the first electrical contact pad extending to the bonding region; a second circuit layer formed on a surface outside the bonding region and having a plurality of second electrodes extending to the bonding region And a second insulating protective layer formed on the surface outside the bonding region and the second wiring layer, and the distance between the sidewall of the second insulating protective layer and the bonding region is greater than or equal to 0.3 mm. A semiconductor package includes: a substrate body; a first insulating protective layer formed on a surface of the substrate body, wherein a surface of the substrate body defines a bonding region surrounding the first insulating protective layer, and the The distance between the outer edge of the insulating protective layer and the side of the first insulating protective layer is greater than or equal to 0.05 mm; the first circuit layer is formed under the first insulating protective layer a surface of the board body having a plurality of first electrical contact pads extending into the joint region; a second circuit layer formed on a surface outside the joint region and having a plurality of extensions extending into the joint region a second electrical contact pad; a second insulating protective layer formed on a surface outside the bonding region and the second wiring layer, and a distance between an inner edge sidewall of the second insulating protective layer and the bonding region is greater than Or equal to 0.3 mm; a plurality of conductive elements, each of the conductive elements being disposed on the first and second electrical contact pads in the bonding region; and the semiconductor wafer being overlaid on the substrate body by the plurality of conductive elements And an underfill material formed between the substrate body and the semiconductor wafer, and covering the first circuit layer, the first insulating protective layer and the conductive elements. The semiconductor package of claim 2, wherein the underfill material covers or does not cover the second insulating protective layer. The semiconductor package of claim 2, wherein the underfill is an underfill or a non-conductive paste (NCP). The semiconductor package of claim 2, wherein the conductive element is a solder bump. A method of fabricating a semiconductor package, comprising: providing a package substrate, comprising: a substrate body; a first insulating protective layer is formed on a surface of the substrate body, wherein a surface of the substrate body defines a bonding region surrounding the first insulating protective layer, and a sidewall of the first insulating protective layer is bonded to the sidewall The distance between the regions is greater than or equal to 0.05 mm; and the first circuit layer is formed on the surface of the substrate body under the first insulating protective layer and has a plurality of first electrical contacts extending into the bonding region a pad; an underfill material is formed on the first insulating protective layer; and a semiconductor wafer is overlying the substrate body by a plurality of conductive elements, each of the conductive elements being disposed in the first corresponding region of the bonding region On the electrical contact pad, the underfill material is pressed by the semiconductor wafer and distributed between the substrate body and the semiconductor wafer, so that the underfill material covers the first circuit layer, the first insulating protective layer and the Equal conductive elements. The method of manufacturing the semiconductor package of claim 6, wherein the package substrate comprises a second circuit layer formed on a surface outside the bonding region and having a plurality of second extending to the bonding region Electrical contact pads. The method of fabricating a semiconductor package according to claim 7, wherein the conductive element is disposed on a second electrical contact pad in the bonding region. The method of fabricating a semiconductor package according to claim 7, wherein a surface outside the bonding region and a second wiring layer are formed a second insulating protective layer, and a distance between an inner edge sidewall of the second insulating protective layer and the bonding region is greater than or equal to 0.3 mm. The method of fabricating a semiconductor package according to claim 9, wherein the underfill material covers or does not cover the second insulating protective layer. The method of fabricating a semiconductor package according to claim 6, wherein the underfill material is an underfill or a non-conductive paste (NCP). The method of fabricating a semiconductor package according to claim 6, wherein the conductive element is a solder bump.