TWI544489B - Memory device and method for operating the same - Google Patents

Description

Memory element and its operation method

The present invention relates to a semiconductor device and a method of operating the same, and more particularly to a memory device and method of operation thereof.

In general, a non-volatile memory can perform operations such as storing, reading, erasing, and the like of a plurality of data, and has an advantage that the stored data does not disappear when the power supply is interrupted. Therefore, non-volatile memory has become a memory component widely used in personal computers and electronic devices to maintain the normal operation of electrical products when they are turned on.

However, as the degree of integration of semiconductor components increases, the size of individual components in the memory component is also increasingly reduced. For example, when the memory cell size of the NAND flash memory is reduced, the critical size of the floating gate of the next 30 nm will also be limited. In order to achieve high density and high performance targets, in the manufacture of semiconductor components, it tends to form an upward stacked structure to more effectively utilize the wafer area. Therefore, semiconductor structures having a high aspect ratio are often found in small-sized components.

However, in the fabrication of the above-described high aspect ratio small-sized components, it is extremely challenging in lithography and etching processes. For example, a conductor layer near the surface of the substrate may be connected to an adjacent conductor layer due to incomplete etching. This phenomenon will cause problems such as slow program, charge loss, or charge gain when a subsequent voltage is applied to the device. Therefore, in the case where the etching process has not yet been broken, how to improve the above-mentioned electrical problems caused by incomplete etching is a subject of current research.

The present invention provides a method of operating a memory element that can improve the problems of slow stylization, charge loss, charge increase, and mutual interference between word lines.

The invention provides a method for operating a memory element, which can improve the gate coupling ratio (GCR) of the memory element.

The present invention provides a method of operating a memory element. The memory element includes a substrate, a plurality of word lines, and a plurality of dummy word lines. The word line and the virtual word line are located on a substrate. At least one side of each virtual word line is adjacent to the word line. At least one word line and at least one virtual word line form a group. The method of operating the above memory element includes the following steps. Select at least one group and operate on the above groups. A first bias voltage is applied to the word lines in the group. A second bias voltage is applied to the virtual word line in the group.

In an embodiment of the invention, when the first bias voltage is applied to the word line in the group, the second bias voltage is simultaneously applied to the virtual word line in the group.

In an embodiment of the invention, the word line in the group is the same as the potential of the virtual word line.

In an embodiment of the invention, each group includes two virtual word lines and one of the word lines, and the virtual word lines are respectively located on both sides of the word line.

The present invention provides a memory element comprising a substrate, a plurality of word lines, and a plurality of virtual word lines. Most of the word lines and a plurality of virtual word lines are on the substrate. At least one side of each virtual word line is adjacent to the word line. At least one word line and at least one virtual word line form a group. The potential of the word line and the virtual word line in the above group is the same.

In an embodiment of the invention, each group includes two virtual word lines and one of the word lines, and the virtual word lines are respectively located on both sides of the word line.

In an embodiment of the invention, the adjacent two groups comprise the same virtual word line.

In an embodiment of the invention, a portion of the word line is in contact with a portion of the virtual word line.

The present invention also provides a memory element comprising a substrate and a plurality of groups of word lines. Most of the character line groups are located on the substrate. Each group of word lines includes at least one word line and at least one virtual word line. The virtual character line is adjacent to the word line. The virtual word line has the same potential as the word line.

In an embodiment of the invention, a portion of the word line in the group of character lines is in contact with a portion of the virtual word line.

Based on the above, the method for operating a memory element according to the present invention, by forming a group including at least one word line and at least one virtual word line in the memory element, and the word line and the dummy word in the group The lines are biased separately. In this way, when the above bias voltages are the same, the word line and the virtual word line in the group have the same potential. Therefore, even if the word lines or dummy word lines in the memory element are connected to each other due to limitations in the etching process, the final potential of the word lines does not decrease due to the potential difference between them, thereby improving the slow stylization. The problem of charge loss, charge increase, and mutual interference between word lines can further increase the gate coupling ratio of the memory element and improve the raw bit error rate (RBER).

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1A is a top plan view of a memory device 100a according to an embodiment of the invention.

Referring to FIG. 1A, the memory element 100a includes a substrate 10 and a plurality of groups 101. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a silicon on insulator (SOI) substrate. The substrate 10 may include a single layer structure or a multilayer structure. In an embodiment, the substrate 10 is, for example, a crucible substrate. The substrate 10 can have, for example, shallow trench isolation (STI). Group 101 is located on substrate 10. The majority of groups 101 may be arranged in a regular or irregular arrangement. In an embodiment, a plurality of groups 101 are adjacent to each other and do not overlap, but the present invention is not limited thereto.

Each group 101 includes at least one word line 40 and at least one virtual word line 60. The word line 40 and the dummy word line 60 are located on the substrate 10 and extend in the first direction D1. The arrangement of the word line 40 and the virtual word line 60 on the substrate 10 is not particularly limited. Any of the word lines 40 may be between the other two word lines 40, between the two virtual word lines 60, or between the other word lines 40 and any of the virtual word lines 60. between. Similarly, any virtual word line 60 can be between two other virtual word lines 60, between two word lines 40, or between another virtual word line 60 and any word. Between the 40 lines. In an embodiment of the invention, at least one side of each virtual word line 60 is adjacent to the word line 40.

The arrangement of the above-described word line 40 and virtual word line 60 on the substrate 10 is, for example, repeated in units of groups 101. In one embodiment, each group 101 includes one word line 40 and two virtual word lines 60. The virtual character line 60 is located on both sides of the word line 40, and the virtual word line 60 in each group 101 is adjacent to the virtual word line 60 in the adjacent group 101, as shown in FIG. 1A. Show. Additionally, the virtual word line 60 in each group 101 may also be adjacent to the word line 40 in the adjacent group 101, as described below with respect to FIG. 1B. However, the present invention is not limited thereto. In other embodiments, each group 101 may also include two or more word lines 40 and virtual word lines 60, respectively. Those having ordinary skill in the art to which the present invention pertains can adjust the number of word lines 40 and virtual word lines 60 within the group as needed.

FIG. 1B is a top view of a memory device 100b according to another embodiment of the invention. The structure of the memory element 100b is, for example, similar to the memory element 100a. The difference between the two is the arrangement of the word line 40 and the virtual word line 60 on the substrate 10.

Referring to FIG. 1B, the memory element 100b includes a substrate 10, a plurality of groups 102, and a plurality of groups 104. Each group 102 and each group 104 includes at least one word line 40 and at least one virtual word line 60, respectively. The number of character lines 40 and virtual word lines 60 in group 102 and group 104 may be the same or different. In an embodiment, group 102 and group 104 are arranged in interaction with each other, but the invention is not limited thereto. In another embodiment, the partial group 102 overlaps with the partial group 104. For example, adjacent group 102 and group 104 include, for example, the same virtual word line 60, but the invention is not limited thereto. Alternatively, adjacent groups 102 and groups 104 may also include the same word line 40.

In one embodiment, each group 102 and each group 104 includes a word line 40 and two virtual word lines 60, respectively, and the virtual word lines 60 are located on opposite sides of the word line 40, respectively. In this embodiment, any group 102 and adjacent group 104 include the same virtual word line 60. However, the invention is not limited thereto. In other embodiments, any group 102 and adjacent groups 104 may also include two or more virtual word lines 60 in common.

Fig. 2 is a schematic cross-sectional view taken along line A-A' of Fig. 1A.

Referring to both FIG. 1A and FIG. 2, in one embodiment, each group 101 includes one word line 40 and two virtual word lines 60. Each word line 40 extends, for example, in a first direction D1. The first direction D1 described above is, for example, the direction of the vertical paper surface in FIG. Each word line 40 is connected in series with a plurality of memory cells 40a. Each memory cell 40a includes a portion of dielectric layer 12, charge storage layer 14, dielectric layer 18a, and control gate 20. Each virtual word line 60 extends, for example, in a first direction D1. Each virtual word line 60 is connected in series with a plurality of virtual memory cells 60a. Each virtual memory cell 60a includes a portion of dielectric layer 12, dummy layer 16, dielectric layer 18b, and dummy control gate 30.

The dielectric layer 12 is on the substrate 10. The material of the dielectric layer 12 includes an oxide, a nitride, an oxynitride, or a combination thereof. The material of the dielectric layer 12 is, for example, ruthenium oxide. The method of forming the dielectric layer 12 is, for example, a chemical vapor deposition method or a thermal oxidation method. In one embodiment, the dielectric layer 12 is, for example, a tunneling dielectric layer that acts as a memory cell.

The charge storage layer 14 is on the dielectric layer 12. The charge storage layer 14 can be a conductor layer or a charge trapping dielectric layer. The material of the charge storage layer 14 includes polycrystalline germanium, doped polycrystalline germanium, cerium oxide, tantalum nitride or a combination thereof. In an embodiment, the charge storage layer 14 is, for example, a floating gate. The dummy layer 16 is on the dielectric layer 12, and the material of the dummy layer 16 is, for example, the same as the charge storage layer 14. In an embodiment of the invention, the virtual layer 16 does not have the function of storing charge. The method of forming the charge storage layer 14 and the dummy layer 16 includes forming a conductor material layer (not shown) on the dielectric layer 12, and then patterning the conductor material layer to form a plurality of charge storage layers 14 and a plurality of dummy layers 16.

It is to be noted that in the above-described process of patterning the conductor material layer, a residue R is likely to be left near the surface of the substrate 10 due to limitations in the etching process. The residue R is randomly distributed between any two of the charge storage layers 14, between the dummy layers 16, or between the charge storage layer 14 and the dummy layer 16, for example. The above phenomenon causes a portion of the charge storage layer 14 to be connected to a portion of the dummy layer 16, such that a subsequent application of a single voltage to the charge storage layer 14 causes the potential of the charge storage layer 14 to decrease.

In addition, a doped region (not shown) may be further included in the substrate 10 on both sides of the charge storage layer 14. The doped region is, for example, a source and a drain of the memory cell.

With continued reference to FIG. 1A, dielectric layers 18a, 18b are respectively located on charge storage layer 14 and dummy layer 16. The material of the dielectric layers 18a, 18b includes hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof. The dielectric layers 18a, 18b can be a single layer or a composite layer. In an embodiment, the dielectric layers 18a, 18b are, for example, a single layer of hafnium oxide layer. In another embodiment, the dielectric layers 18a, 18b are, for example, a composite layer composed of an oxide layer/nitride layer/Oxide (ONO). The method of forming the dielectric layers 18a, 18b is, for example, a chemical vapor deposition method or a thermal oxidation method. In an embodiment of the invention, the dielectric layer 18a is, for example, a gate dielectric layer as a memory cell.

Control gate 20 is located on dielectric layer 18a. The material of the control gate 20 includes polycrystalline germanium, doped polycrystalline germanium, metal germanide or a combination thereof. The control gate 20 extends, for example, in the first direction D1 to be in contact with the charge storage layer 14. The dummy control gate 30 is located on the dielectric layer 18b. The material of the virtual control gate 30 is, for example, the same as the control gate 20. The virtual control gate 30 extends, for example, in a first direction D1 and is parallel to the control gate 20. In an embodiment, at least one side of each virtual control gate 30 is adjacent to the control gate 20.

In the present invention, the above group 101 includes at least one word line 40 and at least one virtual word line 60. In an embodiment, group 101 includes one word line 40 and two virtual word lines 60. The virtual word lines 60 are located on either side of the word line 40, and the virtual word lines 60 in each group 101 are adjacent to the virtual word lines 60 in the adjacent group 101. Additionally, the virtual word line 60 in each group 101 can also be adjacent to the word line 40 in the adjacent group 101. However, the present invention is not limited thereto. In other embodiments, each group 101 may also include two or more word lines 40 and virtual word lines 60, respectively. Those having ordinary skill in the art to which the present invention pertains can adjust the number of word lines 40 and virtual word lines 60 within the group as needed.

Moreover, in one embodiment, the word line 40 and the virtual word line 60 can be electrically connected through a wire.

It is worth noting that when the memory element is subsequently operated, a voltage is applied to the word line 40 and the virtual word line 60 in the same group 101. In one embodiment, the same voltage is applied to word line 40 and virtual word line 60 in the same group 101 such that both have the same potential. The memory element 100a will be exemplified below as an exemplary embodiment.

FIG. 3 is a schematic diagram of an operational flow of the memory component 100a according to an embodiment of the invention.

Referring to FIG. 3, the method of operating the memory element 100a includes the following steps. In step 302, at least one group 101 is selected and the selected group 101 is operated. The above operations include stylization, reading or erasing. In an embodiment, a single group 101 or a plurality of groups 101 may be selected to perform the above operations simultaneously. Next, in step 304, a first bias voltage is applied to the word line 40 in the selected group 101 such that the word line 40 has a potential V1. Then, in step 306, a second bias voltage is applied to the virtual word line 60 in the selected group 101 such that the virtual word line 60 has a potential V2. The first bias and the second bias may include a high voltage or a low voltage. The first bias voltage and the second bias voltage may be equal or unequal. In one embodiment, the potential V1 of the word line 40 is the same as the potential V2 of the virtual word line 60. However, the invention is not limited to the above method. In another embodiment, when the first bias voltage is applied to the word line 40 in the group 101, the second bias voltage is simultaneously applied to the dummy word line 60 in the group 101, the second bias voltage and the second bias voltage A bias voltage is the same so that word line 40 and virtual word line 60 have the same potential.

When the word line 40 in the group 101 is subjected to a programmatic operation, the word line 40 and the virtual word line are caused by simultaneously applying the same stylized bias to the virtual word line 60 in the group 101. The potentials of 60 are the same, so even if the charge storage layer 14 under the word line 40 is connected to the adjacent dummy layer 16 due to the residue R (as shown in FIG. 2), the electrons in the charge storage layer 14 are not The residue R migrates to the adjacent virtual layer 16. In this way, the problem of charge loss or charge increase of the memory element 100a can be avoided.

In addition, since the word line is simultaneously biased with the adjacent dummy word line, the inter poly dielectric layer (IPD) capacitance and the overall capacitance of the word line are changed. Even if the charge storage layer 14 under the word line is connected to the adjacent dummy layer 16 due to the residue R, the potential of the word line does not decrease as a result. As a result, the gate coupling ratio of the above word line will be improved compared to the conventional word line. Therefore, the above operation method can improve the problem of slow stylization and mutual interference between word lines, thereby greatly improving the in-situ error rate of the memory element 100a.

In summary, the method for operating a memory element provided by the present invention forms a group including at least one word line and at least one virtual word line in a memory element, and the word line in the group and The dummy word lines are respectively biased. In this way, when the above bias voltages are the same, the word line and the virtual word line in the group have the same potential. Therefore, even if the word lines or dummy word lines in the memory element are connected to each other due to limitations in the etching process, the final potential of the word lines does not decrease due to the potential difference between them, thereby improving the slow stylization. The problem of charge loss, charge increase, and mutual interference between word lines can further increase the gate coupling ratio of the memory element and improve the in-situ error rate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10: Substrate 12, 18a, 18b: Dielectric layer 14: Charge storage layer 16: Virtual layer 20: Control gate 30: Virtual control gate 40: Word line 60: Virtual character line 40a: Memory cell 60a: Virtual memory cell 100a, 100b: memory elements 101, 102, 104: group 302, 304, 306: step A-A': line D1: direction R: residue V1, V2: potential

FIG. 1A is a top plan view of a memory device according to an embodiment of the invention. FIG. 1B is a top plan view of a memory device according to another embodiment of the invention. Fig. 2 is a schematic cross-sectional view taken along line A-A' of Fig. 1A. FIG. 3 is a schematic diagram of an operation flow of a memory element according to an embodiment of the invention.

10: Substrate 40: Word line 60: Virtual character line 100a: Memory element 101: Group D1: Direction A-A': Line

Claims (10)

A method of operating a memory element, the memory element comprising a substrate, a plurality of word lines, and a plurality of dummy word lines, the word lines and the virtual word lines are located on the substrate, each virtual word line At least one side of the word line is adjacent to the word line, wherein at least one word line and at least one virtual word line form a group, and at least one of the virtual word lines is located between the word lines, The method includes: selecting at least one group and performing an operation on the group; applying a first bias to the word line in the group; and applying a second bias to the group The virtual character line in the group. The method of operating a memory device according to claim 1, wherein when the first bias is applied to the word line in the group, the second bias is simultaneously applied to the group The virtual character line in . The method of operating a memory device according to claim 1, wherein the word line in the group is the same as the potential of the virtual word line. The method for operating a memory element according to claim 1, wherein each group includes two of said virtual word lines and one of said word lines, said virtual word lines being respectively located in said characters On both sides of the line. A memory component comprising: a substrate; a plurality of word lines on the substrate; a plurality of dummy word lines on the substrate, at least one side of each virtual word line is adjacent to the word line, and at least one of the virtual word lines is located between the word lines, wherein at least A word line and at least one virtual word line form a group, and the potential of the word line and the virtual word line in the group are the same. The memory element of claim 5, wherein each group comprises two of said virtual word lines and one of said word lines, said virtual word lines being respectively located in said word line side. The memory element of claim 5, wherein the adjacent two groups comprise the same virtual word line. The memory element of claim 5, wherein a portion of the word lines are in contact with a portion of the virtual word lines. A memory component comprising: a substrate; and a plurality of word line groups on the substrate, each word line group comprising: at least one word line; and at least one virtual word line adjacent to the The word line, wherein the virtual word line is the same as the word line, and at least one of the virtual word lines is between the word lines. The memory element of claim 9, wherein a portion of the word line in the group of word lines is in contact with a portion of the virtual word line.