TWI544462B - Display panel and driving method thereof - Google Patents

Description

Display panel and driving method thereof

The present invention relates to a display panel and a driving method thereof, and more particularly to a display panel usable for partial updating of a display screen and a driving method thereof.

With the evolution of technology, various electronic devices have also been introduced, and display panels are often used to provide interactive interfaces for users. Therefore, the display panel has become a basic device for today's electronic devices. Conventional display panels include various types of thin film transistor liquid crystal displays (TFT-LCDs) or displays made of organic light-emitting diodes (OLEDs). Display.

However, the conventional display panel uses the gate and source scan line structure. Under such a scanning structure, the driving method must reset the display unit of the entire display screen every complete scanning period, and the display screen must also be updated in a certain order. Therefore, the conventional display panel and the driving method thereof are less flexible, and the partial display unit cannot be updated corresponding to the actual screen. Cause unnecessary energy consumption.

In view of the above, the present invention is directed to a display panel and a driving method thereof for solving the problem of energy consumption caused by the fact that the conventional display panel and its driving method cannot partially update the display screen.

The invention discloses a display panel comprising N columns of display areas, N reset lines and M data lines. Each column display area includes a plurality of sub-pixels and M control chips. The plurality of sub-pixels are disposed in the display area. The M control chips are disposed in the display area, and each control chip is electrically coupled to at least a portion of the sub-pixels in the corresponding display area. The N reset lines are electrically coupled to the M control wafers located in one of the N columns of display regions, respectively. The M data lines are electrically coupled to the M control wafers in each column display area. Where M and N are positive integers.

The invention discloses a display panel driving method, which is suitable for a display panel. The display panel includes N columns of display areas, N reset lines, and M data lines, where M and N are positive integers. Each column display area includes a plurality of sub-pixels and M control chips, and the plurality of sub-pixels and the M control chips are disposed in the display area. Each control chip is electrically coupled to at least a portion of all of the plurality of sub-pixels in the display area. The N reset lines are respectively electrically coupled to the The N columns display the M control wafers in one of the regions. The M data lines are electrically coupled to the M control wafers in each column display area. The display panel driving method includes: when a picture update signal is input to one of the N reset lines, the M control chips in the corresponding display area respectively determine whether a data signal is input to the corresponding data line. And the sub-pixels electrically coupled to the M control chips are selectively turned on or off (ie, updated or not updated). When the plurality of control chips in the display area respectively receive the data signals, the corresponding control chips sequentially turn on the sub-pixels of the electrical coupling control chip according to the timing of the received data signals.

In summary, the present invention discloses a display panel and a driving method thereof, wherein the display panel has a plurality of display areas, and each display area is respectively provided with at least one control wafer. Each control chip is electrically coupled to at least a portion of the sub-pixels of the corresponding display area, and electrically coupled to the reset line and the data line, respectively. The display panel and the driving method thereof of the present invention can independently drive the control wafers in each display area by inputting a picture reset signal corresponding to the reset line corresponding to each display area, so that the control chip can be based on the clock signal and the corresponding The data signal updates the sub-pixels that are electrically coupled, thereby achieving a partial update display and energy saving.

The above description of the present invention and the following description of the embodiments are intended to illustrate and clarify the spirit and principles of the present invention and to provide Ming's patent application scope is further explained.

1‧‧‧ display panel

2‧‧‧Display screen

10‧‧‧Substrate

BK‧‧‧ interrupt signal

C _1,1 ~C _3,12 ‧‧‧Control chip

CLK‧‧‧ clock signal

D ₁ ~D ₁₂ ‧‧‧Information line

Data1‧‧‧First Information Signal

Data2‧‧‧Second data signal

Data3‧‧‧ Third Information Signal

L ₁ ~L ₄ ‧‧‧ physical circuit

O ₁ ‧‧‧ objects

P ₁ ~P ₄ ‧‧‧Sub-picture group

P ₁₁ ~P ₄₃ ‧‧‧Subpixels

R ₁ , R ₂ , R ₃ ‧‧‧reset line

S901~S903‧‧‧Step procedure

T ₁ ~T ₁₄ ‧‧‧ time

Z ₁ ~Z ₃ , Z _1,1 ~Z _24,4 ‧‧‧Display area

1 is a circuit diagram of a display panel in an embodiment of the present invention.

2 is a circuit diagram showing a coupling relationship between a control wafer and a sub-pixel in an embodiment of the present invention.

Figure 3 is a timing diagram of a portion of signals in an embodiment of the present invention.

Figure 4 is a schematic diagram showing the display panel for partial updating in an embodiment of the present invention.

Figure 5 is a timing diagram of signals of a plurality of display areas in an embodiment of the present invention.

Figure 6 is a schematic diagram showing the partitioning of the display area of the display panel in an embodiment of the present invention.

FIG. 7 is a circuit diagram showing a coupling relationship between a control wafer and a sub-pixel in another embodiment of the present invention.

Figure 8 is a side elevational view of the S direction in Figure 7.

Figure 9 is a flow chart showing a method of driving a display panel in an embodiment of the present invention.

The detailed features of the present invention are described below in the embodiments, which are sufficient to enable anyone skilled in the art to understand the technical contents of the present invention. The related objects and advantages of the present invention will be readily understood by those skilled in the art in light of this disclosure. The following examples are intended to further illustrate the invention, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a display panel according to an embodiment of the present invention. As shown in FIG. 1, the display panel 1 includes three columns of display areas Z ₁ to Z ₃ , three reset lines R ₁ to R ₃ , twelve data lines D ₁ to D ₁₂ and a plurality of control wafers C _1,1 ~C _3,12 . The first code subscript number of the control chip C _1,1 ~ C _3,12 corresponds to the subscript number of the electrically coupled reset lines R ₁ -R ₃ , and the control chip C _1,1 ~ The second code subscript number of C _3,12 corresponds to the subscript number of the electrically coupled data lines D ₁ -D ₁₂ . For example, the control wafer C _{1, 2} represents a control wafer electrically coupled to the reset line R ₁ and the data line D ₂ . The control chip C _1,1 -C _3,12 may be, for example, a micro integrated circuit (micro IC), but is not limited thereto. For the sake of simplicity and ease of illustration, the sub-pixels electrically coupled to the control chips C _1,1 to C _3,12 are not shown in FIG. 1 and are shown in the subsequent figures. In the meantime, the present invention does not limit the size of the plurality of control wafers, and those skilled in the art can design according to the applicable resolution of the display panel 1 and the number of display areas to be divided. Reasonably control the size of the wafer.

Continuing the foregoing, and more specifically, the control wafers C _1,1 to C _{1,12 are} all disposed in the display area Z ₁ . Each control chip C _1,1 ~ C _1,12 located in the same display area Z ₁ is electrically coupled to the reset line R ₁ , and the control chips C _1,1 ~ C _1,12 are electrically coupled to the data respectively. Line D ₁ ~ D ₁₂ . In addition, each control chip C _2,1 -C _2,12 located in the same display area Z2 is electrically coupled to the reset line R ₂ , and the control chips C _2,1 -C _2,12 are electrically coupled respectively. Data line D ₁ ~ D ₁₂ . Each of the control chips C _3,1 - C _3,12 in the same display area Z3 is electrically coupled to the reset line R3, and the control chips C _3,1 - C _3,12 are electrically coupled to the data lines respectively. D ₁ ~ D ₁₂ .

In other words, the reset line R ₁ ~ R ₃ are electrically coupled to the control chip is located in the same region C _{1,1 ~ C 1,12, C 2,1 ~} C 2,12, C 3,1 ~ C 3 _{, 12} . The data lines D ₁ -D ₁₂ are electrically coupled to _one of the control wafers C _1,1 to C _1,12 in the display area Z ₁ and the control wafers C _2,1 to C ₂ in the display area Z ₂ . One of ₁₂ , and one of the control wafers C _3,1 to C _3,12 in the display area Z ₃ . For example, the reset line R _{1 is} electrically coupled to the control wafers C _1,1 to C _1,12 , and the data line D1 is electrically coupled to the control wafers C _1,1 , C _2,1 , C _3,1 .

In practice, the display panel 1 can be driven by a timing controller (not shown). The timing controller is electrically coupled to each of the reset lines and each of the data lines. The timing controller is configured to generate a picture update signal, at least one data signal, and an interrupt signal to drive each control chip to operate. Briefly, the picture update signal is used to drive each control chip to update its electrically coupled sub-pixels; and under the driving of the picture update signal, each control chip is based on The data packet in the received data signal updates the sub-pixels that are electrically coupled; and the control chip selectively updates the electrical coupling according to the indication of the interrupt signal, driven by the picture update signal. Sub-pixels for finer sub-pixel updates. The following will be accompanied by a signal timing diagram to show how the display panel works according to the above signals, and will not be described here.

Actually, the number of control chips included in the display panel 1 or the respective signal traces is not limited to the embodiment corresponding to FIG. 1 . The display panel 1 may include N columns of display areas, N reset lines, and M data lines, and each column display area includes a plurality of sub-pixels and M control chips. The plurality of sub-pixels and the M control chips are disposed in the associated display area. Each control chip is electrically coupled to at least a portion of all sub-pixels (not shown) in the corresponding display area. The N reset lines are electrically coupled to the M control wafers located in one of the N columns of display regions, respectively. The M data lines are electrically coupled to the M control wafers in each column display area. Wherein M and N are positive integers. For the sake of brevity, the following description will be made with the embodiment corresponding to FIG. 1.

Referring to FIG. 1 and FIG. 2 together, FIG. 2 is a circuit diagram showing a coupling relationship between a control chip and a sub-pixel in an embodiment of the present invention. Figure 2 further illustrates sub-pixel groups P ₁ , P ₂ electrically coupled to any of the control wafers (e.g., control wafer C _1,1 ). The sub-pixel group P ₁ includes sub-pixels P ₁₁ , P ₁₂ , and P ₁₃ , and the sub-pixel group P ₂ includes sub-pixels P ₂₁ , P ₂₂ , and P ₂₃ . As shown in the figure, the sub-pixel groups P ₁ and P ₂ are at least a part of a plurality of sub-pixels in two adjacent columns, and the sub-pixel groups P ₁ and P ₂ are respectively located on the opposite sides of the control wafer C _1,1 . side. The sub-pixels P ₁₁ , P ₁₂ , and P ₁₃ may be symmetric or asymmetric with respect to the sub-pixels P ₂₁ , P ₂₂ , and P ₂₃ . The number of sub-pixels included in the sub-picture groups P ₁ and P ₂ is generally applicable to those skilled in the art and can be freely designed after reading the present specification, and is not limited herein.

The above is a description of the structure of the display panel 1. The following is a description of the operation of the display panel 1 based on the above-described structural description.

Please refer to FIG. 1 and FIG. 3 simultaneously to cooperate with the operation of the display panel 1. FIG. 3 is a timing diagram of partial signals in an embodiment of the present invention. As shown, in FIG. 3, there is shown at a time point the time point T _{T. 1} to ₇ of the screen update the RST signal, the CLK clock signal, the first data signals Data1, the second data signals Data2, Data3 third data signals With interrupt signal BK. The time points T ₁ ~T ₇ in the drawings are freely defined by those having ordinary knowledge in the technical field. The interval length between the time points T ₁ to T ₇ is not limited here. .

When one of the screen update signal input to the reset line RST R ₁ ~ R ₃ wherein, the display region corresponding to Z _1, Z _2, Z ₃ of the control chip C _1,1 ~ C _1,12, C _{2 , 1} ~ C ₂ , ₁₂ , C ₃ , ₁ ~ C ₃ , ₁₂ according to whether there is a data signal input to its corresponding data line D ₁ ~ D ₁₂ according to the control chip C _1,1 ~ C _{1, 12} , C _2,1 ~C _2,12 , C _3,1 ~C _3,12 selectively turn on or off (ie update or not update) respectively to electrically control the control chip C _1,1 ~C _{1, 12} , C _2,1 ~ C _2,12 , C _3,1 ~ C _3,12 of the plurality of sub-pixels.

Z ₁ as an example to show the area, when the screen update signal RST is inputted to the reset line R _1, the display control area Z ₁ C _1,1 ~ C _1,12 wafer according to whether there are input data signals thereto Corresponding data lines D ₁ ~ D ₁₂ , according to which the control wafers C _1,1 ~ C _1,12 are selectively turned on or off (ie, updated or not updated) electrically coupled to the control chip C _1,1 ~C _1,12 sub-pixels. At the same time, the reset lines R ₂ and R ₃ do not receive the instruction corresponding to the picture update signal RST, so the control chips C _2,1 ~C _2,12 , C _3,1 -C in the display areas Z ₂ and Z ₃ are displayed. _3,12 does not update the corresponding sub-pixel according to the data signal.

Also as an example to show the area Z _1, the control chip C _1,1 ~ C _1,12 addition to receiving the display update signal RST, the clock signal but also receives CLK. When the picture update signal RST is at a high level, the clock signal is at a low logic level; when the picture update signal RST is at a low level, the clock signal CLK has a fixed pulse width to drive the electrical coupling control chip C _1,1 The sub-pixels of ~C _1,12 are such that the sub-pixels are updated according to the data signals received by the control chips C _1,1 ~ C _1,12 . In other words, the control chips C _1,1 to C _3,12 receiving the high level picture update signal RST are not activated according to the clock signal CLK or the data signal. Conversely, the control chips C _1,1 to C _3,12 receiving the low level picture update signal RST are activated according to the clock signal or the data signal. The correspondence between the level of the picture update signal RST and the logic level of the clock signal CLK is freely designed by those having ordinary knowledge in the technical field, and is not limited herein. .

In the foregoing, when the low level picture update signal RST is received, the control chips C _1,1 C C _{3 , 12} can directly update the electrically connected sub pixels according to the content of the data signal. In practice, the control chip C _1,1 ~ C _3,12 can further selectively update the sub-pixels that are electrically coupled according to whether it is determined that the data signal is received, if the latter operation mode is used. In addition to selecting a pixel pause update that receives the same picture update signal RST, the specific pixel in the pixel receiving the same update signal RST can be operated to skip the current update period by not transmitting a new data signal. More specifically, in the case where the low level picture update signal RST is received, and the plurality of control chips C _1,1 to C _3,12 in the display areas Z ₁ to Z ₃ are respectively determined to be received When the data signal is received, the corresponding control chips C _1,1 ~ C _3,12 sequentially update the sub-pictures of the electrically coupled control chips C _1,1 ~C _3,12 according to the timing of the received data signals. Prime. Conversely, in the case where the low level picture update signal RST is received, and the plurality of control chips C _1,1 to C _3,12 in the display areas Z ₁ to Z ₃ respectively determine that the data signal is not received, The corresponding control chips C _1,1 ~ C _3,12 respectively do not update their corresponding sub-pixels, thereby saving power consumption.

In the following, the first to third figures are taken as an example to illustrate that the control wafers C _1,1 to C _{3,12 are} actuated according to the respective signals. As described above, in the display area Z ₁ , the data line D _{1 is} electrically coupled to the control chip C _1,1 , and the data line D _{2 is} electrically coupled to the control chip C _1,2 and the data line D _{3 is} electrically coupled. Control wafer C _1,3 .

Between the time point T ₁ and the time point T ₂ , the picture update signal RST is a high clamp, at which time the clock signal CLK is a low logic level and the first data signal Data1, the second data signal Data2 and the third data signal Data3 does not carry a data packet.

In the time zone from the time point T ₂ to the time point T ₃ , the picture update signal RST is a low clamp, and the clock signal CLK has a fixed pulse width, and the first data signal Data1 contains a data in the interval. Packet. Therefore in controlling driving of wafer C _1,1 The clock signal CLK and the first data Data1 signal coupled to the control sub-pixel C _1,1 of the wafer, to update the plurality of sub-pixel.

In the second diagram, the control chip C _1,1 first updates the sub-pixel group P ₁ according to the clock signal CLK and the first data signal Data1, and controls the chip C _1,1 according to the clock signal CLK and The first data signal Data1 updates the sub-pixel group P ₂ . More specifically, the control chip C _1,1 updates the sub-pixel P ₁₁ according to the corresponding data packet segment in the first cycle of the clock signal CLK; and controls the chip C1 in the second cycle of the clock signal CLK. 1 updates the sub-pixel P ₁₂ according to the corresponding data packet segment; and in the third cycle of the clock signal CLK, the control chip C _1,1 updates the sub-pixel P ₁₃ according to the corresponding data packet segment. In the fourth to sixth periods of the clock signal CLK, the control chip C _1,1 updates the sub-pixel group P2 according to the clock signal CLK and the first data signal Data1 as described above. Let me repeat.

In the time zone from the time point T ₃ to the time point T ₄ , the picture update signal RST is a high clamp, and the clock signal CLK is a low logic level and the first data signal Data1, the second data signal Data2 and the first The three data signals Data3 do not carry data packets, so the control chips C _1,1 ~C _1,3 in this time zone will not update the multiple sub-pixels that are electrically coupled.

In the time zone from the time point T ₄ to the time point T ₇ , the picture update signal RST is a low clamp, and the clock signal CLK has a fixed pulse width. Different from the foregoing, in the time zone of the time point T ₄ and the time point T ₇ , the control chip C _1,3 receives an interrupt signal BK, which is a pulse wave signal, and its pulse wave The width continues from time point T ₅ to T ₆ .

Continuing the foregoing, corresponding to the pulse wave of the interrupt signal BK, the third data signal Data3 includes two data packets in the time zone from the time point T ₄ to the time point T ₇ , but the third data signal Data3 is at the time point T _{5 .} No data packet is included between the time point T ₆ and the time point T ₆ . Specifically, one of the data packets is located between time points T ₄ and T ₅ , and the other data packet is located at time points T ₆ , T ₇ . C ₃ and the control wafer according to electrically drive the clock signal CLK, and a third data Data3 coupled to the control signal sub-pixel C _1,3 of the wafer, to update or not to update the sub-pixels are electrically coupled.

From another point of view, when the interrupt signal BK is low, the control chip C _1,3 updates its electrically coupled sub-pixel according to the clock signal CLK and the third data signal Data3; and when the interrupt signal is interrupted When BK is high, the control chip C _{1, 3} does not update its electrically coupled sub-pixel according to the clock signal CLK and the third data signal Data3. Referring to each time point to explain in more detail, between time points T ₄ and T ₅ , the interrupt signal BK is at a low level, and the third data signal Data3 includes a data packet, and the control chip C _{1, 3} is updated as described above. The sub-pixels are electrically coupled; and between time points T ₅ and T ₆ , since the interrupt signal BK is a high clamp, the third data signal Data3 does not include a data packet, and the control chip C _{1, 3 is} not updated. The sub-pixels are electrically coupled; and between time points T ₆ and T ₇ , the interrupt signal BK is at a low level, and the third data signal Data3 includes a data packet, and the control chip C _{1, 3 is} as described above. Update the sub-pixels that are electrically coupled.

That is, the plurality of sub-pixels electrically coupled to the control chips C _1,1 to C _3,12 respectively correspond to different time intervals, or the plurality of sub-pixels respectively correspond to different clock signals CLK. When the control chip C _1,1 ~C _3,12 receives the pulse wave of the interrupt signal BK, the control chip C _1,1 ~C _3,12 does not update its position in the pulse wave interval of the interrupt signal BK. Electrically coupled sub-pixels. It is understood by those skilled in the art that the interrupt signal BK can be used to instruct any of the control chips C _1,1 - C _3,12 to selectively update any of the sub-picture groups as described above. A sub-pixel, which can achieve the effect of partial update. Therefore, in an embodiment, when the number of pins of the control chip C _1,1 ~ C _3,12 does not match the number of sub-pixels of the display panel 1, the target signal can be controlled by the interrupt signal BK. The sub-pixels are electrically connected to the control chip C _1,1 ~ C _{3,12 to} selectively update the sub-pixels electrically connected to the target pin according to the data signal.

Please refer to FIG. 4 to explain how to perform partial update with the display panel 1. FIG. 4 is a schematic diagram of the display panel for partial updating in an embodiment of the present invention. FIG 4 shows a display panel in a display screen 2 of 1, 2 and the display screen corresponding to the structure of the display panel 1 of FIG. 1, also has a display area _{Z 1, Z 2, Z 3} . There is an object O ₁ in the display screen 2, and O ₁ moves from the first position to the second position along the dotted arrow as shown in the figure as the content of the display screen 2 changes. The first position and the second position and the moving path of the object O ₁ are all located in the display area Z ₁ .

In other words, during which time, a display screen 2 is only a portion corresponding to the display area Z ₁ is varied, while the display region Z _2, Z ₃ may be regarded as stationary portion unchanged. Thus, according to the content of the previous discussion of FIG. 3, you can enter the low level of the reset signal RST corresponding to the display area into the reset line Z ₁ R _1, and inputs the high-level reset signal RST corresponding to the display into region Z _2, Z ₃ reset line R _2, R _3, Z to update the contents of the display region ₁ alone, without conventional like regular scans such as an entire display screen, thereby saving unnecessary power consumption.

Next, please refer to FIG. 1 and FIG. 5 together. FIG. 5 is a schematic diagram of signal timing of a plurality of display areas in an embodiment of the present invention. Figure 5 shows the reset signals RST1, RST2, RST3 and the first data signal Data1. In this embodiment, the reset signals RST1, RST2, and RST3 are input to the reset lines R ₁ , R ₂ , and R ₃ , respectively, and correspond to the control wafers C _1,1 , C _2,1 , C _{3,1 , respectively.} . The first data signal Data1 continues to be updated over time, but the corresponding control chips C _1,1 , C _2,1 , C _3,1 will The clock signal CLK and the first data signal Data1 drive electrically couple the sub-pixels of the control chip C _1,1 , C _2,1 , C _3,1 to update the sub-pixels.

In the fifth figure, between time point T ₈ and time point T ₉ , the reset signal RST1 is at a low level, and the reset signals RST2 and RST3 are all at a high level. Controlling driving of wafer C _1,1 The clock signal CLK and the first data Data1 signal coupled to the control sub-pixel C _1,1 of the wafer, to update electrically coupled to the control sub-pixel C _1,1 of the wafer. Controlling wafer C _2,1, C _3,1 when not in accordance with a first clock signal CLK, and data signals Data1 control driver electrically coupled to the wafer sub-pixel C _2,1, C _3,1 of.

Between the time point T ₉ and the time point T ₁₀ , the reset signal RST2 is at a low level, and the reset signals RST1 and RST3 are all at a high level. Wafer according to the control clock signal CLK C _2,1, and the first data signals Data1 driver electrically coupled to the control sub-pixel C _2,1 of the wafer, to update electrically coupled to the control sub-pixel C _2,1 of the wafer. Controlling wafer C _1,1, C _3,1 when not in accordance with a first clock signal CLK, and data signals Data1 control driver electrically coupled to the wafer C _1,1, C _3,1 of the sub-pixels.

Between the time point T ₁₀ and the time point T ₁₁ , the reset signal RST3 is at a low level, and the reset signals RST1 and RST2 are all at a high level. Controlling driving of wafer C _3,1 The clock signal CLK and the first data Data1 signal coupled to the control sub-pixel C _3,1 of the wafer, to update electrically coupled to the control sub-pixel C _3,1 of the wafer. Controlling wafer C _1,1, C _2,1 when not in accordance with a first clock signal CLK, and data signals Data1 control driver electrically coupled to the wafer C _1,1, C _2,1 subpixels.

Therefore, between time points T ₈ and T ₁₁ , the display panel 1 sequentially updates the electrically coupled control chips C _1,1 , C _2,1 , C _3,1 according to the reset signals RST1, RST2, and RST3. Sub-pixel. In other words, corresponding to the display areas Z ₁ , Z ₂ , and Z ₃ , the display panel 1 sequentially updates the display areas Z ₁ , Z ₂ , and Z ₃ according to the reset signals RST1, RST2, and RST3.

The interrupt signal BK is at a high level between the time point T ₁₁ and the time point T ₁₂ , and the reset signals RST1 , RST2 , RST3 and the clock signal CLK and the first data signal Data1 correspond to a low level. The control chips C _1,1 , C _2,1 , C _3,1 are not electrically coupled to the control chip C _1,1 , C _2,1 , C _3,1 according to the clock signal CLK and the first data signal Data1. Sub-pixels. In fact, the control chips C _1,1 , C _2,1 , C _3,1 can selectively update the corresponding sub-pixels according to the level of the different interrupt signals BK, which is detailed in the technical field. It can be freely designed after reading this manual, and will not be repeated here.

Between the time point T ₁₂ and the time point T ₁₃ , the reset signal RST3 is at a high level, and the reset signals RST1 and RST2 are all at a low level. Control chip C _1,1, C _2,1 drive signal according to the clock signal CLK and the first data Data1 is electrically coupled to the control chip C _1,1, C _2,1 of the sub-pixel to update electrically coupled to the control Subpixels of wafers C _1,1 , C _2,1 . _3,1 C while the wafer is not controlled in accordance with a first clock signal CLK, and data signals Data1 control driver electrically coupled to the sub-pixel C _3,1 of the wafer.

Between time point T ₁₃ and time point T ₁₄ , the reset signals RST1, RST2, and RST3 are all at a high level. The control chips C _1,1 , C _2,1 , C _3,1 are not electrically coupled to the control chip C _1,1 , C _2,1 , C _3,1 according to the clock signal CLK and the first data signal Data1. Sub-pixels.

According to the above operation, it is obvious that in such an embodiment, different reset signals RST1, RST2, and RST3 can be input to the reset lines R ₁ , R ₂ , and R ₃ to be individually updated, sequentially updated, or updated synchronously. Different sub-pixels in different display areas. Therefore, when the entire display screen 2 is changed, the entire display screen 2 can be updated by scanning; and when only the partial area of the display screen 2 changes, the corresponding control chip can be driven by the reset signal RST. Update the corresponding local area.

In addition, in one or more embodiments of the present invention, the display panel 1 disclosed in the present invention can effectively reduce the number of signal traces (reset lines, signal lines). Hereinafter, the display panel 1 having a resolution of 240 × 432 will be described as an example. Please refer to FIG. 6 (not to scale). FIG. 6 is a schematic diagram showing the partitioning of the display area of the display panel in an embodiment of the present invention. In the embodiment corresponding to FIG. 6, the display panel 1 is divided into 4×24 display areas Z _1,1 to Z _24,4 , wherein each column of the display panel 1 has 4 display areas, and the display panel 1 Each row has 24 display areas Z _1,1 ~Z _24,4 . Wherein the subscript a first display code representative of Z _1,1 ~ Z _24,4 partition lines located in the display panel 1 of the first columns, and the subscript a second code to represent a display-based partition Z _1,1 ~ Z _24,4 It is located on the first line of the display panel 1. Such a partitioning manner will cause the display panel 1 to have a smaller number of traces.

In detail, each column of such a display panel 1 has 240 pixels, and each of the rows has 432 pixels. When the display panel 1 is divided into 4×24 display areas Z _1,1 to Z _24,4 as described above, each display area Z _1,1 ~Z _24,4 has 1080 (240÷4×432÷24) = 60 × 18) pixels, that is, each display area has 3240 (60 × 3 × 18 = 180 × 18) sub-pixels. Since each control wafer can be used to control a plurality of sub-pixels of two adjacent rows as described above, at least nine (18 ÷ 2) control wafers are required for each display area to control sub-pixels in the corresponding display area, and At this point each control chip can be used to control a total of 360 (180 x 2) sub-pixels in two columns.

Continuing the aforementioned, in which each of the display areas of the same column The control chips are electrically coupled to different data lines, and the display areas of the same column share the same reset line. Therefore, such a display panel 1 requires a total of 60 traces of 36 (9 × 4) data lines and 24 reset lines. Similarly, when the display panel 1 is divided into 4×12 display areas, 72 data lines and 12 reset lines are required to have 84 lines; and the display panel 1 is divided into 4×48 display areas. You will need 18 data lines and 48 reset lines for a total of 66 lines. Those skilled in the art, after reading this specification in detail, can classify the number of data traces required for other situations under different resolutions or different control wafer numbers according to the contents of the specification, and perform partition wiring according to the requirements.

In addition, when the display panel 1 has the display partition as shown in FIG. 6, a more detailed partial picture update operation can be performed accordingly. For example, when only the portion corresponding to the display areas Z ₂ , ₂ , Z ₂ , ₃ , Z ₂₄ , ₃ is changed in the display screen, the display panel 1 can maintain the display content of the remaining display areas, and is separately updated and displayed according to the data signal. Area Z _2,2 , Z _2,3 , Z _24,3 . In an embodiment, the original update frequency of the reset signal of the display area Z _1,1 ~Z _24,4 is 60 Hz (Hertz, Hz), and only the display area Z _2,2 , Z _{2,3 is} displayed in the display screen. _When the content of Z ₂₄ , 3 is changed, the display area Z ₂ can be separately updated by increasing the update frequency of the reset signal corresponding to the display areas Z ₂ , ₂ , Z ₂ , ₃ , Z ₂₄ , _{3, 2} , Z ₂ , ₃ , Z ₂₄ , ₃ display content. Thereby, it is possible to locally update the portion of the display screen that has changed a lot, thereby achieving the purpose of saving energy.

As disclosed above, disclosed in one or more embodiments of the present invention The display panel can thus effectively reduce the complexity of hardware implementation while achieving local update efficiency. According to this example, the relative knowledge of the number of display areas and the number of signal traces in a state of different resolution can be reasonably derived by a person skilled in the art, and is not limited herein.

According to the above, the display panel 1 disclosed in one or more embodiments of the present invention can input the picture update signal RST to the reset line R ₁ by using the gate or source scan line to update the entire display screen. And R ₂ , R ₃ , so that the control wafers C _1,1 C C _{3 , 12} in the corresponding display areas Z ₁ to Z ₃ are activated according to the clock signal CLK and the corresponding data signal, thereby updating the display area Z ₁ ~ At least one of Z ₃ , thereby achieving the effect of local updating. Moreover, by providing a plurality of control wafers C _1,1 to C _3,12 in the same display area Z ₁ to Z ₃ , the display panel 1 can be operated according to a lower scanning frequency than before, thereby reducing energy consumption. It is also possible to control the difficulty or complexity of the wafers C _1,1 ~ C _3,12 and associated signal lines.

In addition to the coupling relationship as disclosed in FIG. 2, the control wafers C _1,1 to C _3,12 have other coupling relationships with their corresponding sub-pixels. Referring to FIGS. 7 and 8, FIG. 7 is a circuit diagram showing a coupling relationship between a control wafer and a sub-pixel in another embodiment of the present invention, and FIG. 8 is a side view showing the S direction in FIG. Please refer to FIG. 7 first, and FIG. 7 is an example of controlling the wafer C _1,1 . In the embodiment corresponding to FIG. 7, the opposite sides of the control chip C _1,1 are electrically coupled to the two sub-pixel groups P ₁ , P ₃ and the other two sub-pixel groups P ₂ , P _{4 , respectively} . In more detail, one side of the control wafer C _1,1 is electrically coupled to the sub-pixel groups P ₁ , P ₃ , and the opposite side of the control chip C _1,1 is electrically coupled to the sub-pixel group P. ₂ , P ₄ . The sub-pixel groups P ₁ and P ₃ belong to different columns, and the sub-pixel groups P ₂ and P ₄ belong to different columns. In practice, the sub-pixels P ₁₁ -P ₄₃ in the sub-picture groups P ₁ -P ₄ may be aligned or staggered, and are not limited herein.

Please refer to Figure 8 next. In practice, the control wafers C _1,1 to C _3,12 and the respective sub-pixels described above may be disposed on the substrate 10. In order to avoid signal interference, the control chip C _1,1 can be electrically coupled to the sub-pixel groups P ₁ and P _{2 on the} surface of the substrate 10 by the physical lines L ₁ and L ₂ , respectively, to control the wafer C _1,1 and The other surface of the substrate 10 is electrically coupled to the sub-pixel groups P ₃ and P ₄ by physical lines L ₃ and L ₄ , respectively. The substrate 10 can be, for example, a glass substrate or a plastic substrate, and can be transparent or opaque; and the physical lines L ₁ -L ₄ can be, for example, conductive lines formed on the substrate 10 by various processes, but None of them is limited to this.

By the connection method as shown in Figs. 7, 8, in addition to reducing the number of control wafers, since the control wafer is connected with more sub-pixels, the display panel 1 can more freely update the partial display screen. In addition, such a structure also reduces the number of signal traces. The actual operation is freely designed by those having ordinary knowledge in the technical field, and will not be described here.

According to the above, the present invention also provides a driving method of a display panel. Please refer to FIG. 9. FIG. 9 is a schematic flow chart of a method for driving a display panel according to an embodiment of the present invention. The driving method of the display panel is applicable to a display panel, and the display panel comprises N columns of display areas, N reset lines and M data lines, wherein M and N are positive integers. Each column display area includes a plurality of sub-pixels and M control chips, and the plurality of sub-pixels and the M control chips are disposed in corresponding display areas. Each control chip is electrically coupled to at least a portion of all sub-pixels in the corresponding display area. The N reset lines are electrically coupled to the M control wafers located in one of the N columns of display regions, respectively. The M data lines are electrically coupled to the M control wafers in each column display area (step S901).

Continuing the foregoing, when the picture update signal is input to one of the N reset lines, the M control chips in the corresponding display area respectively determine whether a data signal is input to the corresponding data line, so as to enable The M control wafers are selectively turned on or off (ie, updated or not updated) to selectively couple the sub-pixels of the M control wafers. When the plurality of control chips in the display area respectively receive the data signals, the corresponding control chips sequentially turn on the sub-pixels of the electrically coupled control chip according to the timing of the received data signals (step S903). ).

In one or more embodiments of the invention, each control crystal The chip receives a clock signal. When the picture update signal received by a control chip is at the first level, the clock signal is at a low logic level; when the picture update signal received by a control chip is at the second level, the clock signal is fixed. The pulse width is used to drive the sub-pixels of the control chip to be updated according to the data signals received by the control chip.

In addition, in the step of sequentially controlling the sub-pixels of the electrically coupled control chip according to the timing of the received data signals (step S903), if a control chip receives the pulse wave of the interrupt signal, Then, the sub-pixels of the control chip corresponding to the reception time of the pulse wave of the interrupt signal are not updated.

In summary, the present invention discloses a display panel and a driving method thereof, and a plurality of display areas for controlling a plurality of control wafers in a display panel. Each control chip is electrically coupled to at least a portion of the sub-pixels of the corresponding display area, and electrically coupled to the reset line and the data line, respectively. The display panel and the driving method thereof of the present invention can independently drive the control wafers in each display area by inputting a picture reset signal corresponding to the reset line corresponding to each display area, so that the control chip can be based on the clock signal and the corresponding The data signal updates its sub-pixels that are electrically coupled. In addition, the display panel of the present invention can change the number of signal traces according to actual needs, thereby increasing the flexibility of the design and reducing the hardware performance by different display partitioning methods or controlling the connection manner of the wafer and the sub-pixels. The complexity and difficulty of doing it. By the above various methods, the display panel and the driving method thereof disclosed by the present invention can achieve partial update display Face and energy saving.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention.

1‧‧‧ display panel

C _1,1 ~C _3,12 ‧‧‧Control chip

D ₁ ~D ₁₂ ‧‧‧Information line

R ₁ , R ₂ , R ₃ ‧‧‧reset line

Z ₁ , Z ₂ , Z ₃ ‧‧‧ display area

Claims (11)

A display panel includes: N columns of display areas, each of the N columns of display areas includes: a plurality of sub-pixels disposed in the display area; and M control chips disposed in the display area, each of the control chips Electrically coupled to at least a portion of the sub-pixels in the display area; N reset lines electrically coupled to the M control chips in one of the N columns of display regions And M data lines electrically coupled to the M control wafers in each of the column display regions; wherein M and N are positive integers. The display panel of claim 1, wherein the control wafers are electrically coupled to at least a portion of the sub-pixels in at least two adjacent columns of the display area. The display panel of claim 1, wherein the sub-pixels electrically coupled to the control wafer are respectively located on opposite sides of the control wafer. The display panel of claim 1, wherein when a picture update signal is input to one of the N reset lines, the M control chips in the corresponding column display area are respectively based on whether there is a data signal Input to the corresponding data line, so that the M control wafers are respectively The sub-pixels electrically coupled to the M control wafers are selectively updated or not updated. The display panel of claim 4, wherein each of the control chips further receives a clock signal, and when the picture update signal received by the control chip is at a first level, the clock signal is at a low level. a logic level, when the picture update signal received by the control chip is at a second level, the clock signal has a fixed pulse width to drive the sub-pixels electrically coupled to the control chip according to the logic level The data signal received by the control chip is updated. The display panel of claim 4, wherein when the plurality of control chips in the column display area respectively determine that the data signal is received, the corresponding control chips are respectively determined according to the received data signal. The sub-pixels electrically coupled to the control chips are sequentially updated in sequence. The display panel of claim 6, wherein the control chips sequentially update the sub-pixels electrically coupled to the control chips according to the timing of the received data signals, respectively When a certain control chip receives a pulse wave of an interrupt signal, the sub-pixels of the control chip corresponding to the reception time of the pulse wave of the interrupt signal are not updated. The display panel of claim 7, wherein the display panel further comprises a timing controller electrically coupled to the N reset lines and The M data lines, the timing controller is configured to generate the picture update signal, the data signal, and the interrupt signal. A display panel driving method is applicable to a display panel, comprising: N columns of display areas, N reset lines, and M data lines, wherein M and N are positive integers, and each of the N columns of display areas includes a plurality of sub- And a plurality of control pixels, wherein the sub-pixels and the M control chips are disposed in the display area, and each of the control chips is electrically coupled to the sub-pixels in the display area corresponding to the pixel At least a part of the N reset lines are electrically coupled to the M control chips in one of the N columns of display areas, and the M data lines are electrically coupled to each of the columns. The M control chips in the area, the display panel driving method includes: when a picture update signal is input to one of the N reset lines, the corresponding M control chips in the column display area Determining whether a data signal is input to the corresponding data line, so that the M control chips selectively update or not update the sub-pixels electrically coupled to the M control chips respectively; This column shows multiple controls in the area The timing of the data signals to the wafer receiving data signals, respectively, corresponding to the plurality of control according to the received wafer are sequentially updated to be electrically coupled to the plurality of the sub-pixel control of the wafer. The display panel driving method of claim 9, wherein each of the control chips further receives a clock signal, and when the image update signal received by the control chip is at a first level, the clock signal system At a low logic level, when the picture update signal received by the control chip is at a second level, the clock signal has a fixed pulse width to drive the sub-pixels electrically coupled to the control chip. Updating according to the data signal received by the control chip. The display panel driving method of claim 9, wherein the control chips sequentially turn on the sub-pixels electrically coupled to the control wafers according to the timing of the received data signals. If a certain control chip receives a pulse wave of an interrupt signal, the sub-pixels of the control chip corresponding to the reception time of the pulse wave of the interrupt signal are not updated.