TWI541956B - Elongated bump structure in semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to semiconductor devices, and more particularly to an elongated bump structure and a package assembly in a semiconductor device.

The integrated circuit wafer includes semiconductor components formed on a substrate (eg, a semiconductor wafer) and includes metal contacts, attachments, pads to provide an electrical interface to the circuit. Conventional techniques for providing the internal circuitry of a wafer to interface with an external circuit, such as a circuit board, another wafer or wafer, include wire bonding, which uses wire bonds to connect the pads of the wafer to an external circuit. A more advanced wafer bonding technique is flip chip technology, which uses integrated solder bumps deposited on the die pads to connect the integrated circuit components to external circuitry. In order to mount the wafer to an external circuit, the wafer is flipped with its top surface facing down and its pads aligned with corresponding pads on the external circuitry. The solder is then reflowed between the flip chip and the substrate supporting the external circuit to complete the interconnection. Since the wafer is directly on the external circuit, the flip chip package is much smaller than the conventional system using the carrier. This greatly reduces the inductance and resistance heat to achieve higher speed components.

Recently, the trend of high-density flip-chip interconnections has been to use circular copper stud bumps for the packaging of a central processing unit (CPU) and a graphics processing unit (GPU). Copper stud bumps are a replacement for traditional solder bumps, but copper stud bumps have some drawbacks. For example, round copper stud bumps add a lot of size to the interconnect structure, thus limiting the pitch of the metal lines of the interconnect. Therefore, the round copper bumps will eventually become the bottleneck of the integrated circuit industry that is constantly miniaturizing. Another disadvantage of round copper stud bumps is that the thermal expansion of the wafer and the package structure is mismatched by the mechanical stresses caused by the package circuit and its underlying layers. It has been observed that after the package, the stress at the edge of the under bump metallization (UBM) is very large, and the stress caused by it causes delamination of the dielectric layer, especially in the case of ultra low dielectric constant. A dielectric layer (extra low-k; k < 3). The package structure is therefore becoming more and more fragile. In addition, the interface of the circular bump-to-pad will have a large current density resulting in electromigration and electrical stress. Types of damage caused by electromigration include micro-racking of the solder joint and delamination of the joint layer.

An embodiment of the present invention provides a semiconductor device including: a wafer including a bump structure, wherein the bump structure includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar a width (W) measured along a minor axis of the conductive post; and a substrate comprising a wire and a mask layer over the wire, wherein the mask layer has an opening to expose a portion of the wire Wherein the wafer is bonded to the substrate to form an interconnection of the conductive pillar and the exposed portion of the conductor; and wherein the opening has a first dimension (d1) along the long axis of the conductive pillar and along A second dimension (d2) measured by the minor axis of the conductive pillar, and the ratio of L to d1 is greater than the ratio of W to d2.

Another embodiment of the present invention provides a semiconductor device including: a conductive pillar formed on a first substrate, the conductive pillar having a length (L) measured along a long axis of the conductive pillar and along the a width (W) measured by the short axis of the conductive post; and a wire formed on a second substrate; and a mask layer disposed on the wire and the second substrate, wherein the mask layer has An opening exposing a portion of the wire; wherein the conductive post is connected to the exposed portion of the wire via a solder layer; and wherein the opening of the mask layer has a first dimension measured along a major axis of the conductive post (d1), and d1 is smaller than L.

Another embodiment of the present invention provides a semiconductor device, a wafer including a bump structure, wherein the bump structure includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar a width (W) measured along a minor axis of the conductive post; and a substrate comprising a wire and a mask layer over the wire, wherein the mask layer has an opening to expose a portion of the wire; Wherein the wafer is attached to the substrate to form an interconnection of the conductive pillar and the exposed portion of the conductor; and wherein the opening has a first dimension (d1) measured along a long axis of the conductive pillar and along the A second dimension (d2) measured by the minor axis of the conductive column, and the ratio of L to d1 is not equal to the ratio of W to d2.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The manufacture and use of embodiments of the invention are detailed below. It will be appreciated that these embodiments provide a number of useful inventive concepts that can be widely applied in a variety of specific categories. This particular embodiment is intended to be illustrative of the particular embodiments and The embodiment herein relates to an elongated bump structure used on a semiconductor device. As discussed in the following embodiments, the elongated bump structure is used to attach a substrate to another substrate, wherein each substrate can be a die, a wafer, an interposer substrate, and a circuit. A board, a package substrate, or the like, thereby achieving a die-to-die, wafer-to-wafer, die or wafer pair transfer substrate, circuit board, package substrate, and the like. Elements that are similar in all embodiments to those illustrated in the drawings will use similar component symbols.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein the same or similar elements will be denoted by the same reference numerals. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the invention. Elements constituting or directly related to the elements of the device of the invention will be specifically described hereinafter. It should be particularly noted that elements not specifically shown or described may be in various forms well known to those skilled in the art. In addition, when a layer is described as being "an" another layer (or substrate), it can mean that the layer is in direct contact with another layer (or substrate) or otherwise. In the present specification, the description of the "an embodiment", the specific elements, structures, or characteristics described in the embodiments are included in at least one embodiment. Therefore, "in an embodiment" appearing in various places in the specification does not necessarily represent the same embodiment. Furthermore, the particular elements, structures, or characteristics described above may be combined in any suitable manner in one or more embodiments. It should be noted that the following illustrations are not drawn to scale and are merely for ease of illustration.

1 is a cross-sectional view of an elongated bump structure in accordance with an embodiment.

Referring to Figure 1, a portion of a wafer 100 is shown with electronic circuitry on and/or in substrate 10. The substrate 10 may be one of various semiconductor substrates commonly used in the fabrication of integrated circuits, and integrated circuits may be formed therein and/or thereon. The semiconductor substrate can be any structure containing a semiconductor material, including but not limited to: tantalum block, semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a germanium substrate. Other semiconductor materials include Group III, Group IV, and/or Group V semiconductors. Although not shown in the drawings, it should be understood that the substrate 10 may further comprise a plurality of isolation structures, such as a shallow trench isolation (STI) structure or a local germanium oxide (LOCOS) structure. The isolation structure can isolate various microelectronic components 12 formed in and/or on the substrate. Examples of microelectronic component 12 include, but are not limited to, a transistor such as a MOS field effect transistor, a complementary MOS transistor, a bipolar junction transistor, a high voltage transistor, a high frequency transistor, a p channel, and/or Or n-channel transistors, resistors, diodes, capacitors, inductors, fuses, and/or other suitable components. The microelectronic components described above can be formed by a variety of processes including, but not limited to, deposition, etching, implantation, lithography, tempering, or other suitable processes. The microelectronic elements are interconnected to form an integrated circuit device including one or more logic devices, memory elements (eg, SRAM), RF devices, input/output devices, system-on-chip devices, or other Suitable device.

The substrate 10 further includes an interconnect structure 14 on the integrated circuit. The interconnect structure 14 includes an inner dielectric layer and a metallization on the integrated circuit. The inner dielectric layer in the metallization layer structure may comprise one or more low dielectric constant materials, undoped bismuth glass (USG), tantalum nitride, hafnium oxynitride, or other commonly used materials. The low dielectric constant material may have a dielectric constant (k value) of less than about 3.9 or less than about 2.8. The metal lines in the metallization layer structure may be formed of copper or a copper alloy. The skilled person will be able to form a metallization layer structure using a suitable process, and thus the details will be omitted.

Conductive pads 16 are formed and patterned into or onto the inner dielectric layer of the top layer. The conductive pad 16 is part of a conductive path. The conductive pads 16 include pads that provide electrical connections on which bump structures such as bump under bump metal (UBM) structures or copper stud bumps can be formed for external electrical connections. Conductive pad 16 may be formed of any suitable electrically conductive material, including one or more of copper, tungsten, aluminum, aluminum tungsten alloy, silver, or the like. In some embodiments, the conductive pad 16 can be a region or end of a redistribution line to provide the desired needle or ball layout. As shown in FIG. 1, one or more protective layers 18 are formed on the conductive pads 16 and patterned. In an embodiment, an opening 19 is formed in the protective layer 18 to expose the underlying conductive pads 16. In at least one embodiment, the protective layer 18 is a non-organic material such as undoped bismuth glass, tantalum nitride, hafnium oxynitride, hafnium oxide, or a combination thereof. The protective layer 18 can be formed by any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. In other embodiments, the protective layer 18 may be a polymer layer such as epoxy resin, polyamidamine, benzocyclobutene (BCB), polybenzoxazole (PBO), etc., but Other relatively soft, generally organic, dielectric materials can also be used. It will be understood by those skilled in the art that only a single layer of conductive pads and protective layers are depicted herein, but other embodiments may include any number of conductive pads and/or protective layers.

FIG. 1 also shows a bump structure 20 on the protective layer 18 that is electrically connected to the conductive pad 16 via the opening 19. According to a feature of this embodiment, the shape of the bump structure 20 is elongated rather than circular. The elongated bump structure described above can be implemented in a variety of shapes including, but not limited to, a rectangle, a rectangle having at least one curved or rounded edge, a rectangle having two convex curved sides, an oval, an ellipse. Ellipse, or any other elongated shape.

In an embodiment, the bump structure 20 includes a bump underlayer metal 22 and a conductive pillar 24. A bump underlayer metal 22 is formed on the exposed surface of the protective layer 18 and the conductive pad 16. In some embodiments, the bump underlayer metal 22 comprises a diffusion barrier layer or an adhesion layer comprising Ti, Ta, TiN, TaN, etc., which may be formed by PVD or sputtering. The bump underlayer metal may further comprise a seed layer which may be formed on the diffusion barrier layer by PVD or sputtering. The seed layer may be formed of copper, an aluminum-containing copper alloy, chromium, nickel, tin, gold, or a combination thereof. In at least one embodiment, the bump underlayer metal 22 comprises a layer of titanium and a layer of copper seed.

A conductive post 24 is formed on the bump underlayer metal 22. In at least one embodiment, the conductive post 24 comprises a layer of copper. The copper layer comprises: pure copper element, copper with unavoidable impurities, and/or copper having a small amount of Ta, In, Sn, Zn, Mn, Cr, Ti, Ge, Sr, Pt, Mg, Al, or Zr elements. alloy. The conductive pillars 24 can be sputtered, printed, plated, electrolessly plated, electrochemically deposited, molecular beam epitaxy, atomic layer deposition, and/or conventional CVD processes. In an embodiment, the copper layer is formed by electrochemical plating. In an exemplary embodiment, the conductive pillars 24 have a thickness greater than 20 μm. In another example, the conductive pillars 24 have a thickness greater than 40 μm. For example, the conductive pillars 24 have a thickness of about 20 to 50 μm or about 40 to 70 μm, but the thickness thereof may be larger or smaller. In at least one embodiment, the conductive posts 24 are the same size and shape as the bump underlayer metal 22. In some embodiments, the size and shape of the conductive posts 24 are not exactly the same as the bump underlayer metal 22 because of variations in the process. For example, when the bump underlayer metal 22 forms an undercut, the bump underlayer metal 22 has a size smaller than the size of the conductive pillars 24.

In an alternate embodiment, an optional conductive cap layer is formed on the conductive posts 24. The conductive cap layer 26 is a metallization layer and may include Ni, Sb, SnPb, Au, Ag, Pd, In, Pt, NiPdAu, NiAu, or the like. The conductive cap layer 26 can be a multilayer structure or a single layer structure. In some embodiments, the conductive cap layer 26 has a thickness of about 1 to 5 μm. In at least one embodiment, the conductive cap layer 26 is a solder layer of lead-free solder, such as Sn, SnAg, Sn-Pb, SnAgCu (less than 0.3% by weight of Cu), SnAgZn, SnZn, SnBi-In, Sn-In, Sn-Au, SnPb, SnCu, SnZnIn, SnAgSb, or the like.

The above structure may be formed using any suitable process, and thus details thereof will not be discussed. Those skilled in the art will appreciate that while the above provides a general description of some of the components, various other components may be present in the wafer, such as other circuits, linings, barrier layers, interconnect metal structures, and the like. The above description is only to provide a context for understanding the embodiments, and is not intended to limit the scope of the invention to the specific embodiments.

2 is a plan view of a portion of a substrate on which a plurality of bump structures, such as bump structures 20c, 20e, are formed, which are equivalent to the bump structures 20 described above, in accordance with an embodiment. As described above, the elongated bump structures 20c, 20e can have a variety of shapes including, for example, an oval or a rectangle having two rounded edges. An elongated bump structure, such as elongated bump structure 20c, located at the corner of wafer 100, is directed toward central region 100c of wafer 100 and forms an angle of about 30-60 degrees with adjacent wafer edge 100e. An elongated bump structure along the edge of the wafer, such as elongated bump structure 20e, is disposed at an angle of 90 ± 15 degrees from the nearest wafer edge 100e. The wafer perimeter and corner regions typically require a minimum pitch because they typically carry a higher density interconnect structure than the power and ground terminals located in the central region 100c. As previously mentioned, the elongated bump structure provides a denser pitch and a larger process window than a conventional cylindrical array. It should be noted that the embodiments of the elongated bump structures located here at the edge of the wafer and at the corners of the wafer are merely illustrative. Other embodiments may provide the bump structure to the inner region of the wafer. In addition, the specific position and pattern of the bump structure may be changed, for example, including: a bump array, a column of bumps located in a middle region of the wafer, staggered bumps, and the like. The wafer and bump sizes shown are for reference only and not their actual size or actual relative size.

3 is an enlarged view of the conductive post 24 of the elongated bump structure 20, in accordance with an embodiment. The elongated bump structure 20 is composed of a bump underlayer metal 22 and a conductive pillar 24. In general, the conductive pillars 24 have a length L and a width W, where L represents the length measured along the long axis 200 of the conductive pillar 24, and W represents the length measured along the minor axis 300 of the conductive pillar 24. The stub shaft 300 is perpendicular to the long axis 200. Depending on the manner in which the array of bump structures is placed on the substrate 10, in some embodiments, the major axis 200 is oriented in a direction toward the central region 100c of the wafer 100. For example, the major axis 200 is perpendicular to the wafer edge 100e, or the major axis 200 forms an angle of about 90 ± 15 degrees with the adjacent wafer edge 100e.

A wafer having an elongated bump structure 20 will be bonded to a work piece at a wafer level or a die level, such as a package substrate, printed circuit board, interposer, wafer, or another wafer. . For example, embodiments can be used in die-to-die bonding configurations, die-to-wafer bonding configurations, wafer-to-wafer bonding configurations, die level packaging, wafer level packaging, etc. . The elongated bump structure 20 is subsequently connectable to the metal lines of the workpiece through the opening of a mask layer.

Figure 4 shows a partial cross-sectional view of the workpiece 400 attached to a wafer (e.g., wafer 100). FIG. 5 shows a cross-sectional view of a flip chip assembly in which wafer 100 is bonded to workpiece 400 in an embodiment.

Referring to FIG. 5, a portion of the workpiece 400 includes a substrate 40, which may be a package substrate, a printed circuit board, an interposer, a wafer, a die, a dielectric substrate, or other suitable substrate. The substrate 40 includes a plurality of wires 46 electrically connected to the underlying metal interconnects 42. The wire 46 may be formed of solid pure copper, aluminum copper alloy, or other metals such as W, Ni, Pd, Au, and the foregoing alloys. A portion of the wire 46 is defined as landing pad regions 46P to be electrically connected to the elongated bump structure 20. In one embodiment, a mask layer 48 is formed on the substrate 40 and patterned to cover a portion of the wires 46, while other portions of the wires 46 are uncovered. In at least one embodiment, a mask opening 50 is formed in the mask layer 48 to expose a portion of the wire 46 and the exposed portion serves as a cushion region 46P. The mask layer 48 may be formed of a solder resist material layer, a dielectric layer, a polymer layer, or other material that is resistant to solder. A mask layer 48 having a mask opening 50 provides a window of solder joint bump structures on other substrates. For example, a solder layer 52 is provided on the pad region 46P that includes an alloy of Sn, Pb, Ag, Cu, Ni, or a combination thereof.

The wafer 100 shown in FIG. 1 can be flipped upside down and bonded to the workpiece 400 as shown in FIG. 4 by flip chip bonding to form the package assembly 500 as shown in FIG. Bonding processes include, for example, applying flux, wafer placement, solder joints, and/or cleaning flux residues. A high temperature process, such as reflow or thermocompression bonding, can be performed to melt the solder layer 52 and/or the solder layer 26 on the conductive stud bumps 24. The molten solder layer thus bonds the wafer 100 to the workpiece 400 and electrically connects the elongated bump structure 20 to the pad region 46P. The reflow pad 502 formed by the molten solder layer is hereinafter referred to as a solder joint region. The conductive posts 24 overlap the pad regions 46P of the wires 46, thus forming a bump-on-trace (BOT) interconnect structure in the package assembly 500.

After solder bonding, a mold underfill (not shown) can be filled into the space between the wafer 100 and the workpiece 400, so that the mold bottom filler also fills the space between adjacent wires. In an alternate embodiment, a mold underfill may not be used in the package assembly 500.

Fig. 6 is an enlarged top plan view showing the relative relationship between the mask opening 50 and the conductive post 24 in the structure obtained in Fig. 5. The conductive post 24 has a length L measured along its major axis 200 and a width W measured along its minor axis 300. The length L is greater than the width W. In one embodiment, the length L is about 70 to 150 μm and the width W is about 40 to 100 μm. The mask opening 50 has a first dimension d1 measured along the long axis 200 of the conductive post 24 and a second dimension d2 measured along the minor axis 300 of the conductive post 24. The mask opening 50 can use a variety of shapes, such as a circle, a polygon, or any shape having a radial symmetry. In an embodiment, the first dimension d1 is equal to the second dimension d2. In another embodiment, the first dimension d1 is greater than the second dimension d2. In yet another embodiment, the first dimension d1 is less than the second dimension d2. For example, the first dimension d1 is about 50-90 μm, and the second dimension d2 is about 50-90 μm.

The geometry of the bump structure of this embodiment is designed to improve joint reliability and reduce bump fatigue. In at least one embodiment, the length L, the width W, the first dimension d1, and the second dimension d2 are related to each other in the following relationship: L/d1>W/d2 or L/d1≠W/d2. In an embodiment, the length L is greater than the first dimension d1. For example, the ratio of the length L to the first dimension d1 is about 1.05 to 2.0. In some embodiments, the ratio of the width W to the second dimension d2 is about 0.8 to 1.3. Embodiments disclosed herein can reduce stress in the ultra-low constant dielectric layer in the wafer and conform to fine bump pitch and high input/output (I/O) numbers.

A semiconductor device according to an embodiment of the invention includes a wafer having a bump structure. The bump structure includes a conductive pillar having a length (L) measured along a major axis of the conductive pillar and a width (W) measured along a minor axis of the conductive pillar. The semiconductor device further includes a substrate including a wire and a mask layer over the wire. The mask layer has an opening to expose a portion of the wire. The wafer is bonded to the substrate to form an interconnection of the conductive pillars with the exposed portions of the wires. The opening has a first dimension (d1) measured along a long axis of the conductive pillar and a second dimension (d2) measured along a minor axis of the conductive pillar, and a ratio of L to d1 is greater than The ratio of W to d2. The ratio of L to d1 is 1.05 to 2.0. The ratio of W to d2 is 0.8 to 1.3. The conductive post has an elongated shape. A solder bond region can be interposed between the conductive post and the exposed portion of the wire. The mask layer is formed of a layer of solder resist material. The conductive post contains copper. The wire contains copper. The long axis of the conductive pillar is perpendicular to an edge of the wafer. The long axis of the conductive pillar is directed to a central region of the wafer.

A semiconductor device according to another embodiment of the present invention includes a conductive pillar formed on a first substrate. The conductive post has a length (L) measured along the long axis of the conductive post and a width (W) measured along the short axis of the conductive post. A wire is formed on a second substrate. A mask layer is disposed on the wire and the second substrate, wherein the mask layer has an opening to expose a portion of the wire. The conductive post is connected to the exposed portion of the wire via a solder layer. The opening of the mask layer has a first dimension (d1) measured along the long axis of the conductive pillar, and d1 is less than L. The ratio of L to d1 is 1.05 to 2.0. The opening of the mask layer has a second dimension (d2) measured along the minor axis of the conductive pillar, wherein the ratio of W to d2 is 0.8 to 1.3. The conductive post has an elongated shape. The mask layer is formed of a layer of solder resist material. The conductive post contains copper. The wire contains copper. The first substrate is a semiconductor substrate, and the second substrate is a dielectric substrate.

A semiconductor device according to still another embodiment of the present invention includes a wafer having a bump structure. The bump structure includes a conductive pillar having a length (L) measured along a major axis of the conductive pillar and a width (W) measured along a minor axis of the conductive pillar. A substrate includes a wire and a mask layer over the wire. The mask layer has an opening to expose a portion of the wire. The wafer is bonded to the substrate to form an interconnection of the conductive pillars with the exposed portions of the wires. The opening has a first dimension (d1) measured along a long axis of the conductive pillar and a second dimension (d2) measured along a minor axis of the conductive pillar, and the ratio of L to d1 is not Equal to the ratio of W to d2. The ratio of L to d1 is 1.05 to 2.0.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

10. . . Substrate

12. . . Microelectronic component

14. . . Inline structure

16. . . Conductive pad

20, 20c, 20e. . . Bump structure

twenty two. . . Bump bottom metal

twenty four. . . Conductive column

26. . . Conductive cover

W. . . width

L. . . length

100. . . Wafer

100c. . . central area

100e. . . Wafer edge

200. . . Long axis

300. . . Short axis

400. . . Work piece

40. . . Substrate

42. . . Metal interconnect

46. . . wire

46P. . . Cushion area

48. . . Mask layer

500. . . Package component

502. . . Reflow zone

50. . . Mask opening

D1. . . First size

D2. . . Second size

1 is a cross-sectional view of an elongated bump structure in accordance with an embodiment.

2 is a plan view showing a plurality of elongated bump structures disposed on a substrate, according to an embodiment.

Figure 3 is an enlarged view of a conductive post of an elongated bump structure in accordance with an embodiment.

Figure 4 is a cross-sectional view of a portion of the workpiece in accordance with an embodiment.

Figure 5 is a cross-sectional view of a flip chip assembly including a wafer bonded to a workpiece, in accordance with an embodiment.

Figure 6 is a top plan view of the opposing relationship of the mask opening to the conductive posts, in accordance with an embodiment.

W. . . width

L. . . length

18. . . The protective layer

20c, 20e. . . Bump structure

100c. . . central area

100e. . . Wafer edge

Claims (11)

A semiconductor device comprising: a wafer comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and along the conductive pillar a width (W) measured by the minor axis; and a substrate comprising a wire and a mask layer over the wire, wherein the mask layer has an opening to expose a portion of the wire; wherein the wafer is bonded And the substrate is formed to form an interconnection of the conductive pillar and the exposed portion of the wire; and wherein the opening has a first dimension (d1) measured along a long axis of the conductive pillar and a minor axis along the conductive pillar A second dimension (d2) is measured, and the ratio of L to d1 is greater than the ratio of W to d2. The semiconductor device according to claim 1, wherein the ratio of L to d1 is 1.05 to 2.0. The semiconductor device according to claim 1, wherein the ratio of W to d2 is 0.8 to 1.3. The semiconductor device of claim 1, wherein the conductive pillar has an elongated shape. The semiconductor device of claim 1, wherein the long axis of the conductive pillar is perpendicular to an edge of the wafer. The semiconductor device of claim 1, wherein the long axis of the conductive pillar is directed to a central region of the wafer. A semiconductor device comprising: a conductive pillar formed on a first substrate, the conductive pillar having a length (L) measured along a long axis of the conductive pillar and a short axis along the conductive pillar Measure a width (W); a wire formed on a second substrate; and a mask layer disposed on the wire and the second substrate, wherein the mask layer has an opening to expose a portion of the wire; Wherein the conductive pillar is connected to the exposed portion of the wire via a solder layer; and wherein the opening of the mask layer has a first dimension (d1) measured along a long axis of the conductive pillar, and d1 is less than L . The semiconductor device according to claim 7, wherein the ratio of L to d1 is 1.05 to 2.0. The semiconductor device of claim 7, wherein the opening of the mask layer has a second dimension (d2) measured along a minor axis of the conductive pillar, wherein a ratio of W to d2 is 0.8. ~1.3. The semiconductor device of claim 7, wherein the conductive pillar has an elongated shape. A semiconductor device comprising: a wafer comprising a bump structure, wherein the bump structure comprises a conductive pillar having a length (L) measured along a long axis of the conductive pillar and along the conductive pillar a width (W) measured by the minor axis; and a substrate comprising a wire and a mask layer over the wire, wherein the mask layer has an opening to expose a portion of the wire; wherein the wafer is bonded And the substrate is formed to form an interconnection of the conductive pillar and the exposed portion of the wire; and wherein the opening has a first dimension (d1) measured along a long axis of the conductive pillar and a minor axis along the conductive pillar A second dimension (d2) is measured, and the ratio of L to d1 is not equal to the ratio of W to d2.