TWI541806B - Content addressable memory - Google Patents

Description

Content addressable memory

The present invention relates to a content addressable memory (CAM), in particular, a ternary content addressable memory (TCAM).

The content-addressable memory includes a plurality of content-addressable memory cells (CAM cells) arranged in an array, and compares the stored contents with a search data in units of columns to generate a match corresponding to the plurality of columns respectively. Bit. The content addressable memory may be binary, ternary, or other content addressable memory, depending on the number of states that each content can address the memory cells.

When the content addressable memory is a binary content addressable memory, each content addressable memory cell includes a data memory cell and a comparison circuit, wherein the data memory cell stores a data bit and a complementary data bit, It is one of two logical states of "0" and "1". When the content addressable memory is a ternary content addressable memory, each content addressable memory cell includes a data memory cell, a mask memory cell, and a comparison circuit, wherein the data memory cell is stored a data bit and a complementary data bit, the mask memory cell stores a mask bit and a complementary mask bit, and the two cooperate to represent "0", "1" and "don't care (don't Care)" One of these three logical states.

In general, when the word-line is at logic "1", the content-addressable memory can read or write to the memory cell via a bit-line. However, when a plurality of memory cells are arranged in an array or a matrix, interference in the direction of the word line often occurs, that is, the logic state of the word line is "1", but no reading or writing operation is performed. This often leads to problems with data loss. Therefore, it is necessary to develop new content addressable memory technology to improve it.

Therefore, one of the objects of the present invention is to solve the above problems.

According to an embodiment of the present invention, a content addressable memory includes: a data memory unit for storing a data bit; a mask memory unit for storing a mask bit; and a Comparing and reading unit, connecting at least one read word line to receive at least one read block signal, connecting at least one function bit line to receive a search bit signal, and coupling the data memory unit and the mask The memory unit accepts the data bit and the mask bit; wherein the data memory unit is connected to a data write word line to receive a data write block signal, and the mask memory unit is connected to a mask Writing a block line to receive a mask write block signal, thereby controlling whether a write bit signal can be written into the data bit and the mask bit via a pair of write bit lines; wherein The comparing and reading unit compares the data bit, the mask bit, and the search bit signal to determine whether the three are matched; and wherein the comparing and reading unit reads according to the at least one The block signal determines the capital And if the bit mask bit can be read.

According to another embodiment of the present invention, a content addressable memory includes: a data storage unit for storing a data bit; a mask memory unit for storing a mask bit; a comparison and reading unit, connecting at least one read word line to receive at least one read block signal, connecting at least one function bit line to receive a search bit signal, and coupling the data memory unit and the cover The cover memory unit receives the data bit and the mask bit; wherein the data memory unit and the mask memory unit are connected to a write word line to receive a write block signal, thereby controlling a data write Whether the bit signal and a mask write bit signal can be written into the data bit and the mask bit respectively via a pair of data write bit lines and a pair of mask write bit lines The comparison and reading unit compares the data bit, the mask bit, and the search bit signal to determine whether the three are matched; and wherein the comparing and reading unit is based on the at least Read the block signal decision Whether the data bits and mask bits can be read.

In an embodiment, the at least one function bit line may include a pair of mixed bit lines, and if the comparison and reading unit allows the data bit and the mask bit to be read, the data bit And the mask bit is read via the pair of mixed bit lines.

100/200/300/400/500/600‧‧‧Content addressable memory

110‧‧‧Data Memory Unit

120‧‧‧mask memory unit

130‧‧‧Comparative and reading unit

132‧‧‧Comparative circuit

134‧‧‧Read circuit

M‧‧‧match signal

N0D/N1D‧‧‧ data bits

N0C/N1C‧‧‧ mask bit

VDD‧‧‧ DC voltage source

HBLP/HBLN‧‧‧ mixed bit line

RBL‧‧‧Read bit line

RBLD‧‧‧ data read bit line

RBLC‧‧‧Reading bit line for mask

SBLP/SBLN‧‧‧Search bit line

RWL‧‧‧Reading word line

RWLD‧‧‧ data read word line

RWLC‧‧‧Reading word line for mask

WBLP/WBLN‧‧‧ write bit line

WBLDP/WBLDN‧‧‧ data is written to the bit line

WBLCP/WBLCN‧‧‧Writing bit line for mask

WWL‧‧‧Write word line

WWLD‧‧‧ data is written to the word line

Write word line for WWLC‧‧‧ mask

MP0/MP1/MP2/MP3/MN0/MN1/MN2/MN3/MN4/MN5‧‧‧Optoelectronics

1 is a block diagram showing a content addressable memory according to a first embodiment of the present invention.

2 is a block diagram showing a content addressable memory according to a second embodiment of the present invention.

Figure 3 is a block diagram showing the content addressable memory of the third embodiment of the present invention.

4 is a block diagram showing a content addressable memory according to a fourth embodiment of the present invention.

Figure 5 is a block diagram showing the content addressable memory of the fifth embodiment of the present invention.

Figure 6 is a block diagram showing the content addressable memory of the sixth embodiment of the present invention.

Fig. 7 is a schematic diagram of a memory circuit designed with a gold oxide semi-transistor, taking the content addressable memory of the third embodiment or the sixth embodiment as an example.

For a more detailed understanding and understanding of the features, objects and functions of the present invention, the present invention will be described in detail with reference to the drawings. In all of the specification and the drawings, the same component numbers will be used to designate the same or similar components.

1 is a block diagram showing a content addressable memory 100 according to a first embodiment of the present invention. The content addressable memory 100 includes: a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130, which can implement a ternary content addressable memory (TCAM). The data storage unit 110 is configured to store a data bit; the mask memory unit 120 is configured to store a mask bit; the comparison and reading unit 130 is configured to compare Searching for a bit signal, the data bit, and the mask bit to determine whether a match between the three outputs a match signal M; and the content addressable memory 100 can be used by the compare and read unit The data bit N0D and the mask bit N0C are read.

In addition, in order to enable the content addressable memory of the embodiment to be addressed according to the search bit signal, the data bit, and the mask bit, and to read or write the content, the content addressable memory The method further includes: at least one read word-line, at least one functional bit-line, one data-use write word-line, and one Mask-use write word-line and a pair of write bit-line. In this manner, the comparison and reading unit 130 can connect the at least one read word line to receive at least one read block signal, connect the at least one function bit line to receive a search bit signal, and couple the data. The memory unit and the mask memory unit receive the data bit and the mask bit; the data memory unit 110 can connect the data to the write word line to receive a data write block signal, the mask memory The unit 120 can be connected to the mask write word line to receive a mask write block signal, thereby controlling whether a write bit signal can be written into the data bit via the pair of write bit lines. And the mask bit.

In the embodiment shown in FIG. 1, the at least one read word line is a read word line RWL, and the at least one function bit line is a pair of mixed bit lines HBLP and HBLN. The data is indicated by the write word line as WWLD, which is indicated by the write word line as WWLC, and the pair of write bit lines are labeled WBLP and WBLN. As such, the compare and read unit 130 is coupled to the read word line RWL to accept the read block signal, and the compare and read unit 130 connects the pair of mixed bit lines HBLP and HBLN to accept the search bit signal. The comparison and reading unit 130 is coupled to the data storage unit 110 and the mask memory unit 120 to receive the data bit NOD and the mask bit N0C. The data memory unit 110 is connected to the data write word line WWLD. The data is written into the block signal, and the mask memory unit 120 is connected to the mask write word line WWLC to accept the mask write block signal. Therefore, the content addressable memory 100 can write the write bit signal to the data memory unit 110 via the pair of write bit lines WBLP and WBLN under the control of the data write block signal and the The memory unit 120 is masked. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether the match between the three is output, and if the result is a match If the match signal M is a high logic level output, otherwise the low logic level match signal M is output. In addition, the content addressable memory 100 can read the data bit N0D stored by the data storage unit 110 and the cover via the pair of mixed bit lines HBLP and HBLN under the control of the read block signal. The mask bit N0C stored by the cover memory unit 120. The pair of mixed bit lines HBLP and HBLN can be used as both read bit and search bit transfer, and is therefore referred to as double effect or hybrid (Hybrid).

2 is a block diagram of a content addressable memory 200 in accordance with a second embodiment of the present invention. The content addressable memory 200 includes: a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130. In the embodiment shown in FIG. 2, the at least one read word line is a read word line RWL, and the at least one function bit line includes a data read bit line RBLD and a strip. The mask read bit line RBLC, and a pair of search bit lines SBLP and SBLN, the data is indicated by the write word line as WWLD, the mask is marked as WWLC by the write word line, and the pair is written The entry line is labeled WBLP and WBLN. As such, the compare and read unit 130 is coupled to the read word line RWL to accept the read block signal, and the compare and read unit 130 is coupled to the search bit lines SBLP and SBLN to accept the search bit signal. And the reading unit 130 is coupled to the data storage unit 110 and the mask memory unit 120 to receive the data bit NOD and the mask bit N0C, and the data memory unit 110 is connected to the data write word line WWLD to accept The data is written to the block signal, and the mask memory unit 120 is connected to the mask write word line WWLC to accept the mask write block signal.

Therefore, the content addressable memory 200 can write the write bit signal to the data memory unit 110 via the pair of write bit lines WBLP and WBLN under the control of the data write block signal and the The memory unit 120 is masked. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether a match between the three is output and output a match signal M, if the result is a match Then, the matching signal M is an output of a high logic level, otherwise a matching signal M of a low logic level is output. In addition, the content addressable memory 100 can read the bit line RBLD via the data under the control of the read block signal. The mask reads the data bit stored by the data storage unit 110 and the mask bit stored by the mask memory unit 120 by using the read bit line RBLC.

FIG. 3 is a block diagram showing a content addressable memory 300 according to a third embodiment of the present invention. The content addressable memory 300 includes: a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130. In the embodiment as shown in FIG. 2, the at least one read word line system includes a data read word line RWLD and a mask read word line RWLC, the at least one function bit line. The system includes a read bit line RBL and a pair of search bit lines SBLP and SBLN. The data is indicated by the write word line as WWLD, and the mask is marked as WWLC by the write word line, and the pair is written. The bit lines are labeled WBLP and WBLN. In this manner, the comparison and reading unit 130 is connected to the data read word line RWLD and the mask read word line RWLC to receive the data read block signal and the mask read block signal, respectively. The comparison and reading unit 130 is connected to the search bit lines SBLP and SBLN to receive the search bit signal. The comparison and reading unit 130 is coupled to the data memory unit 110 and the mask memory unit 120 to receive the data bit N0D. And the mask bit N0C, the data memory unit 110 is connected to the data write word line WWLD to receive the data write block signal, and the mask memory unit 120 is connected to the mask write word line WWLC. Accept the mask to write the block signal.

Therefore, the content addressable memory 300 can write the write bit signal to the data memory unit 110 via the pair of write bit lines WBLP and WBLN under the control of the data write block signal and the The memory unit 120 is masked. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether the match between the three is output and output the match signal M, if the result is a match Then, the matching signal M is an output of a high logic level, otherwise a matching signal M of a low logic level is output. In addition, the content addressable memory 100 can read the data bit N0D stored by the data storage unit 110 and the mask memory unit 120 via the read bit line RBL under the control of the read block signal. The stored mask bit N0C.

In the first, second and third embodiments described above, the data memory unit 110 and the mask memory unit 120 share a pair of write bit lines WBLP and WBLN. Of course The present invention is also applicable to an embodiment in which the data storage unit 110 and the mask memory unit 120 share a write word line WWL, which is described in detail below.

4 is a block diagram showing a content addressable memory 400 according to a fourth embodiment of the present invention. The content addressable memory 400 includes: a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130, which can implement a ternary content addressable memory (TCAM), and a detailed description thereof is provided. Refer to the first embodiment, and details are not described herein again.

In order to enable the content addressable memory of the embodiment to be addressed according to the search bit signal, the data bit N0D, and the mask bit N0C, and to read or write the content, the content addressable memory The method further includes at least one read word line, at least one function bit line, one write word line, a pair of data write bit lines, and a pair of mask write bit lines. In this manner, the comparison and reading unit 130 can connect the at least one read word line to receive at least one read block signal, connect the at least one function bit line to receive a search bit signal, and couple the data. The memory unit and the mask memory unit receive the data bit and the mask bit; the data memory unit 110 and the mask memory unit 120 can be connected to the write word line to receive a write block signal. By controlling whether a data write bit signal can be written to the data bit via the pair of data write bit lines, and controlling whether a mask write bit signal can be written via the pair of masks The bit line is written to the mask bit.

In the embodiment shown in FIG. 4, the at least one read word line is a read word line RWL, and the at least one function bit line is a pair of mixed bit lines HBLP and HBLN. The write word line is labeled as WWL, and the pair of data is written as WBLDP and WBLDN by the write bit line, and the pair of mask write bit lines are labeled as WBLCP and WBLCN. As such, the compare and read unit 130 is coupled to the read word line RWL to accept the read block signal, and the compare and read unit 130 connects the pair of mixed bit lines HBLP and HBLN to accept the search bit signal. The data storage unit 110 and the mask memory unit 120 are coupled to the data memory unit 110 and the mask memory unit 120 to receive the data bit NOD and the mask bit N0C. The data memory unit 110 and the mask memory unit 120 are connected to the write unit. The word line WWL accepts the write block signal. Therefore, the content addressable memory 100 can write data to the bit under the control of the write block signal. The meta signal is written into the data memory unit 110 via the pair of data write bit lines WBLDP and WBLDN, and the mask write bit signal is written via the pair of mask write bit lines WBLCP and WBLCN. The mask memory unit 120. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether a match between the three is output and output a match signal M, if the result is a match Then, the matching signal M is an output of a high logic level, otherwise a matching signal M of a low logic level is output. In addition, the content addressable memory 400 can read the data bit and the mask stored by the data storage unit 110 via the pair of mixed bit lines HBLP and HBLN under the control of the read block signal. The mask bit stored by the memory unit 120. The pair of mixed bit lines HBLP and HBLN can be used as both read bit and search bit transfer, and is therefore referred to as double effect or hybrid (Hybrid).

FIG. 5 is a block diagram showing a content addressable memory 500 according to a fifth embodiment of the present invention. The content addressable memory 500 includes a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130. In the embodiment shown in FIG. 5, the at least one read word line is a read word line RWL, and the at least one function bit line includes a data read bit line RBLD and a strip. The mask read bit line RBLC and a pair of search bit lines SBLP and SBLN, the write word line is denoted as WWL, and the pair of data is written as WBLDP and WBLDN by the write bit line, and the pair is covered The mask is labeled WBLCP and WBLCN with write bit lines. As such, the compare and read unit 130 is coupled to the read word line RWL to accept the read block signal, and the compare and read unit 130 is coupled to the search bit lines SBLP and SBLN to accept the search bit signal. And the reading unit 130 is coupled to the data storage unit 110 and the mask memory unit 120 to receive the data bit NOD and the mask bit N0C. The data memory unit 110 and the mask memory unit 120 are connected to the write word. The line WWL is grouped to accept the write block signal.

Therefore, the content addressable memory 500 can write the data write bit signal to the data memory unit 110 via the pair of data write bit lines WBLDP and WBLDN under the control of the write block signal. And writing the mask into the bit signal and writing the mask to the mask by writing the bit lines WBLDP and WBLDN Recall unit 120. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether a match between the three is output and output a match signal M, if the result is a match Then, the matching signal M is an output of a high logic level, otherwise a matching signal M of a low logic level is output. In addition, the content addressable memory 500 can read the data memory unit via the data read bit line RBLD and the mask read bit line RBLC under the control of the read block signal. 110 stored data bits and mask bits stored by the mask memory unit 120.

FIG. 6 is a block diagram showing a content addressable memory 600 according to a sixth embodiment of the present invention. The content addressable memory 600 includes: a data storage unit 110, a mask memory unit 120, and a comparison and reading unit 130. In the embodiment as shown in FIG. 6, the at least one read word line system includes a data read word line RWLD and a mask read word line RWLC, the at least one function bit line. The system includes a read bit line RBL and a pair of search bit lines SBLP and SBLN, the write word line is denoted as WWL, and the pair of data is marked as WBLDP and WBLDN by the write bit line, and the pair of masks Written as bit lines with WBLCP and WBLCN. In this manner, the comparison and reading unit 130 is connected to the data read word line RWLD and the mask read word line RWLC to receive the data read block signal and the mask read block signal, respectively. The reading unit 130 is connected to the search bit lines SBLP and SBLN to receive the search bit signal. The comparison and reading unit 130 is coupled to the data memory unit 110 and the mask memory unit 120 to receive the data bit NOD and The mask bit N0C, the data memory unit 110 and the mask memory unit 120 are connected to the write word line WWL to accept the write block signal.

Therefore, the content addressable memory 600 can write the data write bit signal to the data memory unit 110 via the pair of data write bit lines WBLDP and WBLDN under the control of the write block signal. And writing the mask write bit signal to the mask memory unit 120 via the pair of mask write bit lines WBLCP and WBLCN. The comparison and reading unit 130 compares the search bit signal, the data bit N0D, and the mask bit N0C to determine whether a match between the three is output and output a match signal M, if the result is a match , the matching signal M is high logic The output of the level is set, otherwise the matching signal M of the low logic level is output. In addition, the content addressable memory 600 can read the data bit stored by the data storage unit 110 and the mask memory unit 120 via the read bit line RBL under the control of the read block signal. The mask bit.

In each embodiment of the present invention, the data storage unit 110 and the mask memory unit 120 can be implemented by a static random access memory (SRAM) memory element, for example, six batteries. A 6T-SRAM memory cell composed of crystals is shown in Fig. 7. Among them, the SRAM memory cell belongs to the prior art and will not be described here. In order to implement the ternary content addressable memory of the present invention on a circuit, FIG. 7 is an example of the content addressable memory 300 of the third embodiment or the content addressable memory 600 of the sixth embodiment, taking gold oxide as an example. A schematic diagram of a memory circuit designed by a MOS transistor and described in detail below.

As shown in FIG. 7, the comparison and reading unit 130 includes a first transistor stack and a second transistor stack; wherein the first transistor stack is two P-type transistors MP0 and MP2 and two The N-type transistors MN4 and MN0 are sequentially connected in series to form a stack, and the second transistor stack is formed by sequentially connecting two P-type transistors MP1 and MP3 and two N-type transistors MN5 and MN3 in series. Stacking. In the first transistor stack, the source of the transistor MP0 is connected to the DC voltage source VDD, the gate thereof is connected to the data memory unit 110 to receive the data bit NOD, and the drain thereof is connected to the source of the transistor MP2. The gate of the transistor MP2 is connected to the search bit line SBLP to receive the search bit signal, and the drain thereof is connected to the drain of the transistor MN4; the gate of the transistor MN4 is also connected to the search bit line SBLP To receive the search bit signal, and the source thereof is connected to the drain of the transistor MN0; the gate of the transistor MN0 is connected to the mask memory unit 120 to receive the mask bit N0C, and the source thereof is connected to a ground terminal . In the second transistor stack, the source of the transistor MP1 is connected to the DC voltage source VDD, the gate thereof is connected to the mask memory unit 120 to receive the mask bit N0C, and the drain thereof is connected to the transistor MP3. a gate of the transistor MP3 is connected to the search bit line SBLN to receive a search bit signal, and a drain thereof is connected to a drain of the transistor MN5; a gate of the transistor MN5 is also connected to the search bit line The SBLN accepts the search bit signal, and its source is connected to the drain of the transistor MN3; the gate of the transistor MN3 is connected to the data memory unit 110 to receive the data bit N0D, and the source thereof is connected to a ground. In addition, the drain connection points of the transistors MP2 and MN4 are connected to the drain connection points of the transistors MP3 and MN5 for outputting the matching signal M.

By the above description, the combination of the transistors MP0, MP1, MP2, MP3, MN0, MN3, MN4 and MN5 forms a comparison circuit 132, and compares the search bit signal, the data bit NOD, and the mask bit N0C. To determine if there is a match between the three. The function of the comparison circuit is: "storage content" (that is, data bit N0D and mask bit N0C) of the data storage unit 110 and the mask memory unit 120 and "from the search bit lines SBLP and SBLN". The input content (that is, the search bit signal) is compared. The above "storage content" includes 1, 0, don't care three kinds of information, which is composed of data bit N0D and mask bit N0C; and the above comparison circuit is exclusive or (Exclusive-OR, Referring to the XOR) logic gate to compare the "input content" and the "storage content". If the two are the same or the "storage content" is "disregarded", the comparison circuit outputs a matching signal M or a matching signal M of a high logic level. It is logic "1", otherwise the matching signal M or the matching signal M outputting the low logic level is logic "0". The following is the truth table of the embodiment.

In addition, as shown in FIG. 7, the comparison and reading unit 130 further includes N-type transistors MN1 and MN2; wherein the transistors MN1 and MN2 and the transistor MN0 and the second in the first transistor stack The transistor MN3 in the transistor stack constitutes a read circuit 134. The drain of the transistor MN1 is connected to the read bit a line RBL, a gate thereof connected to the mask read word line RWLC to receive a mask read block signal, and a source connected to the drain of the transistor MN0; and the drain of the transistor MN2 is also connected The read bit line RBL has its gate connected to the data read word line RWLD to receive the data read block signal, and its source is connected to the drain of the transistor MN3.

Thereby, when the data read block signal is logic "1", the content addressable memory 300 or 600 can read the data bit N0D via the read bit line RBL; and when the mask reads When the word string signal is logic "1", the content addressable memory 300 or 600 can read the mask bit N0C via the read bit line RBL. Please note that in the comparison and reading unit 130 of the present embodiment, the comparison circuit (including the transistors MP0, MP1, MP2, MP3, MN0, MN3, MN4, and MN5) and the read circuit (including the transistor MN0, MN1, MN2, and MN3) share two transistors MN0 and MN3; that is, the present embodiment combines the comparison circuit and the read circuit of the content addressable memory into the comparison and reading unit 130, and the content of each unit can be The number of transistors required to address the memory can be reduced from the original 12 to 10 in the present embodiment, which greatly reduces the manufacturing cost. In addition, in this embodiment, the data read and write paths of the content addressable memory are separated, thereby avoiding reading or writing when the logic state of the word line is "1" as described in the prior art. The problem of "interference in the direction of the word line" of the action.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention, and should be considered as a further embodiment of the present invention.

110‧‧‧Data Memory Unit

120‧‧‧mask memory unit

130‧‧‧Comparative and reading unit

132‧‧‧Comparative circuit

134‧‧‧Read circuit

M‧‧‧match signal

N0D/N1D‧‧‧ data bits

N0C/N1C‧‧‧ mask bit

VDD‧‧‧ DC voltage source

RBL‧‧‧Read bit line

SBLP/SBLN‧‧‧Search bit line

RWLD‧‧‧ data read word line

RWLC‧‧‧Reading word line for mask

WBLP/WBLN‧‧‧ write bit line

WWLD‧‧‧ data is written to the word line

Write word line for WWLC‧‧‧ mask

MP0/MP1/MP2/MP3‧‧‧O crystal

MN0/MN1/MN2/MN3/MN4/MN5‧‧‧Optoelectronics

Claims (10)

A content addressable memory comprising: a data storage unit for storing a data bit; a mask memory unit for storing a mask bit; and a comparison and reading unit for connecting at least one read Taking a word line to receive at least one read block signal, connecting at least one function bit line to receive a search bit signal, and coupling the data memory unit and the mask memory unit to accept the data bit and the a mask bit; wherein the at least one function bit line includes a pair of search bit lines, and the comparison and read unit comprises: a first transistor stack connecting one of the pair of search bit lines to accept Searching the bit signal and connecting the data memory unit and the mask memory unit to receive the data bit and the mask bit; a second transistor stack connecting the other of the pair of search bit lines to accept Searching for a bit signal, connecting the data memory unit and the mask memory unit to receive the data bit and the mask bit; a first transistor connecting the first transistor stack, the pair of search bits line, The at least one read word line to receive the at least one read block signal; and a second transistor connected to the second transistor stack, the pair of search bit lines, and the at least one read word line Receiving the at least one read block signal; wherein the data storage unit is connected to a data write word line to receive a data write block signal, the mask memory unit is connected to a mask write word block The line receives a mask write block signal to control whether a write bit signal can be written into the data bit and the mask bit via a pair of write bit lines; wherein the comparing and reading Comparing the data bit, the mask bit, and the search bit signal with the first and second transistor stacks of the unit, thereby determining whether the three are matched, and outputting a matching signal; The first and second transistors of the comparison and reading unit determine whether the data bit and the mask bit can be read according to the at least one read block signal. The content as claimed in claim 1, wherein the at least one functional bit line comprises a pair of mixed bit lines, and if the comparing and reading unit allows the data bit and the mask The bit is read, and the data bit and the mask bit are read via the pair of mixed bit lines. The content as described in claim 1, wherein the at least one function bit line includes a data read bit line, a mask read bit line, and a pair of search bit lines. And if the comparison and reading unit allows the data bit and the mask bit to be read, the data bit and the mask bit are read by the data reading bit line and the mask respectively The bit line is read. The content addressable memory as described in claim 1 , wherein the at least one read word line includes a data read word line and a mask read word line, and the provided The at least one read block signal includes a data read block signal and a mask read block signal, the at least one function bit line includes a read bit line and a pair of search bit lines, and The comparison and reading unit allows the data bit and the mask bit to be read, and the data bit and the mask bit are read via the read bit line. The content as described in claim 1, wherein the data storage unit comprises a first static random access memory component, and the mask memory unit comprises a second static random access memory component. A content addressable memory comprising: a data storage unit for storing a data bit; a mask memory unit for storing a mask bit; and a comparison and reading unit for connecting at least one read Taking a word line to receive at least one read block signal, connecting at least one function bit line to receive a search bit signal, and coupling the data memory unit and the mask memory unit to accept the data bit and the a mask bit; wherein the at least one function bit line includes a pair of search bit lines, and the comparison and read unit comprises: a first transistor stack connecting one of the pair of search bit lines to accept Searching the bit signal and connecting the data memory unit and the mask Retrieving the unit to receive the data bit and the mask bit; a second transistor stack connecting another one of the pair of search bit lines to receive the search bit signal, and connecting the data memory unit and the mask The memory unit accepts the data bit and the mask bit; a first transistor connecting the first transistor stack, the pair of search bit lines, and the at least one read word line to accept the at least one Reading a block signal; and a second transistor connecting the second transistor stack, the pair of search bit lines, and the at least one read word line to accept the at least one read block signal; wherein The data storage unit and the mask memory unit are connected to a write word line to receive a write block signal, thereby controlling whether a data write bit signal and a mask write bit signal can pass through a pair of data. The data bit and the mask bit are respectively written by the write bit line and the pair of mask write bit lines; wherein the first and second transistors of the comparison and read unit Stacking the data bit, the mask bit, and the search bit a number to determine whether the match between the three is matched, and outputting a match signal; and wherein the first and second transistors of the compare and read unit determine the data bit according to the at least one read block signal And whether the mask bit can be read. The content addressable memory as described in claim 6 wherein the at least one function bit line comprises a pair of mixed bit lines, and if the comparison and reading unit allows the data bit and the mask The bit is read, and the data bit and the mask bit are read via the pair of mixed bit lines. The content addressable memory as described in claim 6 , wherein the at least one function bit line comprises a data read bit line, a mask read bit line, and a pair of search bits. a line, and if the comparison and reading unit allows the data bit and the mask bit to be read, the data bit and the mask bit respectively read the bit line and the mask via the data The read bit line is read. The content addressable memory as described in claim 6 , wherein the at least one read word line includes a data read word line and a mask read word line, and the provided The at least one read block signal includes a data read block The signal and a mask read the block signal, the at least one function bit line includes a read bit line and a pair of search bit lines, and if the comparison and reading unit allows the data bit and the mask The bit is read, and the data bit and the mask bit are read to the read bit line, respectively. The content as described in claim 6 is an addressable memory, wherein the data storage unit comprises a first static random access memory component, and the mask memory unit comprises a second static random access memory component.