TWI539582B - Display panel and fabricating method thereof - Google Patents

Description

Display panel and its making method

The present invention relates to a display panel and a method of fabricating the same, and more particularly to a display panel having better structural reliability and a method of fabricating the same.

A conventional active device array substrate is formed by forming an active device on a substrate, and then covering the active device with a complete protective layer, wherein the protective layer completely covers the active device and the substrate. Thereafter, the protective layer is etched to the active device, and a patterned pixel electrode is further formed on the protective layer, wherein the patterned pixel electrode exposes a portion of the underlying protective layer. However, when the protective layer is etched to the active device, the problem of surface damage of the active device and poor contact surface may still occur. As a result, the process yield of the active device array substrate is reduced, and the structural reliability of the active device array substrate is also reduced.

The invention provides a display panel and a manufacturing method thereof, which can solve the problem of erosion to an active component or a color filter pattern in a conventional etching process, and has better Structural reliability.

A method of fabricating a display panel of the present invention includes the following steps. Forming at least one active component on a first substrate, wherein the first substrate is divided into at least one pixel region, and the active component is located in the pixel region and has a source and a drain. Forming a first insulating layer on the first substrate and covering the active device. Forming at least one color filter pattern on the first insulating layer, and the color filter pattern exposes a portion of the first insulating layer above the drain. A protective layer is formed on the color filter pattern, and the protective layer covers a portion of the first insulating layer exposed above the drain by the color filter pattern and the color filter pattern. A second insulating layer is formed on the protective layer, and the second insulating layer covers the protective layer, wherein the etching rate of the protective layer is lower than the etching rate of the second insulating layer. Performing a patterning process on the second insulating layer to expose a portion of the drain of the active device and a portion of the protective layer to form a patterned insulating layer, wherein the patterned insulating layer has a plurality of strip structures corresponding to the pixel regions And having at least one groove between each two adjacent strip structures, and the groove exposes a portion of the protective layer. Forming a pixel electrode on the patterned insulating layer, wherein the pixel electrode is a strip electrode and covering the strip structure and the groove of the patterned insulating layer, and is convex according to the strip structure to form a plurality of strip electrodes And the pixel electrode is connected to a portion of the drain of the active component exposed by the patterned insulating layer. A second substrate is assembled with the first substrate, wherein a common electrode corresponding to the pixel electrode is formed on the second substrate, and a display medium layer is disposed between the pixel electrode and the common electrode.

In an embodiment of the invention, the patterning process is performed on the second insulating layer, and the step of forming the patterned insulating layer includes: forming a first patterned photoresist layer on the second insulating layer, the first pattern The photoresist layer exposes the color in the pixel area a portion of the second insulating layer on the color filter pattern and a portion of the second insulating layer above the drain: the first patterned photoresist layer is a first etching mask, and is etched to expose the color filter in the pixel region a portion of the protective layer on the light pattern and a portion of the protective layer above the drain; removing the first patterned photoresist layer to expose the second insulating layer, and the second insulating layer has a strip structure corresponding to the pixel region And having a groove between each two adjacent strip structures to expose a portion of the protective layer; forming a second patterned photoresist layer on the second insulating layer exposed after removing the first patterned photoresist layer The second patterned photoresist layer exposes a portion of the protective layer above the drain; the second patterned photoresist layer is a second etch mask, etched to expose a portion of the drain; and the second pattern is removed Photoresist layer.

In an embodiment of the invention, the patterning process is performed on the second insulating layer, and the step of forming the patterned insulating layer includes: forming a first patterned photoresist layer on the second insulating layer, the first pattern The photoresist layer exposes a portion of the second insulating layer above the source; the first patterned photoresist layer is a first etching mask, etched to expose a portion of the drain; and the first patterned photoresist layer is removed And exposing the second insulating layer; forming a second patterned photoresist layer on the second insulating layer exposed after removing the first patterned photoresist layer, and the second patterned photoresist layer is exposed to the a second insulating layer on the color filter pattern of the prime region; the second patterned photoresist layer is a second etching mask, and is etched to expose a portion of the protective layer on the color filter pattern located in the pixel region; And removing the second patterned photoresist layer to expose the second insulating layer, and the second insulating layer has a strip structure corresponding to the pixel region and a groove between each two adjacent strip structures to expose Part of the protective layer.

In an embodiment of the invention, the patterning process is performed on the second insulating layer, and the step of forming the patterned insulating layer includes: forming a photoresist layer on the second insulating layer, and the photoresist layer covering the second insulating layer a layer; providing a half-tone mask on the photoresist layer, and performing a developing process to expose a portion of the photoresist layer on the color filter pattern of the pixel region and a portion of the second insulating layer above the drain; Using a photoresist layer as an etching mask, etching to expose a portion of the protective layer and a portion of the drain layer on the color filter pattern of the pixel region; and removing the photoresist layer to expose the second insulating layer, and The two insulating layers have a strip structure corresponding to the pixel regions and a groove between each two adjacent strip structures to expose a portion of the protective layer.

In an embodiment of the invention, the protective layer has a thickness between about 0.01 microns and 0.3 microns, and the second insulating layer has a thickness between about 0.1 microns and 0.5 microns.

In an embodiment of the invention, the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride.

In an embodiment of the invention, the material of the second insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide.

In an embodiment of the invention, the first substrate further defines a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad region has at least one pad. The peripheral region has at least one transition line structure, wherein the step of forming the transition line structure comprises: simultaneously forming a first metal layer and an insulation layer when forming a gate of the active device, a gate insulating layer, a source and a drain And a second metal layer in the peripheral region, wherein the first metal layer and the gate are in the same film layer, and the insulating layer and the gate insulating layer are The same film layer is located between the first metal layer and the second metal layer, and the second metal layer is the same film layer as the source and the drain; when the first insulating layer is formed, the first insulating layer covers the active device and the first a metal layer and a second metal layer; when the second insulating layer is patterned, the patterned insulating layer exposes the first metal layer and the second metal layer; and when an electrode layer is formed on the patterned insulating layer, The electrode layer connects the first metal layer and the second metal layer exposed by the patterned conductive layer to form a transition line structure.

A method of fabricating a display panel of the present invention includes the following steps. Forming at least one active component on a first substrate, wherein the first substrate is divided into at least one pixel region, and the active component is located in the pixel region and has a source and a drain. A protective layer is formed on the first substrate, and the protective layer covers the active device. An insulating layer is formed on the protective layer, and the insulating layer covers the protective layer, wherein the etching rate of the protective layer is lower than the etching rate of the insulating layer. Performing a patterning process on the insulating layer to expose a portion of the drain of the active device and a portion of the protective layer to form a patterned insulating layer, wherein the patterned insulating layer has a plurality of strip structures corresponding to the pixel regions, and There is at least one groove between each two adjacent strip structures, and the groove exposes a portion of the protective layer. Forming a pixel electrode on the patterned insulating layer, the pixel electrode is a strip electrode and covering the strip structure and the groove of the patterned insulating layer, and protruding according to the strip structure to form a plurality of strip electrodes, And the pixel electrode is connected to a portion of the drain of the active component exposed by the patterned insulating layer. A second substrate is assembled with the first substrate, wherein a common electrode corresponding to the pixel electrode is formed on the second substrate, and a display medium layer is disposed between the pixel electrode and the common electrode.

In an embodiment of the invention, the patterning process of the insulating layer is performed. The step of forming the patterned insulating layer includes: forming a first patterned photoresist layer on the insulating layer, the first patterned photoresist layer exposing the plurality of first portions and the plurality of second portions of the insulating layer, wherein An orthographic projection of the first portion of the insulating layer on the first substrate does not overlap the orthographic projection of the active device on the first substrate, and an orthographic projection of the second portion of the insulating layer on the first substrate overlaps the drain on the first substrate The front projection; the first patterned photoresist layer is a first etching mask, etched to expose a portion of the protective layer; the first patterned photoresist layer is removed to expose the insulating layer, and the insulating layer has a corresponding a strip structure disposed in the pixel region and a groove between each two adjacent strip structures to expose a portion of the protective layer; forming a second patterned photoresist layer after removing the first patterned photoresist layer Exposing the protective layer, the second patterned photoresist layer exposing the plurality of third portions of the protective layer, wherein the orthographic projection portion of the third portion of the protective layer on the first substrate overlaps the drain on the first substrate Orthographic projection; second patterned photoresist As a second etching mask, etching to expose part of the drain electrode of the active device; and removing the second patterned photoresist layer.

In an embodiment of the invention, the patterning process is performed on the insulating layer, and the step of forming the patterned insulating layer includes: forming a first patterned photoresist layer on the insulating layer, the first patterned photoresist layer Exposing a plurality of first portions of the insulating layer, wherein the orthographic projection of the first portion of the insulating layer on the first substrate overlaps the orthographic projection of the drain on the first substrate; the first patterned photoresist layer is first Etching the mask to etch to expose a portion of the drain of the active device; removing the first patterned photoresist layer to expose the insulating layer; forming a second patterned photoresist layer to remove the first patterned photoresist layer On the subsequent insulating layer, the second patterned photoresist layer exposes a plurality of second layers of the insulating layer a portion, wherein the orthographic projection of the second portion of the insulating layer on the first substrate does not overlap the orthographic projection of the active device on the first substrate; and the second patterned photoresist layer is a second etching mask, etched to be exposed a portion of the protective layer; and removing the second patterned photoresist layer to form a patterned insulating layer, wherein the patterned insulating layer has a strip structure corresponding to the pixel region and a concave between each adjacent strip structure Slot to expose a portion of the protective layer.

In an embodiment of the invention, the step of patterning the insulating layer, the step of forming the patterned insulating layer comprises: forming a photoresist layer on the insulating layer, the photoresist layer covering the insulating layer; providing half-tone light Covering the photoresist layer and performing a display process to expose the plurality of first portions and the plurality of second portions of the insulating layer, wherein the orthographic projection of the first portion of the insulating layer on the first substrate does not overlap the active device An orthographic projection on the first substrate, and the orthographic projection of the second portion of the insulating layer on the first substrate overlaps the orthographic projection of the active device on the first substrate; the photoresist layer is an etch mask, etched to be exposed a portion of the protective layer and a portion of the drain; and removing the photoresist layer to form a patterned insulating layer, wherein the patterned insulating layer has a strip structure corresponding to the pixel region and a recess between each adjacent strip structure Slot to expose a portion of the protective layer.

In an embodiment of the invention, the etching rate ratio of the protective layer to the insulating layer is about 1:3.

In an embodiment of the invention, the protective layer has a thickness of between about 0.01 micrometers and about 0.3 micrometers, and the insulating layer has a thickness of between about 0.1 micrometers and about 0.5 micrometers.

In an embodiment of the invention, the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride.

In an embodiment of the invention, the material of the insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide.

In an embodiment of the invention, the first substrate further has a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad region has at least one pad, and the peripheral region has At least one transition structure, wherein the step of forming the transition structure comprises: forming a first metal layer, an insulation layer, and a first layer when forming a gate, a gate insulating layer, a source and a drain of the active device The second metal layer is in the peripheral region, wherein the first metal layer and the gate are the same film layer, and the insulating layer and the gate insulating layer belong to the same film layer and are located between the first metal layer and the second metal layer, and the second metal layer and The source and the drain are the same film layer; when the protective layer is formed, the protective layer covers the active device and the first metal layer and the second metal layer simultaneously; when the insulating layer is patterned, the patterned insulating layer is exposed first The metal layer and the second metal layer; and when forming an electrode layer on the patterned insulating layer, the electrode layer connects the first metal layer and the second metal layer exposed by the patterned conductive layer to form a transition line structure.

The display panel of the present invention includes a first substrate, at least one active component, a first insulating layer, at least one color filter pattern, a protective layer, a patterned insulating layer, a pixel electrode, and a second substrate. a common electrode and a display medium layer. The first substrate is distinguished by at least one pixel region. The active component is located in the pixel area and has a source and a drain. The first insulating layer is disposed on the first substrate and covers the active device, wherein the first insulating layer has at least one first opening, and the first opening is exposed Part of the active element is bungee. The color filter pattern is disposed on the first insulating layer, wherein the color filter pattern exposes a portion of the first insulating layer on the drain. The protective layer is disposed on the color filter pattern and covers a portion of the first insulating layer on the drain exposed by the color filter pattern and the color filter pattern. The protective layer has at least one second opening, and the second opening communicates with the first opening and exposes a portion of the drain of the active component. The patterned insulating layer is disposed on the protective layer, has a plurality of strip structures corresponding to the pixel regions, and has at least one groove between each two adjacent strip structures, and the groove exposes a part of the protective layer, wherein the strips are The structure is located on the color filter pattern, and the orthographic projection of the strip structure on the first substrate does not overlap the orthographic projection of the active component on the first substrate. The patterned insulating layer has at least one third opening that communicates with the second opening and the first opening and exposes a portion of the drain of the active component. The pixel electrode is disposed on the patterned insulating layer, wherein the pixel electrode is a strip electrode and covers the strip structure and the groove of the patterned insulating layer, and is convex according to the strip structure to form a plurality of strip electrodes, And the pixel electrode is connected to the drain of the active device through the third opening, the second opening and the first opening. The second substrate is disposed opposite to the first substrate. The common electrode is disposed on the second substrate. The display medium layer is disposed between the first substrate and the second substrate, wherein the common electrode and the pixel electrode are located on opposite sides of the display medium layer.

In an embodiment of the invention, the first substrate further has a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad region has at least one pad, and the peripheral region has At least one turn structure. The transfer structure includes a first metal layer, a second metal layer, a first insulating layer extending between the first metal layer and the second metal layer, and a protection extending over the peripheral region and covering the first insulating layer a layer, a patterned insulating layer, and an electrode layer. The first insulating layer, the protective layer and the patterned insulating layer respectively have a plurality of first sub-openings, a plurality of second sub-openings and a plurality of third sub-openings. The third sub-opening communicates with the second sub-opening and the first sub-opening, and the electrode layer communicates with the first metal layer and the second metal layer through the third sub-opening, the second sub-opening and the first sub-opening.

In an embodiment of the invention, the protective layer has a thickness between about 0.01 microns and 0.3 microns, and the second insulating layer has a thickness between about 0.1 microns and 0.5 microns.

In an embodiment of the invention, the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride.

In an embodiment of the invention, the material of the second insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide.

The display panel of the present invention comprises a first substrate, at least one active component, a protective layer, a patterned insulating layer, a pixel electrode, a second substrate, a common electrode and a display dielectric layer. The first substrate is distinguished by at least one pixel region. The active component is located in the pixel area and has a source and a drain. The protective layer is disposed on the first substrate and covers the active component, wherein the protective layer has at least one first opening, and the first opening exposes a portion of the drain of the active component. The patterned insulating layer is disposed on the protective layer and has a plurality of strip structures corresponding to the pixel regions. Having at least one groove between each two adjacent strip structures, the groove exposing a portion of the protective layer, wherein the orthographic projection of the strip structure on the first substrate does not overlap the orthographic projection of the active device on the first substrate, and The patterned insulating layer has at least one second opening, and the second opening communicates with the first opening And exposing part of the pole of the active component. The pixel electrode is disposed on the patterned insulating layer, wherein the pixel electrode is a strip electrode and covers the strip structure and the groove of the patterned insulating layer, and is convex according to the strip structure to form a plurality of strip electrodes. The pixel electrode is connected to a portion of the drain of the active device through the second opening and the first opening. The second substrate is disposed opposite to the first substrate. The common electrode is disposed on the second substrate. The display medium layer is disposed between the first substrate and the second substrate, wherein the common electrode and the pixel electrode are located on opposite sides of the display medium layer.

In an embodiment of the invention, the first substrate further has a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad region has at least one pad, and the peripheral region has At least one turn structure. The transfer structure includes a first metal layer, a second metal layer, a gate insulating layer extending between the first metal layer and the second metal layer, and a protective layer extending over the peripheral region and covering the second metal layer. A patterned insulating layer and an electrode layer. The protective layer and the patterned insulating layer respectively have a plurality of first sub-openings and a plurality of second sub-openings, the second sub-opening communicates with the first sub-opening, and the electrode layer communicates with the first sub-opening through the second sub-opening a layer and a second metal layer.

In an embodiment of the invention, the protective layer has a thickness of between about 0.01 micrometers and about 0.3 micrometers, and the insulating layer has a thickness of between about 0.1 micrometers and about 0.5 micrometers.

In an embodiment of the invention, the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride.

In an embodiment of the invention, the material of the insulating layer comprises nitriding Niobium, niobium oxynitride, aluminum oxide or yttrium aluminum oxide.

Based on the above, in the method of fabricating the display panel of the present invention, a protective layer is formed on the color filter pattern, and the etching rate of the protective layer is lower than the etching rate of the second insulating layer. Therefore, in the process of patterning the second insulating layer, the color filter pattern can be effectively protected by the protective layer, which can improve the fabrication yield and structural reliability of the overall display panel.

The above described features and advantages of the invention will be apparent from the following description.

10a, 10b‧‧‧ display panel

110‧‧‧First substrate

112‧‧‧ inner surface

120‧‧‧First insulation

130‧‧‧Color filter pattern

140, 140’‧‧‧ protective layer

150, 150', 150''‧‧‧ second insulation

150a‧‧‧patterned insulation

152‧‧‧ strip structure

154‧‧‧ Groove

160‧‧‧ pixel electrodes

162‧‧‧ strip electrodes

170, 170'‧‧‧Insulation

172‧‧‧ strip structure

174‧‧‧ Groove

180‧‧‧pixel electrodes

182‧‧‧ strip electrodes

210‧‧‧second substrate

220‧‧‧Common electrode

300‧‧‧Display media layer

Part A‧‧‧

C‧‧‧ channel layer

D‧‧‧汲

EL, EL'‧‧‧ electrode layer

G‧‧‧ gate

GI‧‧‧ brake insulation

I‧‧‧Insulation

M1, M11, M4, M44‧‧‧ first mask pattern

M2, M22, M5‧‧‧ second mask pattern

M3, M6‧‧‧ half-tone mask

ML1‧‧‧ first metal layer

ML2‧‧‧ second metal layer

O1, O1', T1, T1'‧‧‧ first opening

O2, O2’, T2, T2’‧‧‧ second opening

O3, O3’‧‧‧ third opening

P1, P11‧‧‧ pixel area

P1’, P11’, P111’‧‧‧ first part

P2, P22‧‧‧ surrounding area

P2’, P22’, P222’‧‧‧ Part II

P3’‧‧‧Part III

PR1, PR3‧‧‧ first photoresist layer

PR1', PR11, PR3', PR33‧‧‧ first patterned photoresist layer

PR2, PR4‧‧‧ second photoresist layer

PR2', PR22, PR4', PR44‧‧‧ second patterned photoresist layer

S‧‧‧ source

T‧‧‧ active components

TS, TS’‧‧‧Transfer structure

1A and FIG. 1B are respectively top plan views of a pixel region and a peripheral region on a first substrate of a display panel according to an embodiment of the invention.

2A to 2M are schematic cross-sectional views showing a method of fabricating a display panel taken along line II' of FIG. 1A and line II-II' of FIG. 1B.

2N is a perspective view showing a partial layer of a pixel region on the first substrate of FIG. 2M.

FIG. 2O is a cross-sectional view of a display panel according to an embodiment of the invention.

3A-3D are cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the present invention.

4A-4B illustrate a display panel according to another embodiment of the present invention. A schematic cross-sectional view of a partial step of the fabrication process.

5A and FIG. 5B are schematic top views of a pixel region and a peripheral region on a first substrate of a display panel according to another embodiment of the invention.

6A to 6J are schematic cross-sectional views showing a method of fabricating a display panel along line III-III' of FIG. 5A and line IV-IV' of FIG. 5B.

FIG. 6K is a cross-sectional view showing a display panel according to another embodiment of the present invention.

7A-7D are cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the present invention.

8A-8B are schematic cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the invention.

1A and FIG. 1B are respectively top plan views of a pixel region and a peripheral region on a first substrate of a display panel according to an embodiment of the invention. 2A to 2M are schematic cross-sectional views showing a method of fabricating a display panel taken along line II' of FIG. 1A and line II-II' of FIG. 1B. 2N is a perspective view showing a partial layer of a pixel region on the first substrate of FIG. 2M. FIG. 2O is a cross-sectional view of a display panel according to an embodiment of the invention. For convenience of explanation, some of the members are omitted in FIGS. 2N and 2O. Referring to FIG. 1A, FIG. 1B and FIG. 2A simultaneously, in accordance with the method for fabricating a display panel of the present embodiment, first, at least one active device T is formed on a first substrate 110, wherein the first substrate 110 is distinguished by at least one pixel. Area P1. Here, the first base The board 110 is, for example, a glass substrate or a plastic substrate. As shown in FIG. 2A, the active device T of the present embodiment includes a gate G, a gate insulating layer GI, a channel layer C, a source S, and a drain D. The gate G is disposed on the first substrate 110. The gate insulating layer GI covers the gate G and an inner surface 112 of the first substrate 110, and the channel layer C is disposed on one side of the gate insulating layer GI, and the source S and the drain D are separated from each other and disposed in the channel layer. C is located on opposite sides of the gate G. Here, the active device T is, for example, a bottom gate type thin film transistor. Of course, in other embodiments not shown, the active device T may also be a top gate type thin film transistor, a multi-gate type thin film transistor or other suitable thin film transistor. Furthermore, the material of the channel layer C may comprise amorphous germanium, polycrystalline germanium, microcrystalline germanium, an oxide semiconductor, an organic semiconductor or other suitable semiconductor material, which is not limited herein.

Referring to FIG. 1A, FIG. 1B and FIG. 2A, the first substrate 110 of the embodiment further distinguishes a peripheral region P2 electrically connected to the pixel region P1 and a pad region connected to the peripheral region P2 (not shown). Wherein the pad region has at least one pad (not shown), and the peripheral region P2 has at least one transition structure TS (please refer to FIG. 2M), that is, the peripheral region P2 is located in the pixel region P1 and the pad region ( Between the two, the pad area (not shown) will be closest to the edge of the first substrate 110. Therefore, one end of the pad (not shown) is connected to one end of the transfer line structure TS, and the other end of the pad (not shown) is connected to an external circuit (not shown) other than the pixel area P1, including A driving circuit (not shown), a circuit chip (not shown), a circuit board (not shown) or other suitable circuit. In detail, when the gate G of the active device T, the gate insulating layer GI, the source S and the drain D are formed, a first metal layer ML1, an insulating layer I and a second metal layer ML2 are simultaneously formed. District P2, The first metal layer ML1 and the gate G belong to the same film layer, and the insulating layer I and the gate insulating layer GI belong to the same film layer and are located between the first metal layer ML1 and the second metal layer ML2, and the second metal layer ML2 and Source S and drain D belong to the same film layer. In addition, the gate G is connected to a scan line (also referred to as a gate line, not shown), and the source S is connected to a data line (or called a signal line, not shown). Therefore, the transfer structure TS is The other end is not connected to the gate line (not shown) or connected to the data line (not shown). In this embodiment, the source S is directly connected to the data line as an example, and the source S is also connected to the data line through the conductive layer. Wherein, the first metal layer ML1 is separated from the gate G, and the above does not contact each other; the second metal layer ML2 is separated from the source/drain S/D, and the above does not contact each other; The metal layer ML1 is separated from the second metal layer ML2, and the above does not contact each other.

Next, referring to FIG. 2B, a first insulating layer 120 is formed on the first substrate 110 and covers the active device T. When the first insulating layer 120 is formed, the first insulating layer 120 covers the active device T and the periphery. The first metal layer ML1 and the second metal layer ML2 of the region P2. Next, at least one color filter pattern 130 is formed on the first insulating layer 120, wherein the color filter pattern 130 exposes a portion of the first insulating layer 120 above the drain D of the active device T. In the peripheral region P2, the color filter pattern 130 exposes a portion of the first insulating layer 120 over the second metal layer ML2 and a portion of the first insulating layer 120 over the first metal layer ML1. Of course, in other embodiments not shown, the color filter pattern exposes a portion of the first insulating layer above the source of the active device, which is not limited herein. As shown in FIG. 2B, the color filter pattern 130 of the embodiment is illustrated as a plurality, wherein the color filter pattern 130 is, for example, Forming a red filter pattern, a blue filter pattern, and a green filter pattern; or a red filter pattern, a blue filter pattern, a green filter pattern, and a fourth color filter pattern, No restrictions. The fourth color filter pattern includes a transparent filter pattern (also referred to as a white filter pattern), a yellow filter pattern, or a color on other color coordinates.

Next, referring to FIG. 2C, a protective layer 140 is formed on the color filter pattern 130, wherein the protective layer 140 covers the first insulating layer 120 exposed above the gate D by the color filter pattern 130 and the color filter pattern 130. . In the peripheral region P2, the protective layer 140 is formed on the color filter pattern 130, wherein the protective layer 140 covers a portion of the first insulating layer exposed by the color filter pattern 130 and the color filter pattern 130 above the second metal layer ML2. 120 and a portion of the first insulating layer 120 over the first metal layer ML1. It should be noted that the thickness of the protective layer 140 of the present embodiment is preferably between about 0.01 micrometers and 0.3 micrometers, and the material of the protective layer 140 is, for example, cerium oxide (SiO _x ) or cerium oxynitride (SiON). ), aluminum nitride (AlN _x ) or yttrium aluminum nitride (SiAlN _x ).

Next, referring to FIG. 2D , a second insulating layer 150 is formed on the protective layer 140 , wherein the second insulating layer 150 covers the protective layer 140 . In the peripheral region P2, the second insulating layer 150 is formed on the protective layer 140, wherein the second insulating layer 150 covers the protective layer 140. Wherein, the etching rate of the protective layer 140 is substantially lower than the etching rate of the second insulating layer 150. Preferably, the etching rate ratio of the protective layer 140 to the second insulating layer 150 is about 1:3. Here, the thickness of the second insulating layer 150 is preferably between about 0.1 micrometers and 0.5 micrometers, and the material of the second insulating layer 150 is, for example, tantalum nitride (SiN _x ) or cerium oxynitride (SiON). , aluminum oxide (AlO _x ) or yttrium aluminum oxide (SiAlO _x ). More specifically, in order to satisfy the condition that the etching rate ratio of the protective layer 140 and the second insulating layer 150 is about 1:3, the materials of the protective layer 140 and the second insulating layer 150 are substantially different, for example, when protecting Preferably, when the material of the layer 140 is yttrium oxide, the material of the second insulating layer 150 is selected from tantalum nitride or hafnium oxynitride; when the material of the protective layer 140 is selected from yttrium oxynitride, preferably, second. The material of the insulating layer 150 should be selected from tantalum nitride; when the material of the protective layer 140 is selected from aluminum nitride, preferably, the material of the second insulating layer 150 should be alumina; when the material of the protective layer 140 is selected to be nitrided Preferably, the material of the second insulating layer 150 is selected from yttrium aluminum oxide.

Next, referring to FIG. 2E, a patterning process is performed on the second insulating layer 150. First, a first photoresist layer PR1 is formed on the second insulating layer 150, wherein the first photoresist layer PR1 covers the second insulating layer 150. . In the peripheral region P2, the first photoresist layer PR1 is formed on the second insulating layer 150, wherein the first photoresist layer PR1 covers the second insulating layer 150.

Next, referring to FIG. 2F, a first mask pattern M1 is provided on the first photoresist layer PR1, and an exposure and development process is performed to form a first patterned photoresist layer PR1'. Here, the first patterned photoresist layer PR1' is formed on the second insulating layer 150, and the first patterned photoresist layer PR1' exposes a portion of the second insulation on the color filter pattern 130 of the pixel region P1. Layer 150 and a portion of second insulating layer 150 above drain D. In the peripheral region P2, the first patterned photoresist layer PR1' exposes a portion of the second insulating layer 150 above the second metal layer ML2 and a portion of the second insulating layer 150 over the first metal layer ML1.

Next, referring to FIG. 2G, the first patterned photoresist layer PR1' is a first etching mask, and is dry etched to expose the color filter pattern 130 located in the pixel region P1. A portion of the upper protective layer 140 and a portion of the protective layer 140 above the drain D. In the peripheral region P2, the first patterned photoresist layer PR1' is a first etching mask, dry etching to expose a portion of the protective layer 140 above the second metal layer ML2 and a portion above the first metal layer ML1. Protective layer 140.

Next, referring to FIG. 2H, the first patterned photoresist layer PR1' is removed to expose the second insulating layer 150'. At this time, as shown in FIG. 2H, the second insulating layer 150' has a strip structure 152 disposed corresponding to the pixel region P1 and a groove 154 between each two adjacent strip structures 152 to expose a portion of the protective layer 140. . In the peripheral region P2, the first patterned photoresist layer PR1' is removed to expose the second insulating layer 150'.

Next, referring to FIG. 2I, a second photoresist layer PR2 is formed on the second insulating layer 150' exposed after removing the first patterned photoresist layer PR1', wherein the second photoresist layer PR2 covers the second layer. The strip structure 152 of the insulating layer 150' and the recess 154 and a portion of the protective layer 140 that is exposed and located above the drain D. In the peripheral region P2, a second photoresist layer PR2 is formed on the second insulating layer 150' exposed after removing the first patterned photoresist layer PR1', wherein the second photoresist layer PR2 covers the second insulation. A portion of the protective layer 140 over the first metal layer ML1 and the second metal layer ML2 is exposed on the layer 150' and by the second insulating layer 150'.

Next, referring to FIG. 2J, a second mask pattern M2 is provided on the second photoresist layer PR2, and an exposure and development process is performed to form a second patterned photoresist layer PR2'. At this time, the second patterned photoresist layer PR2 is formed on the second insulating layer 150' exposed after removing the first patterned photoresist layer PR1, and the second patterned photoresist layer PR2' is exposed at 汲A portion of the protective layer 140 above the pole D. That is It is said that in the pixel region P1, the second patterned photoresist layer PR2 exposes only a portion of the protective layer 140 located above the drain D. In the peripheral region P2, the second patterned photoresist layer PR2 is formed on the second insulating layer 150' exposed after removing the first patterned photoresist layer PR1, and the second patterned photoresist layer PR2' is exposed. A portion of the protective layer 140 is disposed above the first metal layer ML1 and the second metal layer ML2.

Next, referring to FIG. 2K, the second patterned photoresist layer PR2' is a second etching mask, and is dry etched to expose a portion of the drain D of the active device T. In the peripheral region P2, the second patterned photoresist layer PR2' is a second etching mask, and is dry etched to expose a portion of the first metal layer ML1 and a portion of the second metal layer ML2.

Next, referring to FIG. 2L, the second patterned photoresist layer PR2' is removed to form a patterned insulating layer 150a. At this time, as shown in FIGS. 1A and 2L, the patterned insulating layer 150a exposes a portion of the protective layer 140 located in the pixel region P1 and a portion of the drain D of the active device T and a portion of the first metal layer ML1 located in the peripheral region P2. And a portion of the second metal layer ML2. Here, the patterned insulating layer 150a has a strip structure 152 disposed corresponding to the pixel region P1, and a groove 154 is formed between each two adjacent strip structures 152, and the recess 154 exposes a portion of the protective layer 140.

1A, 1B, 2M, and 2N, a pixel electrode 160 is formed on the patterned insulating layer 150a, wherein the pixel electrode 160 is a strip electrode (also referred to as a flat electrode, also That is, there are no openings, grooves, slits or patterns in or on the pixel electrode 160 and cover the strip structure 152 and the groove 154 of the patterned insulating layer 150a, and are convex according to the strip structure 152 to form a plurality of Strip electrodes 162, and the pixel electrode 160 is connected to the active exposed by the patterned insulating layer 150a Part of the pole D of the component T. At this time, in the peripheral region P2, when an electrode layer EL is formed on the patterned insulating layer 150a, the electrode layer EL is connected to the first metal layer ML1 and the second metal layer ML2 exposed by the patterned conductive layer 150a. The transition line structure TS is formed. Here, the pixel electrode 160 and the electrode layer EL belong to the same film layer, but are separated from each other and do not contact each other. So far, the fabrication of the components on the first substrate 110 has been completed.

Finally, referring to FIG. 2O, a second substrate 210 is assembled with the first substrate 110. The common electrode 220 corresponding to the pixel electrode 160 is formed on the second substrate 210, and is disposed on the pixel electrode 160 and the common electrode 220. A display medium layer 300 is disposed between, for example, a liquid crystal material. So far, the production of the display panel 10a has been completed.

It should be noted that this embodiment does not limit the method of fabricating the patterned insulating layer 150a. 3A-3D are cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the present invention. The method for fabricating the patterned insulating layer 150a of the present embodiment is similar to that of the previous embodiment, except that after the step of FIG. 2E, the first photoresist layer PR1 is formed on the second insulating layer 150, wherein the first After the photoresist layer PR1 covers the second insulating layer 150, please refer to FIG. 3A, a first mask pattern M11 is provided on the first photoresist layer PR1, and an exposure and development process is performed to form a first patterned photoresist. Layer PR11. At this time, the first patterned photoresist layer PR11 is formed on the second insulating layer 150, and the first patterned photoresist layer PR11 exposes a portion of the second insulating layer 150 located above the drain D. In the peripheral region P2, the first patterned photoresist layer PR11 exposes a portion of the second insulating layer 150 above the second metal layer ML2 and a portion of the second insulating layer 150 over the first metal layer ML1.

Next, referring to FIG. 3B, the first patterned photoresist layer PR11 is a first etching mask, and is etched to expose a portion of the drain D. That is, the first patterned photoresist layer PR11 exposes only the drain D located in the pixel region P1. In the peripheral region P2, the first patterned photoresist layer PR11 is a first etching mask, and is dry etched to expose a portion of the second metal layer ML2 and a portion of the first metal layer ML1. Next, referring to FIG. 3C, the first patterned photoresist layer PR11 is removed to expose the second insulating layer 150''. Next, referring to FIG. 3D, a second patterned photoresist layer PR22 is formed on the second insulating layer 150'' exposed after removing the first patterned photoresist layer PR11, wherein the second patterned photoresist layer The PR22 exposes a portion of the second insulating layer 150" on the color filter pattern 130 of the pixel region P1, that is, the second patterned photoresist layer PR22 covers the exposed portion of the drain D. In the peripheral region P2, The second patterned photoresist layer PR22 covers a portion of the exposed second metal layer ML2 and a portion of the first metal layer ML1. Here, the second patterned photoresist layer PR22 is formed by transmitting a second light therethrough. The mask pattern M22 is formed by a process of exposing and developing the photoresist. Then, the second patterned photoresist layer PR22 is a second etching mask, and is etched to expose the color filter pattern 130 located in the pixel region P1. The upper portion of the protective layer 140 is removed, and the second patterned photoresist layer PR22 is removed to form the patterned insulating layer 150a of FIG. 2L.

Alternatively, FIG. 4A to FIG. 4B are schematic cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the present invention. After the step of FIG. 2E, the photoresist layer PR1 is formed on the second insulating layer 150. After the photoresist layer PR1 covers the second insulating layer 150, please refer to FIG. 4A to provide a half-tone mask M3. On the photoresist layer PR1, and performing a developing process to expose the presence A portion A of the photoresist layer PR1 on the color filter pattern 130 of the pixel region P1 and a portion of the second insulating layer 150 above the gate D. The portion A has a thick region corresponding to the remaining portion of the patterned insulating layer 150a, and a thin portion corresponding to the removed portion of the patterned insulating layer 150a for forming the stripe described by the patterned insulating layer 150a. Structure 152 and recess 154. Wherein the thickness of the thin region is smaller than the thickness of the thick region, and there is no photoresist on the portion of the second insulating layer 150 above the drain D. In the peripheral region P2, the photoresist layer PR1 exposes a portion of the second insulating layer 150 above the second metal layer ML2 and a portion of the second insulating layer 150 over the first metal layer ML1. The photoresist layer PR1 is next, referring to FIG. 4B, the photoresist layer PR1 is an etching mask, and is dry-etched to expose a portion of the protective layer 140 and a portion of the drain D on the color filter pattern 130 of the pixel region P1. In the peripheral region P2, the photoresist layer PR1 is used as an etching mask, and is dry etched to expose a portion of the first metal layer ML1 and a portion of the second metal layer ML2. Thereafter, the photoresist layer PR1 is removed to form the patterned insulating layer 150a of FIG. 2L.

Referring to FIG. 1A, FIG. 1B, FIG. 2M and FIG. 2O simultaneously, the display panel 10a includes a first substrate 110, an active device T, a first insulating layer 120, a color filter pattern 130, a protective layer 140, and a pattern. The insulating layer 150a, the pixel electrode 160, the second substrate 210, the common electrode 220, and the display medium layer 300. The first substrate 110 is divided into a pixel region P1, and the active device T is located in the pixel region P1 and has a source S and a drain D. The first insulating layer 120 is disposed on the first substrate 110 and covers the active device T. The first insulating layer 120 has at least one first opening O1, and the first opening O1 exposes a portion of the drain D of the active device T, respectively. The color filter pattern 130 is disposed on the first insulating layer 120, wherein the color filter pattern 130 is exposed A portion of the first insulating layer 120 above the drain D. The protective layer 140 is disposed on the color filter pattern 130 and covers the first insulating layer 120 of the color filter pattern 130 and the color filter pattern 130 exposed above the drain D. The protective layer 140 has at least one second opening O2, and the second opening O2 communicates with the first opening O1 and exposes a portion of the drain D of the active device T.

Moreover, the patterned insulating layer 150a is disposed on the protective layer 140, has a plurality of strip structures 152 disposed corresponding to the pixel regions P1, and has a groove 154 between each two adjacent strip structures 152, and the grooves 154 A portion of the protective layer 140 is exposed, wherein the strip structure 152 is located on the color filter pattern 130, and the orthographic projection of the strip structure 152 on the first substrate 110 does not overlap the orthographic projection of the active device T on the first substrate 110. The patterned insulating layer 150a has at least one third opening O3 that communicates with the second opening O1 and the first opening O2 and exposes a portion of the drain D of the active device T. The pixel electrode 160 is disposed on the patterned insulating layer 150a, wherein the pixel electrode 160 is a bulk electrode (also referred to as a flat electrode, that is, there are no openings, grooves, or slits in or on the pixel electrode 160. Or patterning and covering the strip structure 152 of the patterned insulating layer 150a and the recess 154, and protruding according to the strip structure 152 to form a plurality of strip electrodes 162, and the pixel electrode 160 passes through the third opening O3, The two openings O1 and the first opening O2 are connected to the drain D of the active element T. The second substrate 210 is disposed opposite to the first substrate 110 . The common electrode 220 is disposed on the second substrate 210. The display medium layer 300 is disposed between the first substrate 110 and the second substrate 210, wherein the common electrode 220 and the pixel electrode 160 are located on the display medium layer 300, for example, opposite sides of the liquid crystal material.

In addition, the first substrate 110 of the embodiment further distinguishes the peripheral region P2 electrically connected to the pixel region P1 and the pad region (not shown) connected to the peripheral region P2, wherein the pad region has at least one pad (not The peripheral area P2 has a transition structure TS. The peripheral area P2 is located between the pixel area P1 and the pad area (not shown), and the pad area (not shown) is closest to the edge of the first substrate 110. Therefore, one end of the pad (not shown) is connected to one end of the transfer line structure TS, and one end of the transfer line structure TS is not connected to the scan line or the data line, and the other end of the pad (not shown) is connected except An external circuit (not shown) other than the pixel area P1 includes a driving circuit (not shown), a circuit chip (not shown), a circuit board (not shown), or other suitable circuit. The transfer structure TS includes a first metal layer ML1, a second metal layer ML2, a first insulating layer 120 extending between the first metal layer ML1 and the second metal layer ML2, and an extension disposed in the peripheral region P2 and covering the first insulation. The protective layer 140 of the layer 120, the patterned insulating layer 150a, and the electrode layer EL. The first insulating layer 120, the protective layer 140, and the patterned insulating layer 150a have a plurality of first sub-openings O1', a plurality of second sub-openings O2', and a plurality of third sub-openings O3', respectively. The third sub-opening O3 ′ communicates with the second sub-opening O 2 ′ and the first sub-opening O 1 ′, and the electrode layer EL communicates with the first metal through the third sub-opening O 3 ′, the second sub-opening O 2 ′, and the first sub-opening O 1 ′ Layer ML1 and second metal layer ML2.

Referring to FIG. 2M again, since the color filter pattern 130 of the present embodiment has been covered by the protective layer 140 before the patterned insulating layer 150a is formed, the etching rate of the protective layer 140 is lower than the etching rate of the second insulating layer 150. . Therefore, during the etching process of forming the patterned insulating layer 150a, the color filter pattern 130 can be protected by the protective layer 140 to avoid etching erosion. In this way, the display panel 10a of the embodiment can be It has better process yield and structural reliability. In addition, since the first substrate 110 of the embodiment has the active device T and the color filter pattern 130, the first substrate 110 and the components thereon can be regarded as an active array integrated with a color filter layer pattern (Color Filter on Array, COA) substrate.

It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

5A and FIG. 5B are schematic top views of a pixel region and a peripheral region on a first substrate of a display panel according to another embodiment of the invention. 6A to 6J are schematic cross-sectional views showing a method of fabricating a display panel taken along line III-III' of FIG. 5A and line IV-IV' of FIG. 5B. FIG. 6K is a cross-sectional view showing a display panel according to another embodiment of the present invention. The manufacturing method of the display panel 10b of the present embodiment is similar to that of the display panel 10a of the foregoing embodiment, but the main difference is that there is no color filter pattern on the first substrate 110. Therefore, after the active device T is formed on the substrate 110 in FIG. 2A, please simultaneously refer to FIG. 5A, FIG. 5B and FIG. 6A to directly form a protective layer 140' on the first substrate 110, wherein the protective layer 140' is covered in the pixel region. The gate insulating layer GI, the channel layer C, the source S and the drain D of the active device T of P11. Preferably, the thickness of the protective layer 140' is, for example, between about 0.01 micrometers and 0.3 micrometers, and the material of the protective layer 140' is, for example, hafnium oxide, hafnium oxynitride, aluminum nitride or hafnium aluminum nitride. Here, the protective layer 140' also covers the first metal layer ML1 and the second metal layer ML2 located in the peripheral region P22.

Next, referring to FIG. 6B, an insulating layer 170 is formed on the protective layer 140', wherein the insulating layer 170 covers the protective layer 140', and the etching rate of the protective layer 140' is substantially lower than the etching rate of the insulating layer 170. Preferably, the etching rate ratio of the protective layer 140' to the insulating layer 170 is about 1:3. Here, the thickness of the insulating layer 170 is between about 0.1 micrometers and 0.5 micrometers, and the material of the insulating layer 170 is, for example, tantalum nitride, hafnium oxynitride, aluminum oxide or hafnium aluminum oxide. More specifically, in order to satisfy the condition that the etching rate ratio of the protective layer 140' and the insulating layer 170 is about 1:3, the materials of the protective layer 140 and the second insulating layer 150 are substantially different, for example, when the protective layer When the material of the 140' is selected to be tantalum oxide, preferably, the material of the insulating layer 170 is selected from tantalum nitride or tantalum oxynitride; when the material of the protective layer 140' is selected from yttrium oxynitride, preferably, the insulating layer 170 When the material of the protective layer 140' is selected from aluminum nitride, the material of the insulating layer 170 is preferably alumina; when the material of the protective layer 140' is selected from aluminum nitride. Preferably, the material of the insulating layer 170 is selected from yttrium aluminum oxide.

Next, referring to FIG. 6C, a patterning process is performed on the insulating layer 170. First, a first photoresist layer PR3 is formed on the insulating layer 170, wherein the first photoresist layer PR3 covers the insulating layer 170.

Next, referring to FIG. 6D, a first mask pattern M4 is provided on the first photoresist layer PR3, and an exposure and development process is performed to form a first patterned photoresist layer PR3'. The first patterned photoresist layer PR3 ′ is formed on the insulating layer 170 , and the first patterned photoresist layer PR3 exposes the plurality of first portions P1 ′ of the insulating layer 170 and the plurality of second portions P2 ′, wherein the insulating layer 170 The orthographic projection of the first portion P1' on the first substrate 110 does not overlap the orthographic projection of the active device T on the first substrate 110, The orthographic projection of the second portion P2' of the insulating layer 170 on the first substrate 110 overlaps the orthographic projection of the drain D on the first substrate 110. In the peripheral region P22, the first patterned photoresist layer PR3' exposes a portion of the insulating layer 170 above the second metal layer ML2, that is, the second portion P2' and a portion of the insulating layer 170 above the first metal layer ML1, that is, The second part is P2'.

Next, referring to FIG. 6E, the first patterned photoresist layer PR3' is an etch mask and etched to expose a portion of the protective layer 140'.

Next, referring to FIG. 6F, the first patterned photoresist layer PR3' is removed to expose the insulating layer 170', wherein the insulating layer 170' has a strip structure 172 corresponding to the pixel region P11 and every two adjacent strips. There are grooves 174 between the structures 172 to expose a portion of the protective layer 140'.

Next, referring to FIG. 6G, a second photoresist layer PR4 is formed on the insulating layer 170' exposed after removing the first patterned photoresist layer PR3', wherein the second photoresist layer PR4 covers the insulating layer 170'. The strip structure 172 and the recess 174 and the protective layer 140' exposed by the insulating layer 170'.

Next, referring to FIG. 6H, a second mask pattern M5 is provided on the second photoresist layer PR4, and an exposure and development process is performed to form a second patterned photoresist layer PR4'. The second patterned photoresist layer PR4 ′ is formed on the protective layer 140 ′ after the first patterned photoresist layer PR3 ′ is removed, wherein the second patterned photoresist layer PR 4 ′ exposes the protective layer 140 ′ The third portion P3 ′, and the orthographic projection of the third portion P3 ′ of the protective layer 140 ′ on the first substrate 110 overlaps the orthographic projection of the drain D on the first substrate 110 . In the peripheral region P22, the second patterned photoresist layer The PR4' exposes a portion of the protective layer 140' located above the second metal layer ML2, i.e., the third portion P3' and a portion of the protective layer 140' above the first metal layer ML1, i.e., the third portion P3'.

Next, referring to FIG. 6H and FIG. 6I, the second patterned photoresist layer PR4' is a second etching mask, and is etched to expose a portion of the drain D of the active device T. Thereafter, the second patterned photoresist layer PR4' is removed to form a patterned insulating layer 170a. Here, the patterned insulating layer 170a has a plurality of strip structures 172 disposed corresponding to the pixel regions P11, and each of the two adjacent strip structures 172 has a recess 174 therebetween, and the recess 174 exposes a portion of the protective layer 140' . In the peripheral region P22, the second patterned photoresist layer PR4' is a second etching mask, and is etched to expose a portion of the first metal layer ML1 and a portion of the second metal layer ML2. Thereafter, the second patterned photoresist layer PR4' is removed. As shown in FIG. 6I, the patterned insulating layer 170a of the present embodiment exposes a portion of the protective layer 140' located in the pixel region P11 and the drain D of the active device T and the first metal layer ML1 and the second portion located in the peripheral region P22. Metal layer ML2.

Thereafter, referring to FIG. 6J, a pixel electrode 180 is formed on the patterned insulating layer 170a, wherein the pixel electrode 180 is a strip electrode (also referred to as a flat electrode, that is, in the pixel electrode 160 or There are no openings, grooves, slits or patterns thereon and cover the strip structure 172 and the recess 174 of the patterned insulating layer 170a, and are convex according to the strip structure 172 to form a plurality of strip electrodes 182, and the pixels The electrode 180 is connected to the drain D of the active device T exposed by the patterned insulating layer 170a. As shown in FIG. 6J, the pixel electrode 180 does not cover the orthographic projection of the patterned insulating layer 170a on the substrate 110 and the orthographic projection of the gate G of the active device T on the substrate 110 completely overlaps. At the office. In addition, in the peripheral region P22, an electrode layer EL' is formed on the patterned insulating layer 170a, wherein the electrode layer EL1' is connected to the first metal layer ML1 and the second metal layer ML2 exposed by the patterned conductive layer 170a. The transition line structure TS' is formed. Here, the pixel electrode 180 and the electrode layer EL' belong to the same film layer, but are separated from each other and do not contact each other. Therefore, the first substrate 110 of the embodiment further distinguishes a peripheral region P22 electrically connected to the pixel region P11 and a pad region (not shown) connected to the peripheral region P22, wherein the pad region has at least one connection a pad (not shown), and the peripheral area P22 has at least one transition structure TS' (please refer to FIG. 6J), that is, the peripheral area P22 is located between the pixel area P11 and the pad area (not shown), and then The pad area (not shown) will be closest to the edge of the first substrate 110. Therefore, one end of the pad (not shown) is connected to one end of the wire structure TS', and the other end of the pad (not shown) is connected to an external circuit (not shown) other than the pixel area P11. It includes a driving circuit (not shown), a circuit chip (not shown), a circuit board (not shown) or other suitable circuit. Moreover, the gate G is connected to a scan line (or called a gate line, not shown), and the source S is connected to a data line (or called a signal line, not shown). Therefore, the transfer structure TS' The other end is not connected to the gate line (not shown) or connected to the data line (not shown). In this embodiment, the source S is directly connected to the data line as an example, and the source S is also connected to the data line through the conductive layer. Wherein, the first metal layer ML1 is separated from the gate G, and the above does not contact each other; the second metal layer ML2 is separated from the source/drain S/D, and the above does not contact each other; The metal layer ML1 is separated from the second metal layer ML2, and the above does not contact each other. So far, the fabrication of the components on the first substrate 110 has been completed. So far, the fabrication of the components on the first substrate 110 has been completed.

Finally, referring to FIG. 6K, a second substrate 210 is assembled with the first substrate 110. The common electrode 220 corresponding to the pixel electrode 180 is formed on the second substrate 210, and is disposed on the pixel electrode 180 and the common electrode 220. A display medium layer 300, such as a liquid crystal, is disposed therebetween. So far, the production of the display panel 10b has been completed.

It should be noted that this embodiment does not limit the method of forming the patterned insulating layer 170a. 7A-7D are cross-sectional views showing a partial step of a method of fabricating a display panel according to another embodiment of the present invention. The method for fabricating the patterned insulating layer 170a of the present embodiment is similar to that of the previous embodiment except that after the step of FIG. 6C, the first photoresist layer PR3 is formed on the insulating layer 170, wherein the first photoresist layer is formed. After the PR3 covers the insulating layer 170, a first mask pattern M44 is provided on the first photoresist layer PR3, and an exposure and development process is performed to form a first patterned photoresist layer PR33. At this time, the first patterned photoresist layer PR33 is formed on the insulating layer 170, and the first patterned photoresist layer PR33 exposes the plurality of first portions P11' of the insulating layer 170, wherein the first portion P11' of the insulating layer 170 is The orthographic projection on the first substrate 110 overlaps the orthographic projection of the drain D on the first substrate 110. In the peripheral region P22, the first patterned photoresist layer PR33 exposes a portion of the insulating layer 170 above the second metal layer ML2, that is, the second portion P11' and a portion of the insulating layer 170 above the first metal layer ML1, ie, Two parts P1'.

Next, referring to FIG. 7B, the first patterned photoresist layer PR33 is a first etching mask, and is etched to expose a portion of the drain D of the active device T. In the peripheral region P22, the first patterned photoresist layer PR33 is used as an etching mask, and is etched to expose a portion of the first metal layer ML1 and a portion of the second metal layer ML2. After that, and remove the first image The photoresist layer PR33 is formed. Next, referring to FIG. 7C, the first patterned photoresist layer PR33 is removed to expose the insulating layer 170'. In the peripheral region P22, in addition to the exposure of the insulating layer 170', a portion of the first metal layer ML1 and a portion of the second metal layer ML2 are also exposed. Next, referring to FIG. 7D, a second patterned photoresist layer PR44 is formed on the insulating layer 170' after the first patterned photoresist layer PR33 is removed, and the second patterned photoresist layer PR44 exposes the insulating layer 170. A plurality of second portions P22' of the second portion P22' of the insulating layer 170' on the first substrate 110 do not overlap the orthographic projection of the active device T on the first substrate 110. In the peripheral region P22, the second patterned photoresist layer PR44 covers the insulating layer 170', exposing a portion of the first metal layer ML1 and a portion of the second metal layer ML2. Then, the second patterned photoresist layer PR44 is a second etching mask, etched to expose a portion of the protective layer 170', and the second patterned photoresist layer PR44 is removed to form a pattern as shown in FIG. Insulation layer 170a.

Alternatively, FIG. 8A to FIG. 8B are schematic cross-sectional views showing a partial step of a method for fabricating a display panel according to another embodiment of the present invention. After the step of FIG. 6C, the first photoresist layer PR3 is formed on the insulating layer 170. After the first photoresist layer PR3 covers the insulating layer 170, please refer to FIG. 8A to provide a half-tone mask M6. On the resist layer PR3, a developing process is performed to expose the plurality of first portions P111' and the plurality of second portions P222' of the insulating layer 170, wherein the first portion P111' of the insulating layer 170 is positive on the first substrate 110 The projection does not overlap the orthographic projection of the active device T on the first substrate 110, and the orthographic projection portion of the second portion P222' of the insulating layer 170 on the first substrate 110 overlaps the active device T at the first An orthographic projection on the substrate 110. In detail, the thin region of the photoresist layer PR3 corresponds to the first portion P111', and the thin region of the photoresist layer PR3 also corresponds to the second portion P222' located above the drain D and the second metal. The second portion P222' opposite to the layer ML2 is exposed without the photoresist layer PR3 above the first metal layer ML1. Next, referring to FIG. 8B, the photoresist layer PR3 is etched to expose a portion of the protective layer 140' and a portion of the drain D. In the peripheral region P22, the photoresist layer PR3 is an etching mask, and is etched to expose a portion of the first metal layer ML1 and a portion of the second metal layer ML2. Thereafter, the photoresist layer PR3 is removed to form the patterned insulating layer 170a of FIG. 6I.

Referring to FIG. 5A, FIG. 5B, FIG. 6J and FIG. 6K, the display panel 10b includes a first substrate 110, an active device T, a protective layer 140', a patterned insulating layer 170a, a pixel electrode 180, and a second structure. The substrate 210, the common electrode 220, and the display medium layer 300. The first substrate 110 is divided into a pixel region P11, and the active device T is located in the pixel region P11 and has a source S and a drain D. The protective layer 140' is disposed on the first substrate 110 and covers the active device T, wherein the protective layer 140' has at least one first opening T1, and the first opening T1 exposes a portion of the drain D of the active device T.

The patterned insulating layer 170a is disposed on the protective layer 140' and has a plurality of strip structures 172 disposed corresponding to the pixel regions P11. There is a groove 174 between each two adjacent strip structures 172, and the groove 174 exposes a portion of the protective layer 140'. The orthographic projection of the strip structure 172 on the first substrate 110 does not overlap the active device T on the first substrate. The orthographic projection on 110, and the patterned insulating layer 170a has at least one second opening T2 that communicates with the first opening T1 and exposes a portion of the drain D of the active device T. The pixel electrode 180 is disposed on the patterned insulating layer 170a, wherein the pixel electrode 180 is a bulk electrode (also referred to as a flat electrode, that is, there are no openings, grooves, or slits in or on the pixel electrode 160. Or patterning and covering the strip structure 172 of the patterned insulating layer 170a and the recess 174, and protruding according to the strip structure 172 to form a plurality of strip electrodes 182. The pixel electrode 180 is connected to the drain D of the active device T through the second opening T2 and the first opening T1. The second substrate 210 is disposed opposite to the first substrate 110 . The common electrode 220 is disposed on the second substrate 210. The display medium layer 300 is disposed between the first substrate 110 and the second substrate 210, wherein the common electrode 220 and the pixel electrode 180 are located on the display medium layer 300, for example, opposite sides of the liquid crystal material.

In addition, the first substrate 110 of the embodiment further distinguishes the peripheral region P22 electrically connected to the pixel region P11 and the pad region (not shown) connected to the peripheral region P22, and the pad region has at least one pad ( Not shown), and the peripheral area P22 has a transition line structure TS'. The peripheral area P22 is located between the pixel area P11 and the pad area (not shown), and the pad area (not shown) is closest to the edge of the first substrate 110. Therefore, one end of the pad (not shown) is connected to one end of the transfer line structure TS', and one end of the transfer line structure TS' is not connected to the scan line or the data line, and the other end of the pad (not shown) An external circuit (not shown) other than the pixel area P11 is connected, and includes a driving circuit (not shown), a circuit chip (not shown), a circuit board (not shown), or other suitable circuit. The transfer structure TS' includes a first metal layer ML1, a second metal layer ML2, a gate insulating layer GI extending between the first metal layer ML1 and the second metal layer ML2, and an extension disposed in the peripheral region P22 and covering the second metal The protective layer 140' of the layer ML2, the patterned insulating layer 170a, and the electrode layer EL'. Protective layer 140' and patterned insulating layer 170a a plurality of first sub-openings T1 ′ and a plurality of second sub-openings T2 ′, wherein the second sub-opening T2 ′ communicates with the first sub-opening T1 ′, and the electrode layer EL ′ passes through the second sub-opening T 2 ′ and the first The sub-opening T1' communicates with the first metal layer ML1 and the second metal layer ML2.

Referring again to FIG. 6J, since the active device T of the present embodiment has been covered by the protective layer 140' before the patterned insulating layer 170a is formed, the etching rate of the protective layer 140' is lower than the etching rate of the insulating layer 170. Therefore, in the etching process for forming the patterned insulating layer 170a, the active device T can be protected by the protective layer 140' to avoid etching erosion. In this way, the display panel 10b of the embodiment can have better process yield and structural reliability. In addition, since the first substrate 110 of the present embodiment has the active device T, the first substrate 110 of the present embodiment and the components thereon can be regarded as an active device array substrate.

In summary, in the method for fabricating the substrate structure of the present invention, a protective layer is formed on the color filter pattern (ie, the COA substrate) or the active device (ie, the Non-COA substrate), and the protective layer is etched. The rate is lower than the etching rate of the second insulating layer (or insulating layer). Therefore, in the process of patterning the insulating layer, the color filter pattern or the active component can be effectively protected by the protective layer, and the fabrication yield and structural reliability of the overall substrate structure can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧Substrate

120‧‧‧First insulation

130‧‧‧Color filter pattern

140‧‧‧Protective layer

150‧‧‧Second insulation

P1‧‧‧ pixel area

P2‧‧‧ surrounding area

Claims (27)

A method for manufacturing a display panel, comprising: forming at least one active component on a first substrate, wherein the first substrate is divided into at least one pixel region, the active component is located in the pixel region and has a source and a drain Forming a first insulating layer on the first substrate and covering the active device; forming at least one color filter pattern on the first insulating layer, the color filter pattern exposing a portion above the drain An insulating layer; forming a protective layer on the color filter pattern, the protective layer covering the color filter pattern and the portion of the color filter pattern exposed above the drain electrode; forming a first a second insulating layer is disposed on the protective layer, and the second insulating layer covers the protective layer, wherein an etching rate of the protective layer is lower than an etching rate of the second insulating layer; and a patterning process is performed on the second insulating layer, Forming a patterned insulating layer by exposing a portion of the active electrode and the protective layer, wherein the patterned insulating layer has a plurality of strip structures corresponding to the pixel regions, and each Having adjacent at least one groove between the strip structures, the groove exposing a portion of the protective layer; forming a pixel electrode on the patterned insulating layer, wherein the pixel electrode is a piece of electrode and covering The strip-like structures of the patterned insulating layer and the recesses are convex according to the strip structures to form a plurality of strip electrodes, and the pixel electrodes are connected to the exposed portion of the patterned insulating layer a portion of the active element of the drain; and assembling a second substrate with the first substrate, wherein the second substrate is formed There is a pair of common electrodes that should be pixel electrodes, and a display medium layer is disposed between the pixel electrodes and the common electrodes. The method for fabricating a display panel according to claim 1, wherein the patterning process is performed on the second insulating layer, and the step of forming the patterned insulating layer comprises: forming a first patterned photoresist layer On the second insulating layer, the first patterned photoresist layer exposes a portion of the second insulating layer on the color filter pattern of the pixel region and a portion of the second insulating layer above the drain: The first patterned photoresist layer is a first etching mask, and is etched to expose a portion of the protective layer on the color filter pattern of the pixel region and a portion of the protective layer above the drain; Removing the first patterned photoresist layer to expose the second insulating layer, and the second insulating layer has the strip structures disposed corresponding to the pixel regions and each of the adjacent strip structures Having the recess therebetween to expose a portion of the protective layer; forming a second patterned photoresist layer on the second insulating layer exposed after removing the first patterned photoresist layer, the second pattern The photoresist layer exposes a portion above the drain The protective layer; the second patterned photoresist layer is a second etching mask, etched to expose a portion of the drain; and the second patterned photoresist layer is removed. The method for fabricating a display panel according to claim 1, wherein the patterning process is performed on the second insulating layer to form the patterned insulating layer. The method includes: forming a first patterned photoresist layer on the second insulating layer, the first patterned photoresist layer exposing a portion of the second insulating layer above the drain; and the first patterned light The resist layer is a first etching mask, etched to expose a portion of the drain; the first patterned photoresist layer is removed to expose the second insulating layer; and a second patterned photoresist layer is formed Except for the second insulating layer exposed after the first patterned photoresist layer, the second patterned photoresist layer exposes a portion of the second insulating layer on the color filter pattern of the pixel region The second patterned photoresist layer is a second etching mask, etched to expose a portion of the protective layer on the color filter pattern of the pixel region; and the second patterned photoresist is removed a layer to expose the second insulating layer, and the second insulating layer has the strip structures corresponding to the pixel regions and the two adjacent strips have the grooves therebetween to expose Part of the protective layer. The method for fabricating a display panel according to claim 1, wherein the patterning process is performed on the second insulating layer, and the step of forming the patterned insulating layer comprises: forming a photoresist layer on the second insulating layer On the layer, the photoresist layer covers the second insulating layer; a half-tone mask is provided on the photoresist layer, and a developing process is performed to expose the light on the color filter pattern of the pixel region a portion of the resist layer and a portion of the second insulating layer above the drain; Using the photoresist layer as an etching mask, etching to expose a portion of the protective layer and a portion of the drain on the color filter pattern of the pixel region; and removing the photoresist layer to expose the a second insulating layer, wherein the second insulating layer has the strip structures disposed corresponding to the pixel regions and the two adjacent strips have the grooves therebetween to expose a portion of the protective layer. The method of manufacturing the display panel according to claim 1, wherein the protective layer has a thickness of between 0.01 μm and 0.3 μm, and the second insulating layer has a thickness of between 0.1 μm and 0.5 μm. The manufacturing method of the display panel according to the first aspect of the invention, wherein the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride. The method for fabricating a display panel according to claim 1, wherein the material of the second insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or hafnium aluminum oxide. The method of manufacturing the display panel of claim 1, wherein the first substrate further defines a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad The region has at least one pad, the peripheral region has at least one transition structure, wherein the step of forming the transition structure includes: forming a gate of the active component, a gate insulating layer, the source and the drain Forming a first metal layer, an insulating layer and a second metal layer in the peripheral region, wherein the first metal layer and the gate are in the same film layer, and the insulating layer and the gate insulating layer belong to the same film layer And being located between the first metal layer and the second metal layer, and the second metal layer is the same film layer as the source electrode and the drain electrode; when the first insulating layer is formed, the first insulating layer is simultaneously covered The active component and The first metal layer and the second metal layer; when the patterning process is performed on the second insulating layer, the patterned insulating layer exposes the first metal layer and the second metal layer; and an electrode layer is formed When the patterned insulating layer is on the electrode layer, the first metal layer and the second metal layer exposed by the patterned conductive layer are connected to form the transition structure. A method for manufacturing a display panel, comprising: forming at least one active component on a first substrate, wherein the first substrate is divided into at least one pixel region, the active component is located in the pixel region and has a source and a stack Forming a protective layer on the first substrate, the protective layer covers the active device; forming an insulating layer on the protective layer, and the insulating layer covers the protective layer, wherein the etching rate of the protective layer is lower than the Etching rate of the insulating layer; performing a patterning process on the insulating layer to expose the drain of the active device and a portion of the protective layer to form a patterned insulating layer, wherein the patterned insulating layer has a plurality of pairs a strip-like structure disposed in the pixel region, and each of the two adjacent strip-like structures having at least one groove therebetween, the groove exposing a portion of the protective layer; forming a pixel electrode on the patterned insulating layer The pixel electrode is a strip electrode and covers the strip structures of the patterned insulating layer and the recess, and is convex according to the strip structures to form a plurality of strip electrodes, and the pixel Electrode connection Patterning the insulating layer to expose the drain electrode of the active device; and a second substrate with the first substrate assembly, wherein the second substrate has formed There is a pair of common electrodes that should be pixel electrodes, and a display medium layer is disposed between the pixel electrodes and the common electrodes. The method for fabricating a display panel according to claim 9, wherein the patterning process is performed on the insulating layer, and the step of forming the patterned insulating layer comprises: forming a first patterned photoresist layer on the insulating layer The first patterned photoresist layer exposes a plurality of first portions and a plurality of second portions of the insulating layer, wherein an orthographic projection of the first portions of the insulating layer on the first substrate does not overlap the An orthographic projection of the active component on the first substrate, and an orthographic projection of the second portions of the insulating layer on the first substrate overlaps an orthographic projection of the drain on the first substrate; The patterned photoresist layer is a first etching mask, etched to expose a portion of the protective layer; the first patterned photoresist layer is removed to expose the insulating layer, and the insulating layer has a corresponding pixel region Providing the strip structure and the two adjacent strips between the strips to expose a portion of the protective layer; forming a second patterned photoresist layer to remove the first patterned light After the resist layer is exposed on the protective layer, the first The second patterned photoresist layer exposes a plurality of third portions of the protective layer, wherein the positive projection portions of the third portions of the protective layer on the first substrate overlap the source on the first substrate An orthographic projection; the second patterned photoresist layer is a second etching mask, etched to expose a portion of the drain of the active device; and the second patterned photoresist layer is removed. The method for fabricating a display panel according to claim 9, wherein the patterning process is performed on the insulating layer, and the step of forming the patterned insulating layer comprises: forming a first patterned photoresist layer on the insulating layer On the layer, the first patterned photoresist layer exposes a plurality of first portions of the insulating layer, wherein an orthographic portion of the first portion of the insulating layer on the first substrate overlaps the first pole An orthographic projection on the substrate; the first patterned photoresist layer is a first etching mask, etched to expose a portion of the drain of the active device; removing the first patterned photoresist layer to expose The insulating layer; forming a second patterned photoresist layer on the insulating layer after removing the first patterned photoresist layer, the second patterned photoresist layer exposing a plurality of second portions of the insulating layer The orthographic projection of the second portions of the insulating layer on the first substrate does not overlap the orthographic projection of the active device on the first substrate; and the second patterned photoresist layer is a second etching a mask that is etched to expose a portion of the protective layer; Removing the second patterned photoresist layer to form the patterned insulating layer, wherein the patterned insulating layer has the strip structures corresponding to the pixel regions and between the two adjacent strip structures The groove is provided to expose a portion of the protective layer. The method for fabricating a display panel according to claim 9, wherein the patterning process is performed on the insulating layer, and the step of forming the patterned insulating layer comprises: Forming a photoresist layer on the insulating layer, the photoresist layer covers the insulating layer; providing a half-tone mask on the photoresist layer, and performing a display process to expose the first portion of the insulating layer a plurality of second portions, wherein an orthographic projection of the first portions of the insulating layer on the first substrate does not overlap an orthographic projection of the active device on the first substrate, and the second portions of the insulating layer The orthographic projection on the first substrate overlaps the orthographic projection of the active device on the first substrate; the photoresist layer is an etch mask, and is etched to expose a portion of the protective layer and a portion of the drain; And removing the photoresist layer to form the patterned insulating layer, wherein the patterned insulating layer has the strip structures disposed corresponding to the pixel regions and the recesses between the two adjacent strip structures a groove to expose a portion of the protective layer. The method for fabricating a display panel according to claim 9, wherein an etching rate ratio of the protective layer to the insulating layer is about 1:3. The manufacturing method of the display panel according to claim 9, wherein the protective layer has a thickness of between 0.01 μm and 0.3 μm, and the insulating layer has a thickness of between 0.1 μm and 0.5 μm. The method for fabricating a display panel according to claim 9, wherein the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride. The method for fabricating a display panel according to claim 9, wherein the material of the insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide. The method of manufacturing the display panel of claim 9, wherein the first substrate further distinguishes a peripheral region electrically connected to the pixel region and a pad area connected to the peripheral area, and the pad area has at least one pad, the peripheral area has at least one turn line structure, wherein the step of forming the line structure comprises: forming a gate of the active element, When the gate insulating layer, the source and the drain, a first metal layer, an insulating layer and a second metal layer are simultaneously formed in the peripheral region, wherein the first metal layer and the gate are in the same film layer. The insulating layer and the gate insulating layer belong to the same film layer and are located between the first metal layer and the second metal layer, and the second metal layer is in the same film layer as the source and the drain; forming the protection The protective layer simultaneously covers the active device and the first metal layer and the second metal layer; when the patterning process is performed on the insulating layer, the patterned insulating layer exposes the first metal layer and the a second metal layer; and forming an electrode layer on the patterned insulating layer, the electrode layer connecting the first metal layer and the second metal layer exposed by the patterned conductive layer to form the transition line structure. A display panel includes: a first substrate, having at least one pixel region; at least one active component located in the pixel region, and having a source and a drain; a first insulating layer disposed on the first a substrate, and covering the active device, wherein the first insulating layer has at least one first opening, and the first opening exposes a portion of the drain of the active device; at least one color filter pattern is disposed on the first An insulating layer, wherein the color filter pattern exposes a portion of the first insulating layer on the drain; a protective layer disposed on the color filter pattern and covering the color filter pattern and the portion of the first filter layer on the drain exposed by the color filter pattern, wherein the protective layer has at least one second An opening, the second opening communicates with the first opening and exposes a portion of the drain of the active device; a patterned insulating layer disposed on the protective layer and having a plurality of strip structures corresponding to the pixel regions And at least one groove between each of the two adjacent strip structures, the groove exposing a portion of the protective layer, wherein the strip structures are located on the color filter pattern, and the strip structures are The orthographic projection on the first substrate does not overlap the orthographic projection of the active device on the first substrate, the patterned insulating layer has at least one third opening, and the third openings communicate with the second opening and the first opening And exposing a portion of the drain of the active device; a pixel electrode disposed on the patterned insulating layer, wherein the pixel electrode is a strip electrode and covering the strip structure of the patterned insulating layer The groove, Forming a plurality of strip electrodes according to the strip structures, and the pixel electrodes are connected to the drain of the active device through the third opening, the second opening and the first opening; a second substrate Aligning with the first substrate; a common electrode disposed on the second substrate; and a display dielectric layer disposed between the first substrate and the second substrate, wherein the common electrode and the drawing The element electrodes are located on opposite sides of the display medium layer. The display panel of claim 18, wherein the first substrate is further divided into a peripheral region electrically connected to the pixel region and connected to the peripheral region. a pad area, the pad area having at least one pad, the peripheral area having at least one transition structure, and the line structure comprising a first metal layer, a second metal layer, and extending to the first metal The first insulating layer between the layer and the second metal layer and the protective layer, the patterned insulating layer and an electrode layer disposed in the peripheral region and covering the first insulating layer, the first insulating layer, The protective layer and the patterned insulating layer respectively have a plurality of first sub-openings, a plurality of second sub-openings, and a plurality of third sub-openings, the third sub-openings connecting the second sub-openings and the first a sub-opening, and the electrode layer communicates with the first metal layer and the second metal layer through the third sub-openings, the second sub-openings, and the first sub-openings. The display panel of claim 18, wherein the protective layer has a thickness of between 0.01 micrometers and 0.3 micrometers, and the second insulating layer has a thickness of between 0.1 micrometers and 0.5 micrometers. The display panel of claim 18, wherein the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride. The display panel of claim 18, wherein the material of the second insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide. A display panel includes: a first substrate, having at least one pixel region; at least one active component, located in the pixel region, and having a source and a drain; a protective layer disposed on the first substrate And covering the active component, wherein the protective layer has at least one first opening, the first opening exposing a portion of the drain of the active component; a patterned insulating layer disposed on the protective layer, having a plurality of strip structures corresponding to the pixel regions, and each of the adjacent strips having at least one groove therebetween, the recess is exposed a portion of the protective layer, wherein an orthographic projection of the strip structures on the first substrate does not overlap an orthographic projection of the active device on the first substrate, and the patterned insulating layer has at least one second opening, a second opening is connected to the first opening and exposes a portion of the drain of the active device; a pixel electrode is disposed on the patterned insulating layer, wherein the pixel electrode is a strip electrode and covers the patterned insulating layer The strip-shaped structures of the layer and the recesses are convex according to the strip structures to form a plurality of strip electrodes, and the pixel electrodes are connected to the active element through the second opening and the first opening a second substrate disposed opposite to the first substrate; a common electrode disposed on the second substrate; and a display dielectric layer disposed between the first substrate and the second substrate Where the common electrode and the painting Electrodes located on opposite sides of the dielectric layer of the display. The display panel of claim 23, wherein the first substrate further has a peripheral region electrically connected to the pixel region and a pad region connected to the peripheral region, and the pad region has at least a pad having at least one turn structure, and the wire structure includes a first metal layer, a second metal layer, and a gate extending between the first metal layer and the second metal layer An insulating layer and the protective layer, the patterned insulating layer and an electrode layer extending over the peripheral region and covering the second metal layer, the protective layer and the patterned insulating layer respectively having a plurality of first sub-openings and a second sub-opening, the second sub-openings are connected to the first sub-openings, And the electrode layer communicates with the first metal openings and the second metal layer through the second sub-openings. The display panel of claim 23, wherein the protective layer has a thickness of between 0.01 micrometers and 0.3 micrometers, and the insulating layer has a thickness of between 0.1 micrometers and 0.5 micrometers. The display panel of claim 23, wherein the material of the protective layer comprises cerium oxide, cerium oxynitride, aluminum nitride or cerium aluminum nitride. The display panel of claim 23, wherein the material of the insulating layer comprises tantalum nitride, hafnium oxynitride, aluminum oxide or yttrium aluminum oxide.