TWI538167B - Three-dimensional semiconductor device - Google Patents
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Description
本發明是有關於一種三維半導體元件,且特別是有關於一種操作快速的垂直通道式三維半導體元件。The present invention relates to a three-dimensional semiconductor component, and more particularly to a vertically operated three-dimensional semiconductor component that operates rapidly.
非揮發性記憶體元件在設計上有一個很大的特性是,當記憶體元件失去或移除電源後仍能保存資料狀態的完整性。目前業界已有許多不同型態的非揮發性記憶體元件被提出。不過相關業者仍不斷研發新的設計或是結合現有技術,進行含記憶胞之記憶體平面的堆疊以達到具有更高儲存容量的記憶體結構。例如已有一些多層薄膜電晶體堆疊之反及閘(NAND)型快閃記憶體結構被提出。相關業者已經提出各種不同結構的三維記憶體元件,例如具單閘極(Single-Gate)之記憶胞、雙閘極(double gate)之記憶胞,和環繞式閘極(surrounding gate)之記憶胞等三維記憶體元件。A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cells with memory cells to achieve a memory structure with higher storage capacity. For example, some NAND type flash memory structures have been proposed for multilayer thin film transistor stacks. Related companies have proposed three-dimensional memory components of various structures, such as memory cells with single-gate, double-gate memory cells, and memory cells of a surrounding gate. And other three-dimensional memory components.
相關設計者無不期望可以建構出一三維記憶體結構,不僅具有許多層堆疊平面(記憶體層)而達到更高的儲存容量,更具有優異的電子特性(例如具有良好的資料保存可靠性和操作速度),使記憶體結構可以被穩定和快速的如進行抹除和編程等操作。再者,NAND型快閃記憶體的頁(Page)尺寸係與位元線數目成比例。因此當元件尺寸縮小,不僅是成本降低,其平行操作的增加也提高了元件的讀寫速度,進而達到更高的資料傳輸速度。以一般的三維垂直通道式記憶體元件為例,其具有更大的通孔尺寸可降低製程上的困難度。但越大的記憶胞尺寸會造成較少的位元線數目,較少的平行操作以及較慢的資料讀寫速度。而傳統的記憶胞設計,一般是以一條選擇線對同一列的記憶胞進行選取,且同一行的記憶胞係對應一條位元線。以16個記憶胞串列(cell strings)排列成4行和和4列,並具有4條位元線為例和4條選擇線,每個記憶胞串列係對應一條位元線和一條選擇線(如SSL 1/2/3/4)。如欲讀取所有記憶胞之資料,需選取選擇線SSL1該列四個串列資料,之後依序選取選擇線SSL2、SSL 3 和SSL 4以獲得另外12個串列資料。必須循環操作4次,利用選擇線SSL 1/2/3/4之選取,才能讀取所有串列資料。再者,當選擇線SSL1被選取和進行操作時,其他對應選擇線SSL 2/3/4之記憶胞串列也被施以相同的閘極偏壓,而使閘極受到干擾。此外,非選取串列(non-selected strings)也具有閘極偏壓表示有不需要的功率消耗(power consumption)存在。因此,傳統的記憶胞設計不僅具有較低的操作速度,更具有較大的功率消耗和干擾。It is hoped by the relevant designers that a three-dimensional memory structure can be constructed, which not only has many layer stacking planes (memory layers) but also achieves higher storage capacity and superior electronic characteristics (for example, good data storage reliability and operation). Speed), so that the memory structure can be stabilized and fast as operations such as erasing and programming. Furthermore, the page size of the NAND type flash memory is proportional to the number of bit lines. Therefore, when the component size is reduced, not only the cost is reduced, but the parallel operation increases the read/write speed of the component, thereby achieving a higher data transmission speed. Taking a general three-dimensional vertical channel type memory element as an example, it has a larger through-hole size to reduce the difficulty in the process. But larger memory cell sizes result in fewer bit line numbers, less parallel operations, and slower data read and write speeds. In the traditional memory cell design, the memory cells of the same column are generally selected by one selection line, and the memory cells of the same row correspond to one bit line. It is arranged in 4 rows and 4 columns with 16 cell strings, and has 4 bit lines as an example and 4 selection lines, and each memory cell string corresponds to one bit line and one selection. Line (eg SSL 1/2/3/4). To read all the data of the memory cell, select the four serial data of the column of the selection line SSL1, and then select the selection lines SSL2, SSL 3 and SSL 4 to obtain another 12 serial data. It must be cycled 4 times, and all the serial data can be read by selecting the selection line SSL 1/2/3/4. Moreover, when the selection line SSL1 is selected and operated, the memory cell strings of the other corresponding selection lines SSL 2/3/4 are also applied with the same gate bias, and the gate is disturbed. In addition, non-selected strings also have a gate bias indicating the presence of unwanted power consumption. Therefore, the traditional memory cell design not only has a lower operating speed, but also has greater power consumption and interference.
本發明係有關於一種三維半導體元件。根據實施例之三維半導體元件,所有的記憶胞可被同時讀取,而可提高操作速度。再者,依據實施例之三維半導體元件其頻帶寬度(bandwidth)擴大,功率消耗(power consumption)下降,且讀取記憶胞時相鄰記憶胞之間的干擾亦可減少。The present invention is directed to a three-dimensional semiconductor component. According to the three-dimensional semiconductor element of the embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, according to the three-dimensional semiconductor device of the embodiment, the bandwidth is enlarged, the power consumption is lowered, and the interference between adjacent memory cells when the memory cell is read can be reduced.
根據實施例,係提出一種三維半導體元件,包括: 複數層記憶體層(memory layers),垂直堆疊於一基板上且記憶體層係相互平行;複數條選擇線(selection lines),位於記憶體層上方,且選擇線係相互平行;複數條位元線(bit lines),位於選擇線上方,且位元線係相互平行並垂直於選擇線;複數條串列(strings) 垂直於記憶體層和選擇線,且串列(strings)係電性連接至對應之選擇線;複數個記憶胞(cells)分別由串列、選擇線和位元線所定義,且記憶胞係排列為複數列(rows)及複數行(columns),其中位元線係平行於一行方向(column direction),而選擇線係平行於一列方向(row direction)。其中,同一行中相鄰之記憶胞係電性連接至不同的位元線。According to an embodiment, a three-dimensional semiconductor device is provided, comprising: a plurality of memory layers stacked vertically on a substrate and the memory layers are parallel to each other; a plurality of selection lines are located above the memory layer, and The selection lines are parallel to each other; a plurality of bit lines are located above the selection line, and the bit lines are parallel to each other and perpendicular to the selection line; the plurality of strings are perpendicular to the memory layer and the selection line, and The strings are electrically connected to the corresponding selection lines; the plurality of cells are defined by the series, the selection line and the bit line, respectively, and the memory cells are arranged in a plurality of rows and a plurality of rows. (columns), wherein the bit line is parallel to a column direction, and the selection line is parallel to a row direction. The adjacent memory cells in the same row are electrically connected to different bit lines.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下:In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
10‧‧‧基板10‧‧‧Substrate
11‧‧‧記憶體層11‧‧‧ memory layer
12、13、SSL、SSL1~SSL4‧‧‧選擇線12, 13, SSL, SSL1~SSL4‧‧‧ selection line
15‧‧‧串列15‧‧‧Listing
151‧‧‧通道層151‧‧‧channel layer
152‧‧‧導電層152‧‧‧ Conductive layer
17‧‧‧串列接觸17‧‧‧ Serial contact
18‧‧‧金屬部18‧‧‧Metal Department
18a‧‧‧第一部18a‧‧‧ first
18b‧‧‧第二部18b‧‧‧ second
19‧‧‧導電孔19‧‧‧Electrical hole
22‧‧‧階梯接觸22‧‧‧Step contact
BL、BL1~BL16‧‧‧位元線BL, BL1~BL16‧‧‧ bit line
Row1~Row8‧‧‧記憶胞列Row1~Row8‧‧‧ memory cell
Column1~Column8‧‧‧記憶胞行Column1~Column8‧‧‧ memory cell line
Lupper‧‧‧上直線L upper ‧‧‧On the straight line
Llower‧‧‧下直線L lower ‧‧‧Lower straight
Px‧‧‧記憶胞之x 節距Px‧‧‧ memory cell x pitch
Py‧‧‧記憶胞之y 節距Py‧‧‧ memory cell y pitch
X ‧‧‧一金屬部之寬度X ‧‧‧The width of a metal part
Y1‧‧‧一金屬部之長度Y1‧‧‧The length of a metal part
Y2‧‧‧一金屬部之 第一部 和第二部之總長度Y2‧‧‧ The total length of the first and second parts of a metal department
1a、1b、2a、2b‧‧‧位置1a, 1b, 2a, 2b‧‧‧ position
L1a‧‧‧對應第一行記憶胞之位置1a之直線L1a‧‧‧ corresponds to the line 1a of the first line of memory cells
L1b‧‧‧對應第一行記憶胞之位置1b之直線L1b‧‧‧ corresponds to the line 1b of the first line of memory cells
L2a‧‧‧對應第二行記憶胞之位置2a之直線L2a‧‧‧ corresponds to the line 2a of the second line of memory cells
L2b‧‧‧對應第二行記憶胞之位置2b之直線L2b‧‧‧ corresponds to the line 2b of the second line of memory cells
Xc‧‧‧一串列接觸之寬度Xc‧‧‧The width of a series of contacts
Yc‧‧‧一串列接觸之長度Yc‧‧‧ The length of a series of contacts
第1圖係為一三維半導體元件之立體圖。
Figure 1 is a perspective view of a three-dimensional semiconductor component.
第2圖係為本揭露第一實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 2 is a top view showing the memory cell design of the three-dimensional semiconductor element of the first embodiment.
第3A圖繪示根據本揭露第一實施例之一種矩陣陣列記憶胞之串列接觸排列的示意圖。FIG. 3A is a schematic diagram showing a tandem contact arrangement of a matrix array memory cell according to the first embodiment of the present disclosure.
第3B~3D圖繪示根據本揭露第一實施例之一種電性連接串列接觸和對應位元線之實施方式。3B-3D illustrate an embodiment of an electrical connection string contact and a corresponding bit line according to the first embodiment of the present disclosure.
第4圖係為本揭露第二實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 4 is a top view showing the memory cell design of the three-dimensional semiconductor element of the second embodiment.
第5圖係為本揭露第三實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 5 is a top view showing the memory cell design of the three-dimensional semiconductor element of the third embodiment.
第6A圖係繪示本揭露一實施例之一種矩陣陣列記憶胞中,金屬部之排列與設計係部分地遮蓋對應之串列接觸的示意圖。FIG. 6A is a schematic diagram showing the arrangement of the metal portions and the design partially covering the corresponding serial contacts in a matrix array memory cell according to an embodiment of the present disclosure.
第6B圖係繪示本揭露另一實施例之一種矩陣陣列記憶胞中,金屬部之排列與設計係完全遮蓋對應之串列接觸的示意圖。FIG. 6B is a schematic diagram showing the arrangement of the metal portions and the design system completely covering the corresponding serial contacts in a matrix array memory cell according to another embodiment of the present disclosure.
第7圖係為本揭露第四實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 7 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fourth embodiment.
第8圖係為本揭露第五實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 8 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fifth embodiment.
第9圖係為本揭露第六實施例之三維半導體元件之記憶胞設計的上視圖。Fig. 9 is a top view showing the memory cell design of the three-dimensional semiconductor element of the sixth embodiment.
第10A圖繪示本揭露一實施例之一橢圓形串列接觸的示意圖。FIG. 10A is a schematic diagram showing an elliptical tandem contact of an embodiment of the present disclosure.
第10B圖繪示本揭露一實施例之一長方形串列接觸的示意圖。FIG. 10B is a schematic diagram showing a rectangular string contact according to an embodiment of the present disclosure.
本揭露之實施例係提出一種操作快速的三維半導體元件,例如一垂直通道式(vertical-channel,VC)三維半導體元件。根據實施例之三維半導體元件,所有的記憶胞可被同時讀取,而可提高操作速度。再者,依據實施例之三維半導體元件其頻帶寬度(bandwidth)擴大(增加),功率消耗(power consumption)下降,且讀取記憶胞時相鄰記憶胞之間的干擾亦可減少。Embodiments of the present disclosure propose a fast-operating three-dimensional semiconductor component, such as a vertical-channel (VC) three-dimensional semiconductor component. According to the three-dimensional semiconductor element of the embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, according to the three-dimensional semiconductor device of the embodiment, the bandwidth is increased (increased), the power consumption is lowered, and the interference between adjacent memory cells when the memory cell is read can be reduced.
本揭露 可應用至多種不同記憶胞排列方式之三維半導體元件例如垂直通道式(vertical-channel,VC)三維半導體元件。第1圖係為一三維半導體元件之立體圖。一三維半導體元件包括複數層記憶體層(memory layers)11(包括控制閘極),垂直堆疊於一基板10上,且這些記憶體層11係相互平行;複數條選擇線(selection lines)12,位於記憶體層11上方且該些選擇線12係相互平行;複數條串列(strings)15係垂直於記憶體層11和選擇線12,且該些串列15係電性連接至對應之該些選擇線12;複數條位元線(bit lines)BLs係位於選擇線12上方,且該些位元線BLs係相互平行並垂直於選擇線12;複數個記憶胞(cells)係分別由該些串列15、該些選擇線12和該些位元線BLs定義,且這些記憶胞係排列為複數列(rows)及複數行(columns),其中位元線BLs係平行於一行方向(column direction)而選擇線12係平行於一列方向(row direction)。再者,複數個串列接觸(string contacts)17係垂直於記憶體層11和選擇線12,且每串列接觸17之設置係對應於記憶胞之每串列15,其中串列接觸17係電性連接至對應的選擇線12和對應的位元線BL。三維半導體元件還包括其它元件,例如選擇線12是指上方選擇線(upper select lines,upper SG),而記憶體層11下方更有下方選 擇線(lower select lines,lower SG) 13的形成。The present disclosure is applicable to three-dimensional semiconductor components such as vertical-channel (VC) three-dimensional semiconductor components of a plurality of different memory cell arrangements. Figure 1 is a perspective view of a three-dimensional semiconductor component. A three-dimensional semiconductor component includes a plurality of memory layers 11 (including control gates) stacked vertically on a substrate 10, and the memory layers 11 are parallel to each other; a plurality of selection lines 12 are located in the memory Above the body layer 11 and the selection lines 12 are parallel to each other; a plurality of strings 15 are perpendicular to the memory layer 11 and the selection line 12, and the series 15 are electrically connected to the corresponding selection lines 12 a plurality of bit lines BLs are located above the selection line 12, and the bit lines BLs are parallel to each other and perpendicular to the selection line 12; a plurality of cells are respectively arranged by the series 15 The selection lines 12 and the bit lines BLs are defined, and the memory cell lines are arranged in a plurality of rows and a plurality of columns, wherein the bit lines BLs are selected in parallel with a column direction. Line 12 is parallel to a row direction. Furthermore, a plurality of string contacts 17 are perpendicular to the memory layer 11 and the selection line 12, and the arrangement of each string of contacts 17 corresponds to each column 15 of the memory cells, wherein the series contacts 17 are electrically The connection is made to the corresponding selection line 12 and the corresponding bit line BL. The three-dimensional semiconductor component further includes other components. For example, the select line 12 refers to an upper select line (upper SG), and the memory layer 11 has a lower select line (lower SG) 13 formed below.
根據本揭露之實施例,三維半導體元件中同一行中相鄰之記憶胞係電性連接至不同的位元線。According to an embodiment of the present disclosure, adjacent memory cells in the same row of the three-dimensional semiconductor component are electrically connected to different bit lines.
以下係提出其中兩種應用例,例如三維半導體元件中之記憶胞排列為一矩陣陣列(matrix array)(即相鄰列及相鄰行的記憶胞以一矩陣形式排列),或是記憶胞排列為一蜂巢狀陣列(honeycomb array) (即相鄰列及相鄰行的記憶胞係以未對準(中心偏移)(misaligned)形式排列),而作本揭露之實施例之說明。然而本揭露並不僅限於這兩種記憶胞之排列態樣。Two kinds of application examples are proposed below, for example, the memory cells in the three-dimensional semiconductor component are arranged in a matrix array (ie, the memory cells of adjacent columns and adjacent rows are arranged in a matrix form), or the memory cells are arranged. The description of the embodiments of the present disclosure is made for a honeycomb array (i.e., memory cells of adjacent columns and adjacent rows are arranged in a misaligned (misaligned) form). However, the disclosure is not limited to the arrangement of the two memory cells.
根據第一、第二和第三實施例,相鄰列及相鄰行的記憶胞係排列為一矩陣(即一矩陣陣列)。根據第四、第五和第六實施例,相鄰列及相鄰行的記憶胞係排列為一蜂巢狀陣列。實施例所敘述之細部結構係作為例示說明之用,並非作為限縮本揭露保護範圍之用。According to the first, second and third embodiments, the memory cells of adjacent columns and adjacent rows are arranged in a matrix (i.e., a matrix array). According to the fourth, fifth and sixth embodiments, the memory cells of adjacent columns and adjacent rows are arranged in a honeycomb array. The detailed structure described in the embodiments is for illustrative purposes and is not intended to limit the scope of the disclosure.
以下實施例係參照所附圖式敘述本揭露之相關結構與製程,然本揭露並不僅限於此。實施例中相同或類似之元件係以相同或類似的標號標示。需注意的是,本揭露並非顯示出所有可能的實施例。未於本揭露提出的其他實施態樣也可能可以應用。再者,圖式上的尺寸比例並非按照實際產品等比例繪製。因此,說明書和圖示內容僅作敘述實施例之用,而非作為限縮本揭露保護範圍之用。
矩陣陣列之記憶胞(Cells in a matrix array)The following embodiments describe the related structures and processes of the present disclosure with reference to the accompanying drawings, but the disclosure is not limited thereto. The same or similar elements in the embodiments are denoted by the same or similar reference numerals. It should be noted that the disclosure does not show all possible embodiments. Other implementations not presented in this disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
Cells in a matrix array
在第一、第二和第三實施例中,三維半導體元件中相鄰列及相鄰行的記憶胞係以一矩陣形式排列(因此稱為一矩陣陣列)。再者,這些實施例中記憶胞之串列接觸17係透過一圖案化金屬層(patterned metal layer)和複數個導電孔(conductive vias)而電性連接至對應的位元線BLs。
<第一實施例>In the first, second and third embodiments, the memory cells of adjacent columns and adjacent rows in the three-dimensional semiconductor element are arranged in a matrix form (hence the order of a matrix array). Moreover, in the embodiment, the serial contact 17 of the memory cell is electrically connected to the corresponding bit line BLs through a patterned metal layer and a plurality of conductive vias.
<First Embodiment>
第2圖係為本揭露第一實施例之三維半導體元件之記憶胞設計的上視圖。請同時參照第1圖之三維半導體元件,其繪示記憶體層11、選擇線12、串列15、串列接觸17和位元線BL等元件。Fig. 2 is a top view showing the memory cell design of the three-dimensional semiconductor element of the first embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown.
複數個記憶胞(cells)係分別由串列15、選擇線12和位元線BLs定義,且這些記憶胞係排列為一矩陣陣列。根據實施例,這些記憶胞係排列為複數列(rows)及複數行(columns),其中該些行(其行方向係沿著x方向)平行於位元線BL(如BL1~BL16),而該些列(其列方向係沿著y方向)平行於選擇線(如SSL1~SSL4)。而這些記憶胞的每一串列例如是包括一通道層(channel layer)151包圍一導電層(conductive layer)152,以作一實施例之說明。然而本揭露並不以此為限。A plurality of cells are defined by the string 15, the selection line 12, and the bit line BLs, respectively, and the memory cells are arranged in a matrix array. According to an embodiment, the memory cell lines are arranged in a plurality of rows and a plurality of columns, wherein the rows (the row direction is along the x direction) are parallel to the bit line BL (eg, BL1 to BL16), and The columns (the column direction is along the y direction) are parallel to the select line (eg, SSL1~SSL4). Each of the strings of the memory cells includes, for example, a channel layer 151 surrounding a conductive layer 152 for illustration of an embodiment. However, this disclosure is not limited to this.
根據第一實施例,同一行中相鄰之記憶胞係電性連接至不同的位元線。以第2圖的第1行之記憶胞為例,位於第1列和第2列的相鄰記憶胞係分別電性連接至位元線BL1和BL2。According to the first embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row of FIG. 2 as an example, the adjacent memory cell lines located in the first column and the second column are electrically connected to the bit lines BL1 and BL2, respectively.
再者,第一實施例中,四條位元線係相對應地設置於同一行中之記憶胞處。以第2圖的第1行之記憶胞為例,四條位元線BL1 ~BL4係相對應地位於第1行之記憶胞處。Furthermore, in the first embodiment, the four bit lines are correspondingly disposed in the memory cells in the same row. Taking the memory cell of the first row of Fig. 2 as an example, the four bit lines BL1 to BL4 are correspondingly located at the memory cells of the first row.
再者,第一實施例中,串列接觸17之位置係偏移於對應之記憶胞之串列15的中心。如第2圖所示,串列接觸17之位置係對應於串列15的一上方部份(upper portion)或是一下方部份(lower portion)。Moreover, in the first embodiment, the position of the tandem contact 17 is offset from the center of the corresponding memory cell string 15. As shown in FIG. 2, the position of the tandem contact 17 corresponds to an upper portion or a lower portion of the string 15.
再者,第一實施例中,對應於同一列之記憶胞的串列接觸17,相鄰的串列接觸17其中心係未對準地錯開排列(misaligned)。以第2圖的第1列之記憶胞為例,位於第1行和第2行之相鄰的串列接觸17係未對準地錯開排列。Furthermore, in the first embodiment, the tandem contacts 17 of the memory cells of the same column, the adjacent series contacts 17 are misaligned in a misaligned manner. Taking the memory cell of the first column of Fig. 2 as an example, the adjacent series of contacts 17 located in the first row and the second row are misaligned and arranged in a staggered manner.
再者,對應於同一列之記憶胞的串列接觸17,每相隔一個的串列 接觸17(例如於第一行和第三行的串列接觸17)係沿著列方向排列成一直線。請參照第3A圖,其繪示根據本揭露第一實施例之一種矩陣陣列記憶胞之串列接觸排列的示意圖。對應於同一列之記憶胞的串列接觸17係沿著列方向(即x方向)分別排成一第一直線(例如上直線Lupper )和一第二直線(例如下直線Llower ),且第一直線係位於對應該些串列15的一上方部份(upper portion),第二直線係位於對應該些串列的一下方部份(lower portion)。因此,根據串列接觸17的位置,對應於同一列之記憶胞的串列接觸17可區分為兩個群組,第一群組和第二群組係分別由奇數行(如第一行、第三行…)和偶數行(如第二行、第四行…)的串列接觸17所組成。奇數行的串列接觸17係沿著上直線Lupper 排列,偶數行的串列接觸17係沿著下直線Llower 排列。Furthermore, the tandem contacts 17 (e.g., the tandem contacts 17 in the first row and the third row) that are spaced apart from each other by the tandem contacts 17 of the memory cells of the same column are arranged in a line along the column direction. Please refer to FIG. 3A, which is a schematic diagram showing a tandem contact arrangement of a matrix array memory cell according to the first embodiment of the present disclosure. The tandem contacts 17 corresponding to the memory cells of the same column are arranged along the column direction (ie, the x direction) into a first straight line (eg, an upper straight line L upper ) and a second straight line (eg, a lower straight line L lower ), and A straight line is located at an upper portion corresponding to the series 15 and a second line is located at a lower portion corresponding to the series. Therefore, according to the position of the tandem contact 17, the serial contact 17 of the memory cell corresponding to the same column can be divided into two groups, the first group and the second group are respectively composed of odd lines (such as the first line, The third line...) consists of a series of contacts 17 of even lines (such as the second line, the fourth line...). The tandem contacts 17 of the odd rows are arranged along the upper straight line L upper , and the tandem contacts 17 of the even rows are arranged along the lower straight line L lower .
再者,第一實施例中,對應同一列記憶胞(Row1, or Row2, or Row3 or Row4)的串列接觸17係電性連接至該些選擇線之一條選擇線,例如選擇線SSL1 或SSL2或SSL3或SSL4,如第2圖所示。然而本揭露並不以此為限。在其它實施例中,至少兩相鄰列的串列接觸17,例如相鄰四列的串列接觸17,係電性連接至一條選擇線(如之後的第二和第三實施例所述)。Furthermore, in the first embodiment, the serial contact 17 corresponding to the same column of memory cells (Row1, or Row2, or Row3 or Row4) is electrically connected to one of the selection lines, for example, the selection line SSL1 or SSL2. Or SSL3 or SSL4, as shown in Figure 2. However, this disclosure is not limited to this. In other embodiments, at least two adjacent columns of tandem contacts 17, such as adjacent four columns of tandem contacts 17, are electrically connected to a select line (as described in the second and third embodiments that follow) .
再者,如第一實施例所述之矩陣陣列之記憶胞,此些串列接觸17係透過一圖案化金屬層(patterned metal layer)和複數個導電孔(conductive vias)19而電性連接至對應的該些位元線(例如BL1/BL2/…/BL16),如第2圖所示。其中,圖案化金屬層係包括複數個金屬部(metal portions)18其分別形成於對應的該些記憶胞之串列接觸17處,各導電孔19係形成於各金屬部18上以電性連接至對應的位元線(例如BL1/BL2/…/BL16)。Furthermore, the memory cells of the matrix array according to the first embodiment are electrically connected to the series of contacts 17 through a patterned metal layer and a plurality of conductive vias 19. Corresponding to these bit lines (for example, BL1/BL2/.../BL16), as shown in FIG. The patterned metal layer includes a plurality of metal portions 18 respectively formed at the corresponding serial contacts 17 of the memory cells, and the conductive holes 19 are formed on the metal portions 18 to be electrically connected. To the corresponding bit line (for example, BL1/BL2/.../BL16).
第3B~3D圖繪示根據本揭露第一實施例之一種電性連接串列接觸和對應位元線之實施方式。提供如第3B圖所示之記憶體層11、選擇線12(如SSL1~SSL4)、串列15(例如各包括一通道層151包圍一導電層152)和串列接觸17之結構後,係形成包括複數個金屬部18之一圖案化金屬層,且各金屬部18分別對應於該些串列15的各個串列接觸17處,如第3C圖所示。導電孔19係形成於金屬部18上,如第3D圖所示。之後,多條位元線(例如BL1/BL2/…/BL16)係形成於對應的導電孔19 處,而形成如第2圖所示之結構,因而建立串列接觸17和對應位元線之間的電性連接。3B-3D illustrate an embodiment of an electrical connection string contact and a corresponding bit line according to the first embodiment of the present disclosure. Providing a memory layer 11, a selection line 12 (such as SSL1 to SSL4), a series 15 (for example, each including a channel layer 151 surrounding a conductive layer 152) and a series contact 17 as shown in FIG. 3B, A patterned metal layer is included in one of the plurality of metal portions 18, and each of the metal portions 18 corresponds to each of the tandem contacts 17 of the series of columns 15, as shown in FIG. 3C. A conductive hole 19 is formed on the metal portion 18 as shown in Fig. 3D. Thereafter, a plurality of bit lines (for example, BL1/BL2/.../BL16) are formed at the corresponding conductive vias 19 to form a structure as shown in FIG. 2, thereby establishing a series contact 17 and a corresponding bit line. Electrical connection between the two.
一實施 例中,兩相鄰的記憶胞之間,沿著列方向之距離係為一記憶胞x 節距 Px,該些選擇線之一條選擇線係對應m列的記憶胞而設置,n條位元線係對應記憶胞x 節距 Px設置,其中m≧2, 且 m=n。根據第 2 圖(以及之後的第 4和5 圖)所示之結構, m=n=4。In one embodiment, the distance between the two adjacent memory cells along the column direction is a memory cell x pitch Px, and one of the selection lines is set corresponding to the memory cells of the m columns, n The bit line system corresponds to the memory cell x pitch Px setting, where m ≧ 2, and m = n. According to the structure shown in Figure 2 (and subsequent figures 4 and 5), m = n = 4.
根據上述,同一列 (如第一列、第二列…)的記憶胞係電性連接至該些選擇線中之一條選擇線(例如選擇線SSL1 或SSL2或SSL3或SSL4),如第2圖所示。然而本揭露並不以此為限。其它應用中也可以是將至少兩相鄰列的記憶胞電性連接至一條選擇線,如以下實施例所例示。
<第二實施例>According to the above, the memory cell of the same column (such as the first column, the second column, ...) is electrically connected to one of the selection lines (for example, the selection line SSL1 or SSL2 or SSL3 or SSL4), as shown in FIG. 2 Shown. However, this disclosure is not limited to this. In other applications, it is also possible to electrically connect at least two adjacent columns of memory cells to a select line, as exemplified in the following embodiments.
<Second embodiment>
第4圖係為本揭露第二實施例之三維半導體元件之記憶胞設計的上視圖。第二實施例中關於和第一實施例相同之元件請參照第2圖及其說明,在此不再贅述。Fig. 4 is a top view showing the memory cell design of the three-dimensional semiconductor element of the second embodiment. For the components of the second embodiment that are the same as those of the first embodiment, refer to FIG. 2 and its description, and details are not described herein again.
第二實施例和第一實施例之三維半導體元件,其不同之處在於耦接至一選擇線的記憶胞之列數目。在第二實施例中,位於四個相鄰列之記憶胞係耦接至多條選擇線其中之一,例如第4圖中所示之SSL。根據實施例之設計,可以利用較少數目的選擇線進行元件解碼(decoding),如此可簡化製程和擴大製程容許範圍(process window)。
<第三實施例>The second embodiment and the three-dimensional semiconductor component of the first embodiment are different in the number of memory cells coupled to a select line. In a second embodiment, memory cells located in four adjacent columns are coupled to one of a plurality of select lines, such as SSL shown in FIG. Depending on the design of the embodiment, component decoding can be performed with a smaller number of select lines, which simplifies the process and extends the process window.
<Third embodiment>
第5圖係為本揭露第三實施例之三維半導體元件之記憶胞設計的上視圖。第三實施例中關於和第一實施例相同之元件請參照第2圖及其說明,在此不再贅述。Fig. 5 is a top view showing the memory cell design of the three-dimensional semiconductor element of the third embodiment. For the components of the third embodiment that are the same as those of the first embodiment, refer to FIG. 2 and its description, and details are not described herein again.
第三實施例和第一實施例之三維半導體元件,其不同之處在於耦接至一選擇線的記憶胞之列數目。在第三實施例中,位於四個相鄰列之記憶胞係耦接至多條選擇線其中之一。如第5圖所示,位於相鄰之第一列到第四列(Row1~Row4)之記憶胞係電性連接至選擇線SSL1,位於相鄰之第五列到第八列(Row5~Row8)之記憶胞係電性連接至選擇線SSL2。第5圖中元件更具有數個階梯接觸(staircase contacts)22於記憶體層12。根據第三實施例之設計,亦可應用於具有許多階梯接觸的元件,而用來製作選擇線的層則可分區形成多條選擇線於記憶體層12上方,如選擇線SSL1和SSL2。不需要形成許多的選擇線來單獨與每一列之記憶胞相對應。
圖案化金屬層之設計The third embodiment and the three-dimensional semiconductor device of the first embodiment are different in the number of memory cells coupled to a select line. In a third embodiment, the memory cells located in four adjacent columns are coupled to one of the plurality of select lines. As shown in FIG. 5, the memory cell lines located in the adjacent first column to fourth column (Row1~Row4) are electrically connected to the selection line SSL1, and are located in the adjacent fifth column to the eighth column (Row5~Row8). The memory cell is electrically connected to the selection line SSL2. The element in FIG. 5 further has a plurality of step contacts 22 to the memory layer 12. The design according to the third embodiment can also be applied to an element having a plurality of step contacts, and the layer for making the selection line can be partitioned to form a plurality of selection lines above the memory layer 12, such as the selection lines SSL1 and SSL2. There is no need to form a number of selection lines to correspond individually to the memory cells of each column.
Design of patterned metal layer
根據上述第一至第三實施例,圖案化金屬層(為電性連接記憶胞和相應位元線之目的)包括複數個金屬部18,各具有一長方形截面區域。如第2~4圖所示,金屬部18(即長方形的第一部)係部分地遮蓋對應的串列接觸17。然而本揭露並不以此為限。每個金屬部18亦可包括第一部和第二部以全面地遮蓋對應的串列接觸17。金屬部18的其中兩種設計係參照圖示說明如下。但本揭露亦不僅限於此兩種設計態樣。According to the first to third embodiments described above, the patterned metal layer (for the purpose of electrically connecting the memory cells and the corresponding bit lines) includes a plurality of metal portions 18 each having a rectangular cross-sectional area. As shown in Figures 2 to 4, the metal portion 18 (i.e., the first portion of the rectangle) partially covers the corresponding tandem contact 17. However, this disclosure is not limited to this. Each metal portion 18 can also include a first portion and a second portion to completely cover the corresponding tandem contact 17. Two of the designs of the metal portion 18 are described below with reference to the drawings. However, this disclosure is not limited to these two design aspects.
第6A圖係繪示本揭露一實施例之一種矩陣陣列記憶胞中,金屬部之排列與設計係部分地遮蓋對應之串列接觸的示意圖。第6B圖係繪示本揭露另一實施例之一種矩陣陣列記憶胞中,金屬部之排列與設計係完全遮蓋對應之串列接觸的示意圖。FIG. 6A is a schematic diagram showing the arrangement of the metal portions and the design partially covering the corresponding serial contacts in a matrix array memory cell according to an embodiment of the present disclosure. FIG. 6B is a schematic diagram showing the arrangement of the metal portions and the design system completely covering the corresponding serial contacts in a matrix array memory cell according to another embodiment of the present disclosure.
如第6A圖和第6B圖所示,於同一列的該些記憶胞,其相鄰的金屬部18係相互錯開地設置。例如,位於第一行和第三行之金屬部18 係位於對應之記憶胞的上方部分,而位於第二行和第四行之金屬部18 係位於對應之記憶胞的下方部分。再者,經過適當設計和安排,這些金屬部18係獨立設置於對應之記憶胞處而不造成空間上的相互干擾。As shown in FIGS. 6A and 6B, the adjacent metal portions 18 of the memory cells in the same column are arranged offset from each other. For example, the metal portions 18 in the first row and the third row are located in the upper portion of the corresponding memory cell, and the metal portions 18 in the second row and the fourth row are located in the lower portion of the corresponding memory cell. Moreover, after proper design and arrangement, the metal portions 18 are independently disposed at the corresponding memory cells without causing spatial interference.
其中兩相鄰的記憶胞 之間,沿著列方向之一距離係定義為一記憶胞x 節距Px,沿著行方向之一距離係定義為一記憶胞y 節距Py。如第6A圖所示之金屬部18其中之一,其部分地遮蓋對應之記憶胞的串列接觸,係為長方形並具有分別平行於列方向(x-方向)和行方向(y-方向)的一寬度X和一長度Y1,其中X>Px, X< 2Px, and Y1<1/2Py。Among the two adjacent memory cells, one of the distances along the column direction is defined as a memory cell x pitch Px, and one of the distances along the row direction is defined as a memory cell y pitch Py. One of the metal portions 18 as shown in FIG. 6A partially covers the tandem contacts of the corresponding memory cells, is rectangular and has parallel to the column direction (x-direction) and the row direction (y-direction), respectively. A width X and a length Y1, where X>Px, X< 2Px, and Y1<1/2Py.
如第6B圖所示之金屬部18其中之一,其全面地遮蓋對應之記憶胞的串列接觸,係包括一第一部(first part)18a和一第二部(second part)18b連接第一部18a。第一部18a和第二部18b的形狀並不多做限制。第二部18b的形狀例如是半圓形、長方形、正方形或其他不規則形狀。只要第一部18a和第二部18b組合後能全面地遮蓋對應之串列接觸,即為可實施之態樣。因此,雖然在第6B圖中係以半圓形的第二部18b為例做說明,但只要可以遮蓋暴露於第一部18a之外的串列接觸的任何第二部18形狀,都可應用。第一部18 a和第二部18b具有一總長度(overall length)Y2 係平行於行方向,其中Y2> 1/2Py。One of the metal portions 18 as shown in FIG. 6B, which completely covers the serial contact of the corresponding memory cells, includes a first part 18a and a second part 18b. One 18a. The shapes of the first portion 18a and the second portion 18b are not limited. The shape of the second portion 18b is, for example, a semicircle, a rectangle, a square, or other irregular shape. As long as the first portion 18a and the second portion 18b are combined to completely cover the corresponding tandem contact, it is an implementable aspect. Therefore, although the semi-circular second portion 18b is exemplified in FIG. 6B, any shape of the second portion 18 that is exposed to the tandem contact other than the first portion 18a can be applied. . The first portion 18a and the second portion 18b have an overall length Y2 that is parallel to the row direction, where Y2 > 1/2Py.
根據上述實施例之結構,所有的記憶胞可被同時讀取,而可提高操作速度。再者,實施例之三維 半導體元件其頻帶寬度( bandwidth )擴大,功率消耗(power consumption)下降,且讀取記憶胞時相鄰記憶胞之間的干擾亦可減少。
蜂巢狀陣列之記憶胞(Cells in a honeycomb array)According to the configuration of the above embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, the three-dimensional semiconductor device of the embodiment has a wider bandwidth, a lower power consumption, and a smaller interference between adjacent memory cells when the memory cell is read.
Cells in a honeycomb array
在第四、第五和第六實施例中,三維半導體元件中相鄰列及相鄰行的記憶胞係以一蜂巢狀排列。蜂巢狀排列設計可得到更高的記憶胞密度。再者,這些實施例中記憶胞之串列接觸17係直接連接至對應的位元線BLs(不需要形成如第一至第三實施例所述之金屬部18和導電孔19)。根據第四~第六實施例之記憶胞設計,不需要額外製作金屬層(如金屬部18和導電孔19),頻帶寬度可輕易地加倍。
<第四實施例>In the fourth, fifth and sixth embodiments, the memory cells of adjacent columns and adjacent rows in the three-dimensional semiconductor element are arranged in a honeycomb shape. The honeycomb arrangement allows for a higher memory cell density. Furthermore, the tandem contacts 17 of the memory cells in these embodiments are directly connected to the corresponding bit lines BLs (the metal portions 18 and the conductive holes 19 as described in the first to third embodiments are not required to be formed). According to the memory cell design of the fourth to sixth embodiments, it is not necessary to additionally fabricate a metal layer (e.g., the metal portion 18 and the conductive via 19), and the bandwidth can be easily doubled.
<Fourth embodiment>
第7圖係為本揭露第四實施例之三維半導體元件之記憶胞設計的上視圖。請同時參照第1圖之三維半導體元件,其繪示記憶體層11、選擇線12、串列15、串列接觸17和位元線BL等元件。第7圖中,相鄰列(如Row1~Row4)和相鄰行(如Column1~Column8)之記憶胞係排列為一蜂巢狀陣列。Fig. 7 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fourth embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown. In Fig. 7, the memory cell lines of adjacent columns (e.g., Row1~Row4) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array.
根據第四實施例,同一行中相鄰之記憶胞係電性連接至不同的位元線。以第7圖的第1行(Column 1)之記憶胞為例,位於第1列(Row1)和第2列(Row2)的相鄰記憶胞係分別電性連接至位元線BL1和BL2。According to the fourth embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, adjacent memory cell lines located in the first column (Row1) and the second column (Row2) are electrically connected to the bit lines BL1 and BL2, respectively.
再者,第四實施例中,每一條位元線(如 BL1~BL8)係相對應地設置於同一行之記憶胞處。第四實施例中,各串列接觸17之位置係分別對應各記憶胞之中心。再者,一條選擇線係與相鄰兩列之記憶胞相對應。如第7圖所示,選擇線SSL1係對應相鄰之第一列(Row1)和第二列(Row2)之記憶胞,而選擇線SSL2係對應相鄰之第三列(Row3)和第四列(Row4)之記憶胞。Furthermore, in the fourth embodiment, each of the bit lines (e.g., BL1 to BL8) is correspondingly disposed at the memory cell of the same line. In the fourth embodiment, the positions of the tandem contacts 17 correspond to the centers of the respective memory cells. Furthermore, one selection line corresponds to the memory cells of the adjacent two columns. As shown in FIG. 7, the selection line SSL1 corresponds to the memory cells of the adjacent first column (Row1) and the second column (Row2), and the selection line SSL2 corresponds to the adjacent third column (Row3) and the fourth. The memory cell of the column (Row4).
再者,第四實施例中,在同一行之記憶胞的串列接觸17,其相鄰的串列接觸17之中心係未對準地錯開排列(misaligned)。以第7圖的第1行(Column 1)之記憶胞為例,對應第一列(Row1)和第二列(Row2)之相鄰的串列接觸17,其係未對準地錯開設置。Furthermore, in the fourth embodiment, in the tandem contact 17 of the memory cells in the same row, the centers of the adjacent tandem contacts 17 are misaligned misaligned. Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, the adjacent serial column contacts 17 of the first column (Row1) and the second column (Row2) are arranged in a misaligned manner.
再者,對同一行之蜂巢狀陣列記憶胞的串列接觸17來說,至少每相隔一個串列接觸17係沿著行方向(y-方向)排列成一直線。以第7圖的第1行(Column 1)之記憶胞為例,對應第一列(Row1)和第三列(Row3)之串列接觸17係沿著行方向(y-方向)排列成一直線。Furthermore, for the tandem contacts 17 of the honeycomb array cells of the same row, at least one string contact 17 is arranged in a line along the row direction (y-direction). Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, the tandem contacts 17 corresponding to the first column (Row1) and the third column (Row3) are arranged in a line along the row direction (y-direction). .
對蜂巢狀陣列之記憶胞而言,串列接觸17的位置除了可以如第7圖所示之對應各記憶胞之中心,也可以如下所述之偏移記憶胞的中心。
<第五實施例>For the memory cells of the honeycomb array, the position of the tandem contact 17 may be offset from the center of each memory cell as shown in Fig. 7, or may be offset from the center of the memory cell as described below.
<Fifth Embodiment>
第8圖係為本揭露第五實施例之三維半導體元件之記憶胞設計的上視圖。請同時參照第1圖之三維半導體元件,其繪示記憶體層11、選擇線12、串列15、串列接觸17和位元線BL等元件。第8圖中,相鄰列(如Row1~Row4)和相鄰行(如Column1~Column8)之記憶胞係排列為一蜂巢狀陣列。Fig. 8 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fifth embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown. In Fig. 8, the memory cell lines of adjacent columns (e.g., Row1~Row4) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array.
再者,第五實施例中,串列接觸17的位置係偏移對應記憶胞的中心,例如向左偏移和向右偏移。如第8圖所示,對應於同一行(例如第一行或第二行)記憶胞之串列接觸17,每相隔一列(例如第一列Row1和第三列Row3,或是第二列Row2和第四列Row4)的記憶胞之串列接觸17係分別偏移至一左側位置(left position)和一右側位置(right position)。因此,相鄰的兩位元線(例如BL1和BL2)係分別沿著同一行(例如第一行)記憶胞的左側位置和右側位置設置。Furthermore, in the fifth embodiment, the position of the tandem contact 17 is offset corresponding to the center of the memory cell, for example, shifted to the left and offset to the right. As shown in FIG. 8, the serial contacts 17 of the memory cells corresponding to the same row (for example, the first row or the second row) are separated by one column (for example, the first column Row1 and the third column Row3, or the second column Row2). The serial contact 17 of the memory cells of the fourth column Row4) is shifted to a left position and a right position, respectively. Therefore, adjacent two-element lines (for example, BL1 and BL2) are respectively disposed along the left and right positions of the memory cell of the same row (for example, the first row).
根據第五實施例,同一行中相鄰之記憶胞係電性連接至不同的位元線。以第8圖的第1行(Column 1)之記憶胞為例,位於第1列(Row1)和第2列(Row2)的相鄰記憶胞係分別電性連接至位元線BL1和BL2。因此,第五實施例中位元線(如BL1~BL16)的其中兩條位元線的設置係對應同一行之記憶胞。According to the fifth embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row (Column 1) of FIG. 8 as an example, adjacent memory cells located in the first column (Row1) and the second column (Row2) are electrically connected to the bit lines BL1 and BL2, respectively. Therefore, in the fifth embodiment, the setting of two bit lines of the bit lines (eg, BL1 to BL16) corresponds to the memory cells of the same line.
根據第五實施例之設計,不需要額外製作金屬層(如金屬部18和導電孔19),頻帶寬度可輕易地加倍。再者,相較於第四實施例,第五實施例中偏移的串列接觸17可使元件的頻帶寬度加倍。According to the design of the fifth embodiment, it is not necessary to additionally fabricate a metal layer (such as the metal portion 18 and the conductive holes 19), and the bandwidth can be easily doubled. Furthermore, compared to the fourth embodiment, the offset series contact 17 in the fifth embodiment can double the bandwidth of the element.
再者,第五實施例中,在同一行之記憶胞的串列接觸17,其相鄰的串列接觸17之中心係未對準地錯開排列(misaligned)。以第8圖的第1行(Column 1)之記憶胞為例,對應第一列(Row1)和第二列(Row2)之相鄰的串列接觸17係未對準地錯開設置。Furthermore, in the fifth embodiment, the tandem contacts 17 of the memory cells in the same row are misaligned in the center of the adjacent tandem contacts 17 in a misaligned manner. Taking the memory cell of the first row (Column 1) of FIG. 8 as an example, adjacent column contacts 17 corresponding to the first column (Row1) and the second column (Row2) are misaligned and arranged.
再者,第五實施例中,相鄰四列(如Row1~Row4)之記憶胞係經由串列接觸17而電性連接至該些選擇線的其中一條選擇線(如SSL1)。
<第六實施例>Furthermore, in the fifth embodiment, the memory cells of the adjacent four columns (such as Row1~Row4) are electrically connected to one of the selection lines (such as SSL1) via the serial contact 17.
<Sixth embodiment>
第9圖係為本揭露第六實施例之三維半導體元件之記憶胞設計的上視圖。第9圖中,相鄰列(例如Row1~Row8)和相鄰行(例如Column1~Column8)之記憶胞係排列為一蜂巢狀陣列。第六實施例中關於和第五實施例相同之元件請參照第8圖及其說明。Fig. 9 is a top view showing the memory cell design of the three-dimensional semiconductor element of the sixth embodiment. In Fig. 9, the memory cell lines of adjacent columns (e.g., Row1~Row8) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array. For the components of the sixth embodiment which are the same as those of the fifth embodiment, please refer to Fig. 8 and its description.
第六實施例和第五實施例相同之元素及其特點,例如串列接觸17的偏移位置;同一行記憶胞中相鄰之串列接觸17係錯開設置;同一行之相鄰記憶胞係電性連接至不同的位元線;兩條位元線係對應同一行之記憶胞設置,其相關敘述與細節說明請參照第五實施例之說明,在此不再贅述。The same elements and features of the sixth embodiment and the fifth embodiment, such as the offset position of the tandem contact 17; adjacent series of contacts 17 in the same row of memory cells are staggered; adjacent memory cells of the same row For the description of the related description and the detailed description, refer to the description of the fifth embodiment, and the details are not described herein again.
第五實施例和第六實施例之元件分別繪示排成四列和八列之記憶胞。類似於第五實施例,第六實施例中相鄰四列(如Row1~Row4)之記憶胞係電性連接至一條選擇線;例如第一列至第四列之記憶胞電性連接至選擇線SSL1,第五列至第八列之記憶胞電性連接至選擇線SSL2。根據實施例之設計,可以利用較少數目的選擇線進行元件解碼(decoding),如此可簡化製程和擴大製程容許範圍(process window)。The elements of the fifth embodiment and the sixth embodiment respectively show memory cells arranged in four columns and eight columns. Similar to the fifth embodiment, in the sixth embodiment, the memory cells of adjacent four columns (such as Row1~Row4) are electrically connected to one selection line; for example, the memory cells of the first column to the fourth column are electrically connected to the selection. The line SSL1, the memory of the fifth to eighth columns is electrically connected to the selection line SSL2. Depending on the design of the embodiment, component decoding can be performed with a smaller number of select lines, which simplifies the process and extends the process window.
再者,第六實施例中,對同一行之蜂巢狀陣列記憶胞的串列接觸17來說,每相隔三個串列接觸17係沿著行方向(y-方向)排列成一直線。以第9圖的第1行(Column 1)之記憶胞為例,對應第一列(Row1)和第五列(Row5)之串列接觸17係沿著行方向(y-方向)排列成一直線。Furthermore, in the sixth embodiment, for the tandem contacts 17 of the honeycomb-like array memory cells of the same row, the three series of contacts 17 are arranged in a line along the row direction (y-direction) in a straight line. Taking the memory cell of the first row (Column 1) of FIG. 9 as an example, the tandem contacts 17 corresponding to the first column (Row1) and the fifth column (Row5) are arranged in a line along the row direction (y-direction). .
第六實施例中,如第9圖所示,根據串列接觸17的位置,對應於同一行記憶胞的串列接觸17可區分為兩個群組,對同一行如第一行之記憶胞來說,對應第一列(Row1)、第五列(Row5) (和第九列…)之串列接觸17係構成第一群組,其中第一行(Column 1)記憶胞之第一群組的串列接觸17係對應一位置1a並沿著線L1a排列。再者,對第一行(Column 1)記憶胞,對應第三列(Row3)、第七列(Row7) (和第十一列…)之串列接觸17係構成第二群組,其中第一行(Column 1)記憶胞之第二群組的串列接觸17係對應一位置1b並沿著線L1b排列。對第二行(Column 2)之記憶胞,對應第二列(Row2)、第六列(Row6) (和第十列…)之串列接觸17係構成第二行之第一群組,其中第二行記憶胞之第一群組的串列接觸17係對應一位置2a並沿著線L2a排列;再者,對應第四列(Row4)、第八列(Row8) (和第十二列…)之串列接觸17係構成第二行之第二群組,其中第二行記憶胞之第二群組的串列接觸17係對應一位置2b並沿著線L2b排列。如第9圖所示,線L1a和線L2a(a-位置)係偏移至記憶胞中心之左側,而線L1b和線L2b(b-位置)係偏移至記憶胞中心之右側。對應記憶胞的位元線(第9圖省略未繪示)係對應線L1a、線L2a、線L1b、線L2b… 等設置。In the sixth embodiment, as shown in Fig. 9, according to the position of the tandem contact 17, the tandem contacts 17 corresponding to the same row of memory cells can be divided into two groups, for the same row as the first row of memory cells. In other words, the tandem contacts 17 corresponding to the first column (Row1), the fifth column (Row5) (and the ninth column...) constitute a first group, wherein the first group of the first row (Column 1) memory cells The set of series contacts 17 corresponds to a position 1a and is arranged along line L1a. Furthermore, for the first row (Column 1) memory cell, the tandem contact 17 corresponding to the third column (Row3) and the seventh column (Row7) (and the eleventh column...) constitutes a second group, wherein The tandem contacts 17 of the second group of one row (Column 1) memory cells correspond to a position 1b and are arranged along line L1b. For the memory cells of the second row (Column 2), the tandem contacts 17 corresponding to the second column (Row2), the sixth column (Row6) (and the tenth column...) constitute the first group of the second row, wherein The tandem contacts 17 of the first group of memory cells of the second row correspond to a position 2a and are arranged along the line L2a; further, corresponding to the fourth column (Row4), the eighth column (Row8) (and the twelfth column) The series of contacts 17 of the ... constitute a second group of the second row, wherein the tandem contacts 17 of the second group of second rows of memory cells correspond to a position 2b and are arranged along line L2b. As shown in Fig. 9, the line L1a and the line L2a (a-position) are shifted to the left of the center of the memory cell, and the line L1b and the line L2b (b-position) are shifted to the right of the center of the memory cell. The bit line corresponding to the memory cell (not shown in FIG. 9) is set corresponding to the line L1a, the line L2a, the line L1b, the line L2b, and the like.
根據第四到第六實施例之元件,其記憶胞排列為一蜂巢狀陣列,相鄰列和行的記憶胞具有重疊區域,例如第一列(Row1)第一行(Column 1)之記憶胞其導電層152之右側邊緣係與第二列(Row 2)第二行(C olumn 2)之記憶胞其導電層152之左側邊緣重疊(第9圖),係給予應用元件可省略製作如第一~第三實施例之金屬部18和導電孔19的機會。因此,如第四、第五或第六實施例所提出之元件,其頻帶寬度可更容易地加倍。According to the elements of the fourth to sixth embodiments, the memory cells are arranged in a honeycomb array, and the memory cells of adjacent columns and rows have overlapping regions, for example, the memory cells of the first row (Column 1) of the first column (Row1). The right edge of the conductive layer 152 overlaps with the left edge of the conductive layer 152 of the memory cell 152 of the second row (Row 2) of the second row (Fig. 9), and the application component can be omitted. Opportunities for the metal portion 18 and the conductive holes 19 of the first to third embodiments. Therefore, as the element proposed in the fourth, fifth or sixth embodiment, the bandwidth can be more easily doubled.
再者,雖然第9圖係繪示兩條位元線對應同一行之記憶胞設置(例如分別對應第一行記憶胞之線L1a和L1b設置),但本揭露並不以此為限。對應同一行記憶胞所設置的位元線數目可以設計超過兩條(如3, 4, 5.. 條),係可應用條件所需、成本限制和/或元件性能而定。Furthermore, although the ninth figure shows the memory cell settings of the two rows corresponding to the same row (for example, the lines L1a and L1b corresponding to the first row of memory cells respectively), the disclosure is not limited thereto. The number of bit lines set for the same row of memory cells can be designed to be more than two (eg, 3, 4, 5.), depending on the required conditions, cost constraints, and/or component performance.
再者,如第8圖和第9圖所示之串列接觸17其形狀為橢圓形,但本揭露對於串列接觸17的形狀並不特別限制。串列接觸17之形狀可以是圓形、橢圓形、長方形或其他形狀。第10A圖繪示本揭露一實施例之一橢圓形串列接觸的示意圖。第10B圖繪示本揭露一實施例之一 長方形串列接觸的示意圖。如第10A圖所示,具橢圓形截面的一串列接觸具有平行於列方向(x-方向)的一寬度Xc和平行於行方向(y-方向)的一長度Yc,其中Yc>Xc,或Yc>2Xc。如第10B圖所示,具長方形截面的一串列接觸具有一寬度Xc和一長度Yc,其中Yc>Xc,或Yc>2Xc。Further, the tandem contact 17 as shown in Figs. 8 and 9 has an elliptical shape, but the present disclosure is not particularly limited with respect to the shape of the tandem contact 17. The shape of the tandem contact 17 can be circular, elliptical, rectangular or other shape. FIG. 10A is a schematic diagram showing an elliptical tandem contact of an embodiment of the present disclosure. FIG. 10B is a schematic view showing a rectangular string contact according to an embodiment of the present disclosure. As shown in FIG. 10A, a series of contacts having an elliptical cross section has a width Xc parallel to the column direction (x-direction) and a length Yc parallel to the row direction (y-direction), where Yc>Xc, Or Yc>2Xc. As shown in FIG. 10B, a series of contacts having a rectangular cross section has a width Xc and a length Yc, where Yc>Xc, or Yc>2Xc.
根據上述實施例所揭露之內容,其所繪示之細部結構和說明係為敘述之用,而本揭 露並不僅限制在上述結構。因此,相關領域之技藝者可知,上述實施例所提出之構造和設計皆可根據應用之實際需求而做適當修飾和調整。根據上述實施例所揭露之三維半導體元件結構,所有的記憶胞可被同時讀取,而可提高操作速度。再者,實施例之三維半導體元件其頻帶寬度( bandwidth )擴大,功率消耗下降,且讀取記憶胞時相鄰記憶胞之間的干擾亦可減少。The detailed construction and description of the above embodiments are for the purpose of description, and the disclosure is not limited to the above structures. Therefore, those skilled in the relevant art can understand that the configurations and designs proposed in the above embodiments can be appropriately modified and adjusted according to the actual needs of the application. According to the three-dimensional semiconductor device structure disclosed in the above embodiments, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, the three-dimensional semiconductor device of the embodiment has a wider bandwidth, a lower power consumption, and a smaller interference between adjacent memory cells when the memory cell is read.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
11‧‧‧記憶體層 11‧‧‧ memory layer
SSL1~SSL4‧‧‧選擇線 SSL1~SSL4‧‧‧ selection line
15‧‧‧串列 15‧‧‧Listing
151‧‧‧通道層 151‧‧‧channel layer
152‧‧‧導電層 152‧‧‧ Conductive layer
17‧‧‧串列接觸 17‧‧‧ Serial contact
18‧‧‧金屬部 18‧‧‧Metal Department
19‧‧‧導電孔 19‧‧‧Electrical hole
BL1~BL16‧‧‧位元線 BL1~BL16‧‧‧ bit line
Row1~Row4‧‧‧記憶胞列 Row1~Row4‧‧‧ memory cell
Column1~Column4‧‧‧記憶胞行 Column1~Column4‧‧‧ memory cell line
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