TWI538167B - Three-dimensional semiconductor device - Google Patents

Description

Three-dimensional semiconductor component 【0001】

The present invention relates to a three-dimensional semiconductor component, and more particularly to a vertically operated three-dimensional semiconductor component that operates rapidly.

【0002】

A very important feature of non-volatile memory components is the ability to preserve the integrity of the data state when the memory component loses or removes power. Many different types of non-volatile memory components have been proposed in the industry. However, related companies continue to develop new designs or combine existing technologies to stack memory cells with memory cells to achieve a memory structure with higher storage capacity. For example, some NAND type flash memory structures have been proposed for multilayer thin film transistor stacks. Related companies have proposed three-dimensional memory components of various structures, such as memory cells with single-gate, double-gate memory cells, and memory cells of a surrounding gate. And other three-dimensional memory components.

[0003]

It is hoped by the relevant designers that a three-dimensional memory structure can be constructed, which not only has many layer stacking planes (memory layers) but also achieves higher storage capacity and superior electronic characteristics (for example, good data storage reliability and operation). Speed), so that the memory structure can be stabilized and fast as operations such as erasing and programming. Furthermore, the page size of the NAND type flash memory is proportional to the number of bit lines. Therefore, when the component size is reduced, not only the cost is reduced, but the parallel operation increases the read/write speed of the component, thereby achieving a higher data transmission speed. Taking a general three-dimensional vertical channel type memory element as an example, it has a larger through-hole size to reduce the difficulty in the process. But larger memory cell sizes result in fewer bit line numbers, less parallel operations, and slower data read and write speeds. In the traditional memory cell design, the memory cells of the same column are generally selected by one selection line, and the memory cells of the same row correspond to one bit line. It is arranged in 4 rows and 4 columns with 16 cell strings, and has 4 bit lines as an example and 4 selection lines, and each memory cell string corresponds to one bit line and one selection. Line (eg SSL 1/2/3/4). To read all the data of the memory cell, select the four serial data of the column of the selection line SSL1, and then select the selection lines SSL2, SSL 3 and SSL 4 to obtain another 12 serial data. It must be cycled 4 times, and all the serial data can be read by selecting the selection line SSL 1/2/3/4. Moreover, when the selection line SSL1 is selected and operated, the memory cell strings of the other corresponding selection lines SSL 2/3/4 are also applied with the same gate bias, and the gate is disturbed. In addition, non-selected strings also have a gate bias indicating the presence of unwanted power consumption. Therefore, the traditional memory cell design not only has a lower operating speed, but also has greater power consumption and interference.

[0004]

The present invention is directed to a three-dimensional semiconductor component. According to the three-dimensional semiconductor element of the embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, according to the three-dimensional semiconductor device of the embodiment, the bandwidth is enlarged, the power consumption is lowered, and the interference between adjacent memory cells when the memory cell is read can be reduced.

[0005]

According to an embodiment, a three-dimensional semiconductor device is provided, comprising: a plurality of memory layers stacked vertically on a substrate and the memory layers are parallel to each other; a plurality of selection lines are located above the memory layer, and The selection lines are parallel to each other; a plurality of bit lines are located above the selection line, and the bit lines are parallel to each other and perpendicular to the selection line; the plurality of strings are perpendicular to the memory layer and the selection line, and The strings are electrically connected to the corresponding selection lines; the plurality of cells are defined by the series, the selection line and the bit line, respectively, and the memory cells are arranged in a plurality of rows and a plurality of rows. (columns), wherein the bit line is parallel to a column direction, and the selection line is parallel to a row direction. The adjacent memory cells in the same row are electrically connected to different bit lines.

[0006]

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

[0060]

10‧‧‧Substrate

11‧‧‧ memory layer

12, 13, SSL, SSL1~SSL4‧‧‧ selection line

15‧‧‧Listing

151‧‧‧channel layer

152‧‧‧ Conductive layer

17‧‧‧ Serial contact

18‧‧‧Metal Department

18a‧‧‧ first

18b‧‧‧ second

19‧‧‧Electrical hole

22‧‧‧Step contact

BL, BL1~BL16‧‧‧ bit line

Row1~Row8‧‧‧ memory cell

Column1~Column8‧‧‧ memory cell line

L _upper ‧‧‧On the straight line

L _lower ‧‧‧Lower straight

Px‧‧‧ memory cell x pitch

Py‧‧‧ memory cell y pitch

X ‧‧‧The width of a metal part

Y1‧‧‧The length of a metal part

Y2‧‧‧ The total length of the first and second parts of a metal department

1a, 1b, 2a, 2b‧‧‧ position

L1a‧‧‧ corresponds to the line 1a of the first line of memory cells

L1b‧‧‧ corresponds to the line 1b of the first line of memory cells

L2a‧‧‧ corresponds to the line 2a of the second line of memory cells

L2b‧‧‧ corresponds to the line 2b of the second line of memory cells

Xc‧‧‧The width of a series of contacts

Yc‧‧‧ The length of a series of contacts

【0007】

Figure 1 is a perspective view of a three-dimensional semiconductor component.

Fig. 2 is a top view showing the memory cell design of the three-dimensional semiconductor element of the first embodiment.

FIG. 3A is a schematic diagram showing a tandem contact arrangement of a matrix array memory cell according to the first embodiment of the present disclosure.

3B-3D illustrate an embodiment of an electrical connection string contact and a corresponding bit line according to the first embodiment of the present disclosure.

Fig. 4 is a top view showing the memory cell design of the three-dimensional semiconductor element of the second embodiment.

Fig. 5 is a top view showing the memory cell design of the three-dimensional semiconductor element of the third embodiment.

FIG. 6A is a schematic diagram showing the arrangement of the metal portions and the design partially covering the corresponding serial contacts in a matrix array memory cell according to an embodiment of the present disclosure.

FIG. 6B is a schematic diagram showing the arrangement of the metal portions and the design system completely covering the corresponding serial contacts in a matrix array memory cell according to another embodiment of the present disclosure.

Fig. 7 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fourth embodiment.

Fig. 8 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fifth embodiment.

Fig. 9 is a top view showing the memory cell design of the three-dimensional semiconductor element of the sixth embodiment.

FIG. 10A is a schematic diagram showing an elliptical tandem contact of an embodiment of the present disclosure.

FIG. 10B is a schematic diagram showing a rectangular string contact according to an embodiment of the present disclosure.

[0008]

Embodiments of the present disclosure propose a fast-operating three-dimensional semiconductor component, such as a vertical-channel (VC) three-dimensional semiconductor component. According to the three-dimensional semiconductor element of the embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, according to the three-dimensional semiconductor device of the embodiment, the bandwidth is increased (increased), the power consumption is lowered, and the interference between adjacent memory cells when the memory cell is read can be reduced.

【0009】

The present disclosure is applicable to three-dimensional semiconductor components such as vertical-channel (VC) three-dimensional semiconductor components of a plurality of different memory cell arrangements. Figure 1 is a perspective view of a three-dimensional semiconductor component. A three-dimensional semiconductor component includes a plurality of memory layers 11 (including control gates) stacked vertically on a substrate 10, and the memory layers 11 are parallel to each other; a plurality of selection lines 12 are located in the memory Above the body layer 11 and the selection lines 12 are parallel to each other; a plurality of strings 15 are perpendicular to the memory layer 11 and the selection line 12, and the series 15 are electrically connected to the corresponding selection lines 12 a plurality of bit lines BLs are located above the selection line 12, and the bit lines BLs are parallel to each other and perpendicular to the selection line 12; a plurality of cells are respectively arranged by the series 15 The selection lines 12 and the bit lines BLs are defined, and the memory cell lines are arranged in a plurality of rows and a plurality of columns, wherein the bit lines BLs are selected in parallel with a column direction. Line 12 is parallel to a row direction. Furthermore, a plurality of string contacts 17 are perpendicular to the memory layer 11 and the selection line 12, and the arrangement of each string of contacts 17 corresponds to each column 15 of the memory cells, wherein the series contacts 17 are electrically The connection is made to the corresponding selection line 12 and the corresponding bit line BL. The three-dimensional semiconductor component further includes other components. For example, the select line 12 refers to an upper select line (upper SG), and the memory layer 11 has a lower select line (lower SG) 13 formed below.

[0010]

According to an embodiment of the present disclosure, adjacent memory cells in the same row of the three-dimensional semiconductor component are electrically connected to different bit lines.

[0011]

Two kinds of application examples are proposed below, for example, the memory cells in the three-dimensional semiconductor component are arranged in a matrix array (ie, the memory cells of adjacent columns and adjacent rows are arranged in a matrix form), or the memory cells are arranged. The description of the embodiments of the present disclosure is made for a honeycomb array (i.e., memory cells of adjacent columns and adjacent rows are arranged in a misaligned (misaligned) form). However, the disclosure is not limited to the arrangement of the two memory cells.

[0012]

According to the first, second and third embodiments, the memory cells of adjacent columns and adjacent rows are arranged in a matrix (i.e., a matrix array). According to the fourth, fifth and sixth embodiments, the memory cells of adjacent columns and adjacent rows are arranged in a honeycomb array. The detailed structure described in the embodiments is for illustrative purposes and is not intended to limit the scope of the disclosure.

[0013]

The following embodiments describe the related structures and processes of the present disclosure with reference to the accompanying drawings, but the disclosure is not limited thereto. The same or similar elements in the embodiments are denoted by the same or similar reference numerals. It should be noted that the disclosure does not show all possible embodiments. Other implementations not presented in this disclosure may also be applicable. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.
Cells in a matrix array

[0014]

In the first, second and third embodiments, the memory cells of adjacent columns and adjacent rows in the three-dimensional semiconductor element are arranged in a matrix form (hence the order of a matrix array). Moreover, in the embodiment, the serial contact 17 of the memory cell is electrically connected to the corresponding bit line BLs through a patterned metal layer and a plurality of conductive vias.
<First Embodiment>

[0015]

Fig. 2 is a top view showing the memory cell design of the three-dimensional semiconductor element of the first embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown.

[0016]

A plurality of cells are defined by the string 15, the selection line 12, and the bit line BLs, respectively, and the memory cells are arranged in a matrix array. According to an embodiment, the memory cell lines are arranged in a plurality of rows and a plurality of columns, wherein the rows (the row direction is along the x direction) are parallel to the bit line BL (eg, BL1 to BL16), and The columns (the column direction is along the y direction) are parallel to the select line (eg, SSL1~SSL4). Each of the strings of the memory cells includes, for example, a channel layer 151 surrounding a conductive layer 152 for illustration of an embodiment. However, this disclosure is not limited to this.

[0017]

According to the first embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row of FIG. 2 as an example, the adjacent memory cell lines located in the first column and the second column are electrically connected to the bit lines BL1 and BL2, respectively.

[0018]

Furthermore, in the first embodiment, the four bit lines are correspondingly disposed in the memory cells in the same row. Taking the memory cell of the first row of Fig. 2 as an example, the four bit lines BL1 to BL4 are correspondingly located at the memory cells of the first row.

[0019]

Moreover, in the first embodiment, the position of the tandem contact 17 is offset from the center of the corresponding memory cell string 15. As shown in FIG. 2, the position of the tandem contact 17 corresponds to an upper portion or a lower portion of the string 15.

[0020]

Furthermore, in the first embodiment, the tandem contacts 17 of the memory cells of the same column, the adjacent series contacts 17 are misaligned in a misaligned manner. Taking the memory cell of the first column of Fig. 2 as an example, the adjacent series of contacts 17 located in the first row and the second row are misaligned and arranged in a staggered manner.

[0021]

Furthermore, the tandem contacts 17 (e.g., the tandem contacts 17 in the first row and the third row) that are spaced apart from each other by the tandem contacts 17 of the memory cells of the same column are arranged in a line along the column direction. Please refer to FIG. 3A, which is a schematic diagram showing a tandem contact arrangement of a matrix array memory cell according to the first embodiment of the present disclosure. The tandem contacts 17 corresponding to the memory cells of the same column are arranged along the column direction (ie, the x direction) into a first straight line (eg, an upper straight line L _upper ) and a second straight line (eg, a lower straight line L _lower ), and A straight line is located at an upper portion corresponding to the series 15 and a second line is located at a lower portion corresponding to the series. Therefore, according to the position of the tandem contact 17, the serial contact 17 of the memory cell corresponding to the same column can be divided into two groups, the first group and the second group are respectively composed of odd lines (such as the first line, The third line...) consists of a series of contacts 17 of even lines (such as the second line, the fourth line...). The tandem contacts 17 of the odd rows are arranged along the upper straight line L _upper , and the tandem contacts 17 of the even rows are arranged along the lower straight line L _lower .

[0022]

Furthermore, in the first embodiment, the serial contact 17 corresponding to the same column of memory cells (Row1, or Row2, or Row3 or Row4) is electrically connected to one of the selection lines, for example, the selection line SSL1 or SSL2. Or SSL3 or SSL4, as shown in Figure 2. However, this disclosure is not limited to this. In other embodiments, at least two adjacent columns of tandem contacts 17, such as adjacent four columns of tandem contacts 17, are electrically connected to a select line (as described in the second and third embodiments that follow) .

[0023]

Furthermore, the memory cells of the matrix array according to the first embodiment are electrically connected to the series of contacts 17 through a patterned metal layer and a plurality of conductive vias 19. Corresponding to these bit lines (for example, BL1/BL2/.../BL16), as shown in FIG. The patterned metal layer includes a plurality of metal portions 18 respectively formed at the corresponding serial contacts 17 of the memory cells, and the conductive holes 19 are formed on the metal portions 18 to be electrically connected. To the corresponding bit line (for example, BL1/BL2/.../BL16).

[0024]

3B-3D illustrate an embodiment of an electrical connection string contact and a corresponding bit line according to the first embodiment of the present disclosure. Providing a memory layer 11, a selection line 12 (such as SSL1 to SSL4), a series 15 (for example, each including a channel layer 151 surrounding a conductive layer 152) and a series contact 17 as shown in FIG. 3B, A patterned metal layer is included in one of the plurality of metal portions 18, and each of the metal portions 18 corresponds to each of the tandem contacts 17 of the series of columns 15, as shown in FIG. 3C. A conductive hole 19 is formed on the metal portion 18 as shown in Fig. 3D. Thereafter, a plurality of bit lines (for example, BL1/BL2/.../BL16) are formed at the corresponding conductive vias 19 to form a structure as shown in FIG. 2, thereby establishing a series contact 17 and a corresponding bit line. Electrical connection between the two.

[0025]

In one embodiment, the distance between the two adjacent memory cells along the column direction is a memory cell x pitch Px, and one of the selection lines is set corresponding to the memory cells of the m columns, n The bit line system corresponds to the memory cell x pitch Px setting, where m ≧ 2, and m = n. According to the structure shown in Figure 2 (and subsequent figures 4 and 5), m = n = 4.

[0026]

According to the above, the memory cell of the same column (such as the first column, the second column, ...) is electrically connected to one of the selection lines (for example, the selection line SSL1 or SSL2 or SSL3 or SSL4), as shown in FIG. 2 Shown. However, this disclosure is not limited to this. In other applications, it is also possible to electrically connect at least two adjacent columns of memory cells to a select line, as exemplified in the following embodiments.
<Second embodiment>

[0027]

Fig. 4 is a top view showing the memory cell design of the three-dimensional semiconductor element of the second embodiment. For the components of the second embodiment that are the same as those of the first embodiment, refer to FIG. 2 and its description, and details are not described herein again.

[0028]

The second embodiment and the three-dimensional semiconductor component of the first embodiment are different in the number of memory cells coupled to a select line. In a second embodiment, memory cells located in four adjacent columns are coupled to one of a plurality of select lines, such as SSL shown in FIG. Depending on the design of the embodiment, component decoding can be performed with a smaller number of select lines, which simplifies the process and extends the process window.
<Third embodiment>

[0029]

Fig. 5 is a top view showing the memory cell design of the three-dimensional semiconductor element of the third embodiment. For the components of the third embodiment that are the same as those of the first embodiment, refer to FIG. 2 and its description, and details are not described herein again.

[0030]

The third embodiment and the three-dimensional semiconductor device of the first embodiment are different in the number of memory cells coupled to a select line. In a third embodiment, the memory cells located in four adjacent columns are coupled to one of the plurality of select lines. As shown in FIG. 5, the memory cell lines located in the adjacent first column to fourth column (Row1~Row4) are electrically connected to the selection line SSL1, and are located in the adjacent fifth column to the eighth column (Row5~Row8). The memory cell is electrically connected to the selection line SSL2. The element in FIG. 5 further has a plurality of step contacts 22 to the memory layer 12. The design according to the third embodiment can also be applied to an element having a plurality of step contacts, and the layer for making the selection line can be partitioned to form a plurality of selection lines above the memory layer 12, such as the selection lines SSL1 and SSL2. There is no need to form a number of selection lines to correspond individually to the memory cells of each column.
Design of patterned metal layer

[0031]

According to the first to third embodiments described above, the patterned metal layer (for the purpose of electrically connecting the memory cells and the corresponding bit lines) includes a plurality of metal portions 18 each having a rectangular cross-sectional area. As shown in Figures 2 to 4, the metal portion 18 (i.e., the first portion of the rectangle) partially covers the corresponding tandem contact 17. However, this disclosure is not limited to this. Each metal portion 18 can also include a first portion and a second portion to completely cover the corresponding tandem contact 17. Two of the designs of the metal portion 18 are described below with reference to the drawings. However, this disclosure is not limited to these two design aspects.

[0032]

FIG. 6A is a schematic diagram showing the arrangement of the metal portions and the design partially covering the corresponding serial contacts in a matrix array memory cell according to an embodiment of the present disclosure. FIG. 6B is a schematic diagram showing the arrangement of the metal portions and the design system completely covering the corresponding serial contacts in a matrix array memory cell according to another embodiment of the present disclosure.

[0033]

As shown in FIGS. 6A and 6B, the adjacent metal portions 18 of the memory cells in the same column are arranged offset from each other. For example, the metal portions 18 in the first row and the third row are located in the upper portion of the corresponding memory cell, and the metal portions 18 in the second row and the fourth row are located in the lower portion of the corresponding memory cell. Moreover, after proper design and arrangement, the metal portions 18 are independently disposed at the corresponding memory cells without causing spatial interference.

[0034]

Among the two adjacent memory cells, one of the distances along the column direction is defined as a memory cell x pitch Px, and one of the distances along the row direction is defined as a memory cell y pitch Py. One of the metal portions 18 as shown in FIG. 6A partially covers the tandem contacts of the corresponding memory cells, is rectangular and has parallel to the column direction (x-direction) and the row direction (y-direction), respectively. A width X and a length Y1, where X>Px, X< 2Px, and Y1<1/2Py.

[0035]

One of the metal portions 18 as shown in FIG. 6B, which completely covers the serial contact of the corresponding memory cells, includes a first part 18a and a second part 18b. One 18a. The shapes of the first portion 18a and the second portion 18b are not limited. The shape of the second portion 18b is, for example, a semicircle, a rectangle, a square, or other irregular shape. As long as the first portion 18a and the second portion 18b are combined to completely cover the corresponding tandem contact, it is an implementable aspect. Therefore, although the semi-circular second portion 18b is exemplified in FIG. 6B, any shape of the second portion 18 that is exposed to the tandem contact other than the first portion 18a can be applied. . The first portion 18a and the second portion 18b have an overall length Y2 that is parallel to the row direction, where Y2 > 1/2Py.

[0036]

According to the configuration of the above embodiment, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, the three-dimensional semiconductor device of the embodiment has a wider bandwidth, a lower power consumption, and a smaller interference between adjacent memory cells when the memory cell is read.
Cells in a honeycomb array

[0037]

In the fourth, fifth and sixth embodiments, the memory cells of adjacent columns and adjacent rows in the three-dimensional semiconductor element are arranged in a honeycomb shape. The honeycomb arrangement allows for a higher memory cell density. Furthermore, the tandem contacts 17 of the memory cells in these embodiments are directly connected to the corresponding bit lines BLs (the metal portions 18 and the conductive holes 19 as described in the first to third embodiments are not required to be formed). According to the memory cell design of the fourth to sixth embodiments, it is not necessary to additionally fabricate a metal layer (e.g., the metal portion 18 and the conductive via 19), and the bandwidth can be easily doubled.
<Fourth embodiment>

[0038]

Fig. 7 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fourth embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown. In Fig. 7, the memory cell lines of adjacent columns (e.g., Row1~Row4) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array.

[0039]

According to the fourth embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, adjacent memory cell lines located in the first column (Row1) and the second column (Row2) are electrically connected to the bit lines BL1 and BL2, respectively.

[0040]

Furthermore, in the fourth embodiment, each of the bit lines (e.g., BL1 to BL8) is correspondingly disposed at the memory cell of the same line. In the fourth embodiment, the positions of the tandem contacts 17 correspond to the centers of the respective memory cells. Furthermore, one selection line corresponds to the memory cells of the adjacent two columns. As shown in FIG. 7, the selection line SSL1 corresponds to the memory cells of the adjacent first column (Row1) and the second column (Row2), and the selection line SSL2 corresponds to the adjacent third column (Row3) and the fourth. The memory cell of the column (Row4).

[0041]

Furthermore, in the fourth embodiment, in the tandem contact 17 of the memory cells in the same row, the centers of the adjacent tandem contacts 17 are misaligned misaligned. Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, the adjacent serial column contacts 17 of the first column (Row1) and the second column (Row2) are arranged in a misaligned manner.

[0042]

Furthermore, for the tandem contacts 17 of the honeycomb array cells of the same row, at least one string contact 17 is arranged in a line along the row direction (y-direction). Taking the memory cell of the first row (Column 1) of FIG. 7 as an example, the tandem contacts 17 corresponding to the first column (Row1) and the third column (Row3) are arranged in a line along the row direction (y-direction). .

[0043]

For the memory cells of the honeycomb array, the position of the tandem contact 17 may be offset from the center of each memory cell as shown in Fig. 7, or may be offset from the center of the memory cell as described below.
<Fifth Embodiment>

[0044]

Fig. 8 is a top view showing the memory cell design of the three-dimensional semiconductor element of the fifth embodiment. Referring to the three-dimensional semiconductor device of FIG. 1 at the same time, elements such as the memory layer 11, the selection line 12, the string 15, the tandem contact 17, and the bit line BL are shown. In Fig. 8, the memory cell lines of adjacent columns (e.g., Row1~Row4) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array.

[0045]

Furthermore, in the fifth embodiment, the position of the tandem contact 17 is offset corresponding to the center of the memory cell, for example, shifted to the left and offset to the right. As shown in FIG. 8, the serial contacts 17 of the memory cells corresponding to the same row (for example, the first row or the second row) are separated by one column (for example, the first column Row1 and the third column Row3, or the second column Row2). The serial contact 17 of the memory cells of the fourth column Row4) is shifted to a left position and a right position, respectively. Therefore, adjacent two-element lines (for example, BL1 and BL2) are respectively disposed along the left and right positions of the memory cell of the same row (for example, the first row).

[0046]

According to the fifth embodiment, adjacent memory cells in the same row are electrically connected to different bit lines. Taking the memory cell of the first row (Column 1) of FIG. 8 as an example, adjacent memory cells located in the first column (Row1) and the second column (Row2) are electrically connected to the bit lines BL1 and BL2, respectively. Therefore, in the fifth embodiment, the setting of two bit lines of the bit lines (eg, BL1 to BL16) corresponds to the memory cells of the same line.

[0047]

According to the design of the fifth embodiment, it is not necessary to additionally fabricate a metal layer (such as the metal portion 18 and the conductive holes 19), and the bandwidth can be easily doubled. Furthermore, compared to the fourth embodiment, the offset series contact 17 in the fifth embodiment can double the bandwidth of the element.

[0048]

Furthermore, in the fifth embodiment, the tandem contacts 17 of the memory cells in the same row are misaligned in the center of the adjacent tandem contacts 17 in a misaligned manner. Taking the memory cell of the first row (Column 1) of FIG. 8 as an example, adjacent column contacts 17 corresponding to the first column (Row1) and the second column (Row2) are misaligned and arranged.

[0049]

Furthermore, in the fifth embodiment, the memory cells of the adjacent four columns (such as Row1~Row4) are electrically connected to one of the selection lines (such as SSL1) via the serial contact 17.
<Sixth embodiment>

[0050]

Fig. 9 is a top view showing the memory cell design of the three-dimensional semiconductor element of the sixth embodiment. In Fig. 9, the memory cell lines of adjacent columns (e.g., Row1~Row8) and adjacent rows (e.g., Column1~Column8) are arranged in a honeycomb array. For the components of the sixth embodiment which are the same as those of the fifth embodiment, please refer to Fig. 8 and its description.

[0051]

The same elements and features of the sixth embodiment and the fifth embodiment, such as the offset position of the tandem contact 17; adjacent series of contacts 17 in the same row of memory cells are staggered; adjacent memory cells of the same row For the description of the related description and the detailed description, refer to the description of the fifth embodiment, and the details are not described herein again.

[0052]

The elements of the fifth embodiment and the sixth embodiment respectively show memory cells arranged in four columns and eight columns. Similar to the fifth embodiment, in the sixth embodiment, the memory cells of adjacent four columns (such as Row1~Row4) are electrically connected to one selection line; for example, the memory cells of the first column to the fourth column are electrically connected to the selection. The line SSL1, the memory of the fifth to eighth columns is electrically connected to the selection line SSL2. Depending on the design of the embodiment, component decoding can be performed with a smaller number of select lines, which simplifies the process and extends the process window.

[0053]

Furthermore, in the sixth embodiment, for the tandem contacts 17 of the honeycomb-like array memory cells of the same row, the three series of contacts 17 are arranged in a line along the row direction (y-direction) in a straight line. Taking the memory cell of the first row (Column 1) of FIG. 9 as an example, the tandem contacts 17 corresponding to the first column (Row1) and the fifth column (Row5) are arranged in a line along the row direction (y-direction). .

[0054]

In the sixth embodiment, as shown in Fig. 9, according to the position of the tandem contact 17, the tandem contacts 17 corresponding to the same row of memory cells can be divided into two groups, for the same row as the first row of memory cells. In other words, the tandem contacts 17 corresponding to the first column (Row1), the fifth column (Row5) (and the ninth column...) constitute a first group, wherein the first group of the first row (Column 1) memory cells The set of series contacts 17 corresponds to a position 1a and is arranged along line L1a. Furthermore, for the first row (Column 1) memory cell, the tandem contact 17 corresponding to the third column (Row3) and the seventh column (Row7) (and the eleventh column...) constitutes a second group, wherein The tandem contacts 17 of the second group of one row (Column 1) memory cells correspond to a position 1b and are arranged along line L1b. For the memory cells of the second row (Column 2), the tandem contacts 17 corresponding to the second column (Row2), the sixth column (Row6) (and the tenth column...) constitute the first group of the second row, wherein The tandem contacts 17 of the first group of memory cells of the second row correspond to a position 2a and are arranged along the line L2a; further, corresponding to the fourth column (Row4), the eighth column (Row8) (and the twelfth column) The series of contacts 17 of the ... constitute a second group of the second row, wherein the tandem contacts 17 of the second group of second rows of memory cells correspond to a position 2b and are arranged along line L2b. As shown in Fig. 9, the line L1a and the line L2a (a-position) are shifted to the left of the center of the memory cell, and the line L1b and the line L2b (b-position) are shifted to the right of the center of the memory cell. The bit line corresponding to the memory cell (not shown in FIG. 9) is set corresponding to the line L1a, the line L2a, the line L1b, the line L2b, and the like.

[0055]

According to the elements of the fourth to sixth embodiments, the memory cells are arranged in a honeycomb array, and the memory cells of adjacent columns and rows have overlapping regions, for example, the memory cells of the first row (Column 1) of the first column (Row1). The right edge of the conductive layer 152 overlaps with the left edge of the conductive layer 152 of the memory cell 152 of the second row (Row 2) of the second row (Fig. 9), and the application component can be omitted. Opportunities for the metal portion 18 and the conductive holes 19 of the first to third embodiments. Therefore, as the element proposed in the fourth, fifth or sixth embodiment, the bandwidth can be more easily doubled.

[0056]

Furthermore, although the ninth figure shows the memory cell settings of the two rows corresponding to the same row (for example, the lines L1a and L1b corresponding to the first row of memory cells respectively), the disclosure is not limited thereto. The number of bit lines set for the same row of memory cells can be designed to be more than two (eg, 3, 4, 5.), depending on the required conditions, cost constraints, and/or component performance.

[0057]

Further, the tandem contact 17 as shown in Figs. 8 and 9 has an elliptical shape, but the present disclosure is not particularly limited with respect to the shape of the tandem contact 17. The shape of the tandem contact 17 can be circular, elliptical, rectangular or other shape. FIG. 10A is a schematic diagram showing an elliptical tandem contact of an embodiment of the present disclosure. FIG. 10B is a schematic view showing a rectangular string contact according to an embodiment of the present disclosure. As shown in FIG. 10A, a series of contacts having an elliptical cross section has a width Xc parallel to the column direction (x-direction) and a length Yc parallel to the row direction (y-direction), where Yc>Xc, Or Yc>2Xc. As shown in FIG. 10B, a series of contacts having a rectangular cross section has a width Xc and a length Yc, where Yc>Xc, or Yc>2Xc.

[0058]

The detailed construction and description of the above embodiments are for the purpose of description, and the disclosure is not limited to the above structures. Therefore, those skilled in the relevant art can understand that the configurations and designs proposed in the above embodiments can be appropriately modified and adjusted according to the actual needs of the application. According to the three-dimensional semiconductor device structure disclosed in the above embodiments, all the memory cells can be simultaneously read, and the operation speed can be improved. Furthermore, the three-dimensional semiconductor device of the embodiment has a wider bandwidth, a lower power consumption, and a smaller interference between adjacent memory cells when the memory cell is read.

[0059]

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

11‧‧‧ memory layer

SSL1~SSL4‧‧‧ selection line

15‧‧‧Listing

151‧‧‧channel layer

152‧‧‧ Conductive layer

17‧‧‧ Serial contact

18‧‧‧Metal Department

19‧‧‧Electrical hole

BL1~BL16‧‧‧ bit line

Row1~Row4‧‧‧ memory cell

Column1~Column4‧‧‧ memory cell line

Claims (10)

[Item 1] A three-dimensional semiconductor component, comprising: a plurality of memory layers stacked vertically on a substrate and the memory layers are parallel to each other; a plurality of selection lines located above the memory layers and the selection lines Parallel to each other; a plurality of bit lines located above the selection lines, and the bit lines are parallel to each other and perpendicular to the selection lines; a plurality of strings are perpendicular to the memory layers and The selection lines, and the strings are electrically connected to the corresponding selection lines; a plurality of cells are respectively defined by the series, the selection lines, and the bit lines And the memory cell lines are arranged in a plurality of rows and a plurality of columns, wherein the bit lines are parallel to a column direction and the selection lines are parallel to a row direction The memory cells adjacent to each other in the same row are electrically connected to different bit lines. [Item 2] The component of claim 1, wherein at least two of the bit lines are correspondingly located at the memory cells in the same row. [Item 3] The component of claim 1, wherein the four bit lines are correspondingly disposed at the memory cells in the same row. [Item 4] The component of claim 1, wherein at least the two adjacent columns of the memory cells are electrically connected to one of the selection lines. [Item 5] The component of claim 1, wherein the memory cells of the four adjacent columns are electrically connected to one of the selection lines. [Item 6] The component of claim 1, further comprising: a plurality of string contacts perpendicular to the memory layers and the selection lines, and each setting of the serial contacts corresponds to the memories Each of the series of cells, wherein the series of contacts are electrically connected to the corresponding selection lines and corresponding ones of the bit lines. [Item 7] The component of claim 6, wherein the positions of the series contacts are offset from the centers of the corresponding memory cells. [Item 8] The component of claim 6, wherein the series of contacts of the memory cells corresponding to the same column contact adjacent arrays in a misaligned arrangement of centers thereof. [Item 9] The component of claim 6, wherein the series of contacts of the memory cells corresponding to the same column are aligned in a line along the column direction. [Item 10] The component of claim 9, wherein the series of contact lines corresponding to the memory cells of the same column are respectively arranged in a first straight line and a second straight line along the column direction, and the first straight line An upper portion corresponding to the plurality of strings, and the second straight line is located at a lower portion corresponding to the plurality of strings, wherein the memory cells are arranged in a matrix array ( The matrix arrays are electrically connected to the corresponding bit lines through a patterned metal layer and a plurality of conductive vias, wherein the patterned metal layer includes A plurality of metal portions are respectively formed at the series of contact points of the corresponding memory cells, and each of the conductive holes is formed on each of the metal portions to be electrically connected to the corresponding bit line The metal portions partially or completely cover the corresponding serial contacts, wherein the memory cells in the same column are adjacent to the metal portions, wherein two adjacent Between these memory cells The distance along the column direction is a memory cell x pitch Px and the distance along the row direction is a memory cell y pitch Py, when one of the metal portions at least partially covers the corresponding When the series contacts and the metal portion is a first part of a rectangle, the first portion has a width X and a length Y1 respectively parallel to the column direction and the row direction, wherein 2Px>X> Px and Y1<1/2Py; when the metal portion completely covers the corresponding serial contact, the metal portion includes the first portion and a second part connecting the first portion, the first portion The overall length Y2 of the portion and the second portion is parallel to the row direction, where Y2 > 1/2Py.