TWI536524B - Semiconductor device for restraining creep-age phenomenon and fabricating method thereof - Google Patents

Semiconductor device for restraining creep-age phenomenon and fabricating method thereof Download PDF

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TWI536524B
TWI536524B TW103100948A TW103100948A TWI536524B TW I536524 B TWI536524 B TW I536524B TW 103100948 A TW103100948 A TW 103100948A TW 103100948 A TW103100948 A TW 103100948A TW I536524 B TWI536524 B TW I536524B
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pin
pins
wafer
side edge
adjacent
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TW201528467A (en
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牛志強
哈姆扎 依瑪茲
魯軍
王飛
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萬國半導體股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Description

抑制爬電現象的半導體裝置及製備方法 Semiconductor device for suppressing creepage phenomenon and preparation method thereof

本發明一般涉及一種半導體裝置,更確切的說,本發明旨在提供一種最佳化電氣間隙和增加電壓爬電距離(Creep-age distance)的功率半導體裝置及其製備方法,以在半導體裝置的端子間獲得較佳的電氣安全距離。 The present invention generally relates to a semiconductor device, and more particularly to a power semiconductor device for optimizing electrical clearance and increasing creep creepage distance and a method of fabricating the same for use in a semiconductor device A better electrical safety distance is obtained between the terminals.

在傳統的功率半導體裝置中,各個引腳間通常流過大電流或施加有高電壓,而且伴隨著主流技術的發展,往往需要充分縮減裝置的尺寸以符合輕巧化的要求,與之相應的負面效應是,彼此間靠得非常近的引腳周圍的絕緣材料很容易被電極化,致使絕緣材料呈現帶電現象,影響裝置的正常運行,嚴重的情況會帶來安全隱患,特別是在潮濕或粉塵的惡劣環境下,爬電現象愈趨於嚴重。在北美的電器產品安全標準裡,常用ANSI/UL標準進行評估,電氣安全距離是電氣產品安全標準很重要的一個結構審查環節。基於抑制爬電現象的考慮,電氣間隙或爬電距離等參數的控制顯得尤為重要。 In a conventional power semiconductor device, a large current or a high voltage is usually applied between the respective pins, and with the development of mainstream technology, it is often necessary to sufficiently reduce the size of the device to meet the requirements of lightness, and the corresponding negative effects. Yes, the insulating material around the pins that are very close to each other is easily polarized, causing the insulating material to be charged, affecting the normal operation of the device, and serious conditions may cause safety hazards, especially in wet or dusty In harsh environments, the phenomenon of creepage is becoming more and more serious. In North American electrical product safety standards, ANSI/UL standards are commonly used for evaluation. Electrical safety distance is an important structural review link for electrical product safety standards. Based on the consideration of the suppression of creepage, the control of parameters such as clearance or creepage distance is particularly important.

第1A圖展示了常規TO-220裝置,功率裝置的用於支撐功率MOSFET晶片的金屬安裝基座連同晶片都被完全密封在塑封體10內, 引腳11~13和散熱片14都裸露在封裝體10之外,引腳11、13一般是獨立的而與金屬安裝基座斷開,分別作為柵第1極和源極接觸端子,中間的引腳12通常連接在基座上作為漏極端子,引腳11~13等距離平行排列。問題就在於,引腳11~13相互間靠得過近而導致它們之間的爬電距離不符和高壓條件下的要求,例如引腳12的沿長度方向的對稱中心線與引腳11或13的沿長度方向的對稱中心線之間的距離大體上為2.54mm,而引腳12最靠近塑封體的部分與引腳11(或13)最靠近塑封體的部分之間的最窄的距離僅僅約為1.27mm,這樣的引腳距離很容易誘發爬電現象。為了克服這個問題,美國專利申請US6255722B1提出了一種方案,如第1B圖所示,在中間引腳24與它兩側的兩個引腳23、25之間的塑封體60的側面上形成有細槽70、71,雖然引腳23~25中任意兩者間的物理間距沒有明顯變化,但是細槽70相當於拉開了引腳23、24之間的爬電距離,細槽71相當於拉開了引腳24、25之間的爬電距離。在另一些增加爬電距離的文獻中,例如美國專利申請US6291262B1,不僅將塑封體50位於兩個引腳38之間的側壁中形成槽體(如第1C-1圖的俯視圖),還將中間的一個引腳44與該兩個兩側的引腳38分別設置在不同的平面(如第1C-2圖側視圖),也可以實現爬電距離的調整。 Figure 1A shows a conventional TO-220 device in which the metal mounting base of the power device for supporting the power MOSFET wafer is completely sealed within the molding body 10, Pins 11~13 and heat sink 14 are exposed outside the package body 10. The pins 11, 13 are generally independent and disconnected from the metal mounting base as the gate first and source contact terminals, respectively. Pin 12 is usually connected to the pedestal as a drain terminal, and pins 11 to 13 are arranged in parallel at equal distances. The problem is that the pins 11~13 are too close to each other, causing the creepage distance between them to be different and the requirements under high voltage conditions, such as the symmetrical centerline of the pin 12 along the length direction and the pin 11 or 13 The distance between the symmetrical centerlines along the length direction is substantially 2.54 mm, and the narrowest distance between the portion of the lead 12 closest to the molded body and the portion of the lead 11 (or 13) closest to the molded body is only About 1.27mm, such a pin distance is easy to induce creepage. In order to overcome this problem, U.S. Patent No. 6,255,722 B1 proposes a scheme in which, as shown in Fig. 1B, a thin portion is formed on the side of the molding body 60 between the intermediate pin 24 and the two pins 23, 25 on both sides thereof. In the slots 70 and 71, although the physical spacing between any two of the pins 23 to 25 does not change significantly, the slot 70 is equivalent to pulling the creepage distance between the pins 23 and 24, and the slot 71 is equivalent to pulling. The creepage distance between pins 24, 25 is turned on. In other documents which increase the creepage distance, for example, U.S. Patent Application No. 6,921,262 B1, not only is the molded body 50 formed in the side wall between the two pins 38 (as in the top view of FIG. 1C-1), but also in the middle. One pin 44 and the two side pins 38 are respectively disposed on different planes (such as the side view of FIG. 1C-2), and the creepage distance can also be adjusted.

以上文獻所涉及的方法,在改變爬電距離的效果上非常有限,尤其是高電壓施加在漏極或源極引腳上時,根本無法抑制惡劣環境下的爬電現象。本發明正是基於此點,而更有效的抬升爬電距離來抑制這種負面效應。 The methods referred to in the above literature have very limited effects on changing the creepage distance, especially when a high voltage is applied to the drain or source pin, and the creepage phenomenon in a harsh environment cannot be suppressed at all. The present invention is based on this point, and more effectively raises the creepage distance to suppress this negative effect.

在本發明提供的一種功率半導體裝置中,包括:帶有一基座和多個引腳的一晶片安裝單元,並排設置的多個引腳位於基座的一側緣附近,多個引腳中的第一引腳連接在基座上而第二、第三引腳與基座斷開,第二、第三引腳各自靠近基座的一端均有一鍵合區,第二引腳鄰近第一和第三引腳並且第一、第二和第三引腳間以非等距離排列的方式設置;一粘貼於基座的晶片,設於晶片背面的第一電極通過導電材料電性連接於基座,設於晶片的與背面相對的一正面的第二、第三電極通過導電結構分別電性連接於第二、第三引腳各自的鍵合區上;將基座、晶片、導電結構、以及第二、第三引腳的鍵合區予以包覆的一塑封體,塑封體包括一個沿著第一、第二和第三引腳中之一的長度方向延伸的塑封延伸部。 In a power semiconductor device provided by the present invention, a wafer mounting unit having a pedestal and a plurality of pins is disposed, and a plurality of pins arranged side by side are located near one side edge of the pedestal, among the plurality of pins The first pin is connected to the base and the second and third pins are disconnected from the base, and the second and third pins each have a bonding area near one end of the base, and the second pin is adjacent to the first and a third pin and the first, second and third pins are arranged in a non-equidistant arrangement; a wafer attached to the susceptor, the first electrode disposed on the back surface of the wafer is electrically connected to the pedestal via a conductive material The second and third electrodes disposed on the front surface of the wafer opposite to the back surface are respectively electrically connected to the respective bonding regions of the second and third pins through the conductive structure; the susceptor, the wafer, the conductive structure, and The sealing portion of the second and third pins is covered by a molding body, and the molding body includes a plastic extending portion extending along a length direction of one of the first, second and third pins.

上述的功率半導體裝置,其中可設置第三引腳到第二引腳間的距離比第一引腳到第二引腳間更近。 In the above power semiconductor device, the distance between the third pin and the second pin may be set closer than between the first pin and the second pin.

上述的功率半導體裝置,其中第二引腳的一個鄰近第三引腳的側緣與第三引腳的一個鄰近第二引腳的側緣平行延伸,第二引腳的該側緣沿第二引腳的長度方向從塑封體內部延伸到塑封體外部。 In the above power semiconductor device, a side edge of the second pin adjacent to the third pin extends in parallel with a side edge of the third pin adjacent to the second pin, and the side edge of the second pin is along the second side The length of the pin extends from the inside of the molded body to the outside of the molded body.

上述的功率半導體裝置,塑封延伸部沿著第二、第三引腳的長度方向延伸。 In the above power semiconductor device, the plastic package extension extends along the length direction of the second and third leads.

上述的功率半導體裝置,第二引腳的鄰近第一引腳的側緣包括一個角部,向第一引腳和基座靠近。 In the above power semiconductor device, the side edge of the second pin adjacent to the first pin includes a corner portion adjacent to the first pin and the pedestal.

上述的功率半導體裝置,其中設置第一引腳到第二引腳間的距離比第三引腳到第二引腳間更近。 In the above power semiconductor device, the distance between the first pin and the second pin is set closer than the third pin to the second pin.

上述的功率半導體裝置,第二引腳的一個鄰近第一引腳的側 緣與第一引腳的一個鄰近第二引腳的側緣平行延伸,第二引腳的該側緣沿第二引腳的長度方向從塑封體內部延伸到塑封體外部。 The above power semiconductor device, a side of the second pin adjacent to the first pin The edge extends parallel to a side edge of the first pin adjacent to the second pin, and the side edge of the second pin extends from the inside of the molding body to the outside of the molding body along the length of the second pin.

上述的功率半導體裝置,塑封延伸部沿著第一、第二引腳的長度方向延伸。 In the above power semiconductor device, the plastic package extension extends along the longitudinal direction of the first and second leads.

上述的功率半導體裝置,第二引腳的鄰近第三引腳的一個側緣包括一個角部,向第三引腳和向基座靠近。 In the above power semiconductor device, a side edge of the second pin adjacent to the third pin includes a corner portion toward the third pin and toward the pedestal.

上述的功率半導體裝置,晶片為MOSFET或IGBT,第一電極是漏極以及晶片正面的第二、第三電極包括源極和柵極。 In the above power semiconductor device, the wafer is a MOSFET or an IGBT, the first electrode is a drain, and the second and third electrodes on the front side of the wafer include a source and a gate.

在本發明提供的一種功率半導體裝置的封裝方法中,包括以下步驟:提供具多個晶片安裝單元的一引線框架,晶片安裝單元具有一個基座和多個引腳,並排設置的多個引腳位於基座的一側緣附近,多個引腳中第一引腳連接於基座而第二、第三引腳與基座斷開,在第二、第三引腳靠近基座的一端各設有一個鍵合區,其中第二引腳鄰近第一和第三引腳,第一、第二和第三引腳間以非等距離的方式設置;將晶片粘附在基座上,使設置在晶片背面的第一電極通過導電材料電性連接於基座;利用導電結構將晶片正面的多個電極一對一的電性連接於與基座斷開的多個引腳各自的靠近基座的鍵合區上;形成塑封體,將基座、晶片、導電結構、及與基座斷開的每個引腳的鍵合區予以包覆,塑封體包括至少一個沿著第一、第二和第三引腳中之一的長度方向延伸的塑封延伸部;切割引線框架,將各晶片安裝單元分離下來。 In a packaging method of a power semiconductor device provided by the present invention, the method includes the steps of: providing a lead frame having a plurality of wafer mounting units, the wafer mounting unit having a base and a plurality of pins, and a plurality of pins arranged side by side Located near one side edge of the pedestal, the first pin of the plurality of pins is connected to the pedestal and the second and third pins are disconnected from the pedestal, and the second and third pins are respectively adjacent to the pedestal end. a bonding area is provided, wherein the second pin is adjacent to the first and third pins, and the first, second and third pins are arranged in a non-equidistant manner; the wafer is adhered to the base, so that The first electrode disposed on the back surface of the wafer is electrically connected to the pedestal through the conductive material; the conductive structure is used to electrically connect the plurality of electrodes on the front side of the wafer one to one to the respective bases of the plurality of pins disconnected from the pedestal a bonding body; forming a molding body, covering a pedestal, a wafer, a conductive structure, and a bonding region of each pin disconnected from the pedestal, the molding body including at least one along the first, Long-length plastic extension of one of the second and third pins Extension portion; cutting the lead frame, each of the wafer mounting unit detached.

上述方法,設置第三引腳比第一引腳更靠近第二引腳。 In the above method, the third pin is set closer to the second pin than the first pin.

上述方法,第二引腳的一個鄰近第三引腳的側緣與第三引腳 的一個鄰近第二引腳的側緣平行延伸,沿著第二引腳的長度方向從塑封體內部延伸到塑封體外部。 In the above method, a second pin is adjacent to the third pin of the side edge and the third pin A side edge adjacent to the second pin extends in parallel and extends from the inside of the molding body to the outside of the molding body along the length of the second pin.

上述方法,塑封延伸部沿著第二、第三引腳的長度方向延伸。 In the above method, the plastic extension extends along the length of the second and third pins.

上述方法,第二引腳鄰近第一引腳的側緣包括一個角部,向第一引腳和向基座靠近。 In the above method, the side edge of the second pin adjacent to the first pin includes a corner portion toward the first pin and toward the pedestal.

上述方法,第一引腳比第三引腳更接近第二引腳。 In the above method, the first pin is closer to the second pin than the third pin.

上述方法,第二引腳的一個靠近第一引腳的側緣與第一引腳的靠近第二引腳的一個側緣平行延伸,沿著第二引腳的長度方向從塑封體內部延伸到塑封體外部。 In the above method, a side edge of the second pin adjacent to the first pin extends parallel to a side edge of the first pin adjacent to the second pin, and extends from the inside of the molding body along the length of the second pin to The outside of the plastic body.

上述方法,塑封延伸部沿著第一和第二引腳的長度方向延伸。 In the above method, the plastic extension extends along the length of the first and second leads.

上述方法,其中所述第二引腳鄰近第三引腳的一個側緣包含一個角部,向第三引腳和向基座靠近。 The above method, wherein the second pin is adjacent to a side edge of the third pin and includes a corner portion toward the third pin and toward the base.

上述方法,晶片為MOSFET或IGBT,第一電極為漏極,設於晶片正面的第二、第三電極包括源極和柵極。 In the above method, the wafer is a MOSFET or an IGBT, the first electrode is a drain, and the second and third electrodes disposed on the front surface of the wafer include a source and a gate.

本領域的技術人員閱讀以下較佳實施例的詳細說明,並參照附圖之後,本發明的這些和其他方面的優勢無疑將顯而易見。 These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

10‧‧‧塑封體、封裝體 10‧‧‧Plastic body, package

11、12、13、23、24、25、38、44、113、114、115‧‧‧引腳 11, 12, 13, 23, 24, 25, 38, 44, 113, 114, 115‧‧‧ pins

14、112、112'‧‧‧散熱片 14, 112, 112'‧‧ ‧ heat sink

50、60、140‧‧‧塑封體 50, 60, 140‧‧ ‧ plastic enclosure

70、71‧‧‧細槽 70, 71‧‧‧ fine grooves

100‧‧‧引線框架 100‧‧‧ lead frame

110‧‧‧晶片安裝單元 110‧‧‧ wafer mounting unit

111‧‧‧基座 111‧‧‧Base

111a‧‧‧邊緣 111a‧‧‧ edge

120‧‧‧晶片 120‧‧‧ wafer

120a、120b‧‧‧連筋 120a, 120b‧‧‧ reinforced

121‧‧‧柵極 121‧‧‧Gate

122‧‧‧源極 122‧‧‧ source

130‧‧‧引線 130‧‧‧Leader

135‧‧‧導電材料 135‧‧‧Electrical materials

141、141'、142‧‧‧塑封延伸部 141, 141', 142‧‧ ‧ plastic extension

1130、1140‧‧‧鍵合區 1130, 1140‧‧‧ bonding area

1131、1141、1151‧‧‧肩部 1131, 1141, 1151‧‧‧ shoulder

1131a、1141a‧‧‧角部 1131a, 1141a‧‧ corner

1132、1142、1152‧‧‧引腳端部 1132, 1142, 1152‧‧‧ pin end

L‧‧‧長度值 L‧‧‧ length value

W‧‧‧距離值 W‧‧‧ distance value

參考所附附圖,以更加充分的描述本發明的實施例。然而,所附附圖僅用於說明和闡述,並不構成對本發明範圍的限制。 Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

第1A圖為典型的TO-220系列的封裝形式。 Figure 1A shows the typical TO-220 series package.

第1B圖為美國專利申請US6255722B1揭示的增加爬電距離的方案。 FIG. 1B is a scheme for increasing the creepage distance disclosed in US Pat. No. 6,255,722 B1.

第1C-1圖至第1C-2圖為美國專利申請US6291262B1揭示的增加爬電距離的方案。 Figures 1C-1 through 1C-2 illustrate a scheme for increasing creepage distance as disclosed in U.S. Patent Application No. 6,921,262 B1.

第2圖是本發明的引線框架的俯視圖。 Fig. 2 is a plan view of the lead frame of the present invention.

第3A圖至第3B圖是引線框架所包含的晶片安裝單元的結構。 3A to 3B are views showing the structure of a wafer mounting unit included in the lead frame.

第4A圖至第4C-3圖是製備本發明的裝置的方法流程。 Figures 4A through 4C-3 are process flows for preparing the apparatus of the present invention.

第5A圖至第5B圖是基於第4A圖至第4C-3圖流程而提出的一個實施例。 5A to 5B are an embodiment proposed based on the flow of Figs. 4A to 4C-3.

第6A圖至第6B圖是基於第4A圖至第4C-3圖流程而提出的另一個實施例。 6A to 6B are another embodiment proposed based on the flow of Figs. 4A to 4C-3.

第7A圖至第7B圖是調整有效爬電距離的示意圖。 7A to 7B are schematic views of adjusting the effective creepage distance.

第8A圖至第8B圖是將基座的底面從塑封體中外露的結構示意圖。 8A to 8B are schematic views showing the structure in which the bottom surface of the susceptor is exposed from the molded body.

第9A圖至第9D圖是將基座底面和整個散熱片從塑封體中外露的流程示意圖。 9A to 9D are schematic views showing the flow of the bottom surface of the base and the entire heat sink from the molded body.

第10A圖至第10D圖是將與基座不相連的一個引腳移至靠近連接於基座的引腳的實施例。 10A through 10D are embodiments in which a pin that is not connected to the susceptor is moved to a pin that is connected to the susceptor.

第2圖展示了一條金屬材質的引線框架100的一部分片段,現在我們仍然以業界標準化的TO單排直插式的封裝系列為例進行後續闡述,引線框架100通常包含有多個晶片安裝單元110,如第3A圖所示的放大圖。每個晶片安裝單元110至少包含有一個用於承載和粘附晶片的大體為方形的金屬安裝基座111或稱作基島,並在基座111的相對的一對側緣中的一個邊緣111a附近,設置多個平行排列的引腳113、114、115或者一些 更多數量的未示意出的引腳,其中引腳113、114與基座110斷開,而引腳115則連接在基座110上,引腳114佈置在引腳113和115的中間。在基座111的一對側緣中,與邊緣111a相對的另一個邊緣上連接有一個叉狀的散熱片112,在散熱片112的叉指之間設置有切口,其開口方向以背離基座111的方式設置,切口的相對於其開口處部分的內側部分為圓弧狀,或接近於半圓形,可用於引線框架100的定位,注意這裡描述的散熱片112僅僅只是多種選擇方式中的一種,不應作為限制。 Figure 2 shows a portion of a lead frame 100 of a metal material. We will now follow the industry standard TO single in-line package series as an example. The lead frame 100 typically includes a plurality of wafer mounting units 110. , as shown in the enlarged view of Figure 3A. Each of the wafer mounting units 110 includes at least one substantially square metal mounting base 111 for carrying and adhering the wafer, or a base island, and one edge 111a of the opposite pair of side edges of the base 111. Nearby, set multiple parallel arranged pins 113, 114, 115 or some A greater number of unillustrated pins, wherein pins 113, 114 are disconnected from pedestal 110, and pin 115 is coupled to pedestal 110, which is disposed intermediate pins 113 and 115. In a pair of side edges of the base 111, a fork-shaped fin 112 is connected to the other edge opposite to the edge 111a, and a slit is provided between the fingers of the fin 112, the opening direction of which faces away from the base In the manner of 111, the inner portion of the slit relative to the portion at the opening thereof is arcuate, or close to a semicircle, which can be used for positioning of the lead frame 100. Note that the heat sink 112 described herein is only in a plurality of selection modes. One should not be used as a limitation.

在第3A圖的實施方式中,多個引腳113、114、115各自分別對應具有呈條狀平板結構的肩部1131、1141、1151。引腳113的肩部1131的外側一端一體延伸出一個也呈條狀平板結構的引腳端部1132,引腳113的鍵合區1130設於基部113相對的另一內側端。同樣,引腳1141的肩部1141的外側一端一體延伸出一個呈條狀平板結構的引腳端部1142,引腳113的鍵合區1140設於基部1141的另一內側端。引腳115的肩部1151的外側一端一體延伸出一個呈條狀平板結構的引腳端部1152,肩部1151的另一內側端連接於基座111的一條邊緣111a上,並連接於該邊緣111a兩側的兩個端部(或說兩個拐角處)任意之一附近,而實質上該基座111和散熱片112以及引腳115是一體化成型的整體結構。肩部1131~1151和引腳端部1132~1152的長度延伸的方向皆是垂直於邊緣111a的長度方向。其中,與基座111斷開的互相毗鄰的引腳113、114各自的鍵合區1130和1140分別用來承接引線、金屬片、金屬帶或者其他導電結構的鍵合,以便用於連接晶片的電極端子,並且長條狀設置的鍵合區1130、1140均沿著邊緣111a的長度方向延伸以便一定限度的增大鍵合區的面積,從而可以在其上面來 鍵合連接更多數量的引線。在本發明的一種可選實施方式中,連接於基座111的引腳115未穿插在與基座111斷開的引腳113、114之間,引腳113、114佈置在該引腳115左右兩側中的任意一側,即位於引腳115的同一側。 In the embodiment of FIG. 3A, each of the plurality of pins 113, 114, 115 respectively has a shoulder 1131, 1141, 1151 having a strip-like flat structure. The outer end of the shoulder 1131 of the pin 113 integrally extends a pin end portion 1132 which is also in the form of a strip-like flat plate. The bonding region 1130 of the pin 113 is disposed at the opposite inner end of the base portion 113. Similarly, the outer end of the shoulder 1141 of the pin 1141 integrally extends out of a pin end portion 1142 having a strip-like flat structure, and the bonding portion 1140 of the pin 113 is disposed at the other inner end of the base portion 1141. The outer end of the shoulder 1151 of the pin 115 integrally extends a pin end portion 1152 of a strip-like flat structure, and the other inner end of the shoulder 1151 is connected to an edge 111a of the base 111 and is connected to the edge. 111a is adjacent to either end of the two sides (or both corners), and substantially the pedestal 111 and the fins 112 and the leads 115 are integrally formed integral structures. The lengths of the shoulders 1131 to 1151 and the lead ends 1132 to 1152 extend in a direction perpendicular to the length of the edge 111a. Wherein, the respective bonding regions 1130 and 1140 of the mutually adjacent pins 113, 114 which are disconnected from the susceptor 111 are respectively used for receiving the bonding of a lead, a metal piece, a metal strip or other conductive structure for connecting the wafer. Electrode terminals, and the elongated bonding regions 1130, 1140 are all extended along the length direction of the edge 111a so as to increase the area of the bonding region to a certain extent, so that it can be placed thereon Bonding connects a larger number of leads. In an optional embodiment of the present invention, the pin 115 connected to the susceptor 111 is not interposed between the pins 113 and 114 disconnected from the susceptor 111, and the pins 113 and 114 are disposed around the pin 115. Either of the two sides, that is, on the same side of the pin 115.

在一些電路中,N型溝道MOSFET的漏極需要接高電壓,這裡的高電壓是相對於源極或柵極上的低電位而言,例如將垂直式的N-MOSFET的底部漏極電性連接於基座111,就相當於引腳115接到漏極的高電位。最大限度的將相互鄰近的引腳113、114相互靠近以縮短它們間的距離,從而構成多個引腳113~115中指定的一組引腳,使得該一組引腳中例如引腳113、114之間的間距,比該一組引腳中任意一個引腳113或114到餘下的一個引腳115之間的間距小一些,從而引腳113~115間呈現為非等距離排列設置。引腳組113、114中之一連接源極,則增大該引腳組113、114與引腳115間的距離便可拉開源極和漏極間的距離,這對改善爬電距離是有益的,後續內容中將會詳細介紹。 In some circuits, the drain of the N-channel MOSFET needs to be connected to a high voltage, where the high voltage is relative to the low potential on the source or gate, such as the bottom drain of the vertical N-MOSFET. Connecting to the pedestal 111 corresponds to the high potential of the pin 115 connected to the drain. Maximizing the proximity of the adjacent pins 113, 114 to each other to shorten the distance between them, thereby forming a designated one of the plurality of pins 113-115, such that the set of pins, for example, the pin 113, The spacing between 114 is less than the spacing between any one of the set of pins 113 or 114 to the remaining one of the pins 115, such that the pins 113-115 appear as non-equidistant arrangements. One of the pin groups 113, 114 is connected to the source, and increasing the distance between the pin group 113, 114 and the pin 115 can pull the distance between the open source and the drain, which is to improve the creepage distance. Useful, will be described in detail in the follow-up content.

在第3A圖中,內側的引腳114靠近外側的與基座111斷開的引腳113,而遠離與基座111相連的引腳115,並且假定引腳114可以設置在最靠近引腳113的極限位置,而這個極限限度是依賴於用於製作引線框架的沖切設備或刻蝕設備的製程精度。第3A圖中,在肩部1131的背離引腳114的側緣上設有凸緣或角部1131a,在肩部1141的背離引腳113的側緣上設有角部1141a,角部1141a可移至靠近引腳115和靠近基座111。此外,在基部1151的兩個側緣上可以都設有角部或者在其任意一個側緣上設有角部(未標注)。角部的作用在於強化引腳特別是肩部的機械強度防止它們發生形變。 In FIG. 3A, the inner pin 114 is adjacent to the outer pin 113 that is disconnected from the susceptor 111, away from the pin 115 connected to the susceptor 111, and it is assumed that the pin 114 can be placed closest to the pin 113. The extreme limit, which is dependent on the process accuracy of the die cutting equipment or etching equipment used to make the lead frame. In Fig. 3A, a flange or a corner 1131a is provided on a side edge of the shoulder 1131 facing away from the pin 114, and a corner 1141a is provided on a side edge of the shoulder 1141 facing away from the pin 113. The corner 1141a can be Move closer to pin 115 and close to pedestal 111. Further, a corner portion may be provided on both side edges of the base portion 1151 or a corner portion (not shown) may be provided on any one of the side edges. The role of the corners is to strengthen the mechanical strength of the pins, especially the shoulders, from deformation.

但角部並不是必須的,譬如當將這些角部移除時,肩部1131、1141、1151的寬度分別與引腳端部1132、1142、1152的寬度相等。該實施例中使其靠近引腳114的一個端面與肩部1131的靠近引腳114的側緣齊平,同時與引腳端部1132靠近引腳114的一個側緣齊平。以及鍵合區1140靠近引腳113的一個端面與肩部1141的靠近引腳113的側緣齊平,同時與引腳端部1142靠近引腳113的一個側緣齊平。一種結果是,引腳114的鄰近引腳113的一個邊緣大體上與引腳113的鄰近引腳114的一個邊緣平行,並沿著引腳114的長度方向從後續形成的塑封體的內部延伸到塑封體的外部。圖示的結構,可以使引腳113和引腳114之間的距離最小化,也就是說,引腳114與引腳115間的距離最大化。此外,雖然圖中未示意出,但應該明白,在肩部1131~1151各自的兩個側緣上都可以設有角部或者在其任意一個側緣上設有角部,而且鍵合區1130和1140沿邊緣111a延伸的程度不受圖示的限制,鍵合區1130兩端的端面可以相應凸出於肩部1131兩側的側緣也可以與之齊平,鍵合區1140兩端的端面可以凸出於肩部1141兩側的側緣也可以與之齊平。第3B圖是沿著第2圖中虛線AA對基座110的豎剖面圖,引腳113、114、115共面,基座111和散熱片112共面,但引腳113~115與基座111分別位於兩個錯開的平面。第4A圖至第4C-3圖展示了製備能夠抑制爬電現象的半導體裝置的方法。在引線框架100中為了固持這些晶片安裝單元110,防止它們在運輸或製程步驟中發生較大幅度的形變,提供了一些連筋起到物理支撐作用。每個晶片安裝單元110的各個引腳113~115的引腳端部1132~1152的自由末端,都連接在引線框架100的一條連筋120b上,引腳端部1132~1152在從引線框架上切割下來後, 可以插入安裝於PCB上的插座的接納孔中,也可稱作引腳的插頭部。引線框架100的另一條連筋120a也連接在每個引腳113(或114、115)的引腳端部1132(或1142、1152)上,連筋120a連接在引腳端部1132(或1142、1152)的靠近其所屬引腳的肩部1131(或1141、1151)的另一端附近,這裡另一端是相對於引腳端部1132~1152的自由末端而言。間隔開的連筋120a、120b呈平行設置。 However, the corners are not necessary. For example, when the corners are removed, the widths of the shoulders 1131, 1141, and 1151 are equal to the widths of the lead ends 1132, 1142, and 1152, respectively. In this embodiment, an end face adjacent to the pin 114 is flush with the side edge of the shoulder 1131 near the pin 114 while being flush with the pin end 1132 near a side edge of the pin 114. And an end face of the bonding region 1140 near the pin 113 is flush with the side edge of the shoulder 1141 near the pin 113 while being flush with the pin end 1142 near a side edge of the pin 113. One result is that one edge of the adjacent pin 113 of the pin 114 is substantially parallel to one edge of the adjacent pin 114 of the pin 113 and extends from the interior of the subsequently formed molding body along the length of the pin 114 to The exterior of the molded body. The illustrated structure minimizes the distance between pin 113 and pin 114, that is, the distance between pin 114 and pin 115 is maximized. In addition, although not shown in the drawings, it should be understood that a corner portion may be provided on each of the side edges of the shoulder portions 1131 to 1151, or a corner portion may be provided on any one of the side edges, and the bonding region 1130 The extent of the extension of 1140 along the edge 111a is not limited by the illustration. The end faces of the two ends of the bonding region 1130 may be correspondingly protruded from the side edges of the shoulders 1131, and the end faces of the bonding regions 1140 may be The side edges protruding from both sides of the shoulder 1141 can also be flush with it. 3B is a vertical cross-sectional view of the susceptor 110 along the dashed line AA of FIG. 2, the leads 113, 114, 115 are coplanar, the pedestal 111 and the heat sink 112 are coplanar, but the leads 113-115 and the pedestal 111 are located in two staggered planes. 4A to 4C-3 illustrate a method of preparing a semiconductor device capable of suppressing creepage. In order to hold the wafer mounting units 110 in the lead frame 100, they are prevented from undergoing a large deformation in the transportation or process steps, and some of the ribs are provided to provide physical support. The free ends of the pin ends 1132 to 1152 of the respective pins 113 to 115 of each of the wafer mounting units 110 are connected to one of the ribs 120b of the lead frame 100, and the pin ends 1132 to 1152 are on the lead frame. After cutting it, It can be inserted into the receiving hole of the socket mounted on the PCB, which can also be called the plug portion of the pin. The other rib 120a of the lead frame 100 is also connected to the pin end 1132 (or 1142, 1152) of each pin 113 (or 114, 115), and the rib 120a is connected to the pin end 1132 (or 1142). , 1152) near the other end of the shoulder 1131 (or 1141, 1151) of its associated pin, where the other end is relative to the free end of the pin end 1132 ~ 1152. The spaced apart ribs 120a, 120b are arranged in parallel.

在第4A圖中,執行貼片的步驟,利用導電的粘合材料,將多個功率MOSFET晶片120一對一的粘附到多個基座111上,晶片120底面的底部漏極通過粘合材料與基座111電性連接。然後實施引線鍵合製程,將晶片120正面的柵極121通過引線130電性連接到引腳113的鍵合區1130上,將晶片120正面的源極122通過多條引線130電性連接到引腳114的鍵合區1140上,這裡的引線130可以被金屬片或帶狀的金屬導帶等類似的導電結構替換。注意晶片120正面的電極位置可以互換,換言之,柵極121也可以電性連接到鍵合區1140上,源極122也可以電性連接到鍵合區1130上。如第4B圖所示,執行塑封製程,利用環氧樹脂之類的塑封材料,形成一個塑封體140,來將晶片安裝單元110、晶片120及引線130都予以塑封包覆,塑封體140對晶片安裝單元110的包覆方式為至少將基座111、鍵合區1130、1140都包覆在內。在形成了塑封體140的同時,還與塑封體140一體成型形成了的一個塑封延伸部141,塑封延伸部141用於將肩部1151的一部分或全部塑封在內。肩部1141~1151沒有被任何塑封延伸部包覆。在第4C-1圖中,執行了引線框架的切割步驟,主要是對連筋120a、120b實施沖切,以將各個引腳(113或114、115)從這些連筋上切割分離,此 時各晶片安裝單元110便從引線框架100上分離下來。一般在完成塑封後,還往往需要在引腳113~115延伸到塑封體140外部的部分的表面上鍍上起保護作用或增進電接觸的金屬層,最後才將引腳端部1132~1152從連筋上沖切斷開,分離出第4C-3圖所示的半導體裝置。注意被業界熟知的一些細節性的標準封裝流程在本發明中不再贅述。 In Fig. 4A, the step of performing a patch is performed by using a conductive adhesive material to adhere a plurality of power MOSFET wafers 120 one by one to a plurality of susceptors 111, and the bottom drain of the bottom surface of the wafer 120 is bonded. The material is electrically connected to the base 111. Then, the wire bonding process is performed to electrically connect the gate electrode 121 on the front surface of the wafer 120 to the bonding region 1130 of the pin 113 through the wire 130, and electrically connect the source electrode 122 on the front surface of the wafer 120 to the lead wire 130 through the plurality of leads 130. On the bonding area 1140 of the foot 114, the lead 130 herein may be replaced by a similar conductive structure such as a metal piece or a strip-shaped metal conduction band. Note that the electrode positions on the front side of the wafer 120 can be interchanged. In other words, the gate electrode 121 can also be electrically connected to the bonding region 1140, and the source electrode 122 can also be electrically connected to the bonding region 1130. As shown in FIG. 4B, a molding process is performed, and a molding material 140 is formed by using a molding material such as an epoxy resin to mold the wafer mounting unit 110, the wafer 120, and the leads 130, and the molding body 140 is wafer-to-wafer. The mounting unit 110 is coated in such a manner that at least the susceptor 111 and the bonding regions 1130 and 1140 are covered. At the same time as the molding body 140 is formed, a plastic molding extension portion 141 is formed integrally formed with the molding body 140, and the plastic molding extension portion 141 is used to mold a part or all of the shoulder portion 1151. The shoulders 1141~1151 are not covered by any plastic extensions. In the 4C-1 diagram, the cutting step of the lead frame is performed, mainly by punching the continuous ribs 120a, 120b to cut and separate the respective pins (113 or 114, 115) from the ribs. Each of the wafer mounting units 110 is separated from the lead frame 100. Generally, after the plastic molding is completed, it is often necessary to plate a metal layer for protecting or enhancing electrical contact on the surface of the portion of the lead 113-115 extending to the outside of the molding body 140, and finally the pin end portions 1132 to 1152 are The ribs are cut and opened, and the semiconductor device shown in Fig. 4C-3 is separated. Note that some of the detailed standard packaging processes that are well known in the industry are not described in the present invention.

第4C-2圖仍然是第2圖中虛線AA的剖面圖,只不過此時已經完成了塑封,其中晶片120通過焊錫膏或導電銀漿之類的導電材料135粘附在基座111的頂面上,而塑封體140則將基座111和散熱片112以及晶片120都完全塑封包覆在內而沒有裸露,引腳113、114各自的鍵合區1130、1140也被密封在塑封體140。圖示的塑封延伸部141大體呈現為錐形,比塑封體140要薄,從塑封體140的一側壁向外延伸並靠近引腳。我們設定塑封延伸部141沿基部1151的長度方向向外延伸的長度值為L,參考第3A圖的俯視圖和結合第4C-3圖的立體圖,如果設定基部1141和基部1151兩者間最窄處的距離值大約W,在本發明中此時的有效的爬電距離大致上為L與W兩者之和。以一個不具限制性的例子進行闡釋,如果第4C-3圖的半導體裝置與第1A圖中裝置的整體尺寸相同,一般L可達2~4mm,W也可達2~4mm,所以第4C-3圖的爬電距離最小值是4mm左右,但相比之下,第1A圖中的爬電距離僅僅是1.27mm左右,可見本發明對提升爬電距離的貢獻是本領域的技術人員所樂見其成的。 4C-2 is still a cross-sectional view of the broken line AA in Fig. 2, except that the plastic sealing has been completed at this time, in which the wafer 120 is adhered to the top of the susceptor 111 by a conductive material 135 such as solder paste or conductive silver paste. On the surface, the molding body 140 completely encapsulates the susceptor 111 and the heat sink 112 and the wafer 120 without being exposed, and the respective bonding regions 1130 and 1140 of the leads 113 and 114 are also sealed in the molding body 140. . The illustrated plastic extension 141 is generally tapered, thinner than the molded body 140, extending outwardly from a side wall of the molded body 140 and adjacent to the pins. We set the length value of the plastic extension portion 141 to extend outward in the longitudinal direction of the base portion 1151. Referring to the top view of FIG. 3A and the perspective view of FIG. 4C-3, if the narrowest portion between the base portion 1141 and the base portion 1151 is set The distance value is about W, and the effective creepage distance at this time in the present invention is roughly the sum of both L and W. In a non-limiting example, if the semiconductor device of FIG. 4C-3 is the same as the overall size of the device of FIG. 1A, generally L can be 2 to 4 mm, and W can be 2 to 4 mm, so 4C- The creepage distance of Fig. 3 is about 4 mm, but the creepage distance in Fig. 1A is only about 1.27 mm. It can be seen that the contribution of the present invention to increasing the creepage distance is appreciated by those skilled in the art. See what it is.

第5A圖至第5B圖的實施方式是基於第4A圖至第4C-1圖流程,類似於第4B圖和第4C-3圖,最大的區別是,在塑封工序中沒有塑封引腳115的肩部1151,沒有製備塑封延伸部141,而是以同樣的方式, 形成了塑封體140的另一個不同的塑封延伸部142,塑封延伸部142沿著引腳113(或114、115)的長度方向延伸。與基座斷開的多個引腳113、114相互靠近,並遠離連接於基座111的引腳115,在該情形下,塑封延伸部142用於包覆該組引腳113、114各自的基部1131、1141,塑封延伸部142的包覆方式為,可將基部1131、1141全部包覆在內或者僅包覆基部1131、1141各自的一部分,一般而言,塑封延伸部142比只塑封一個基部115的塑封延伸部141要略寬一些,所占的體積也大一些。注意此時基部1151沒有被任何塑封延伸部包覆住。 The embodiment of FIGS. 5A to 5B is based on the flow of FIG. 4A to FIG. 4C-1, similar to FIG. 4B and FIG. 4C-3, the biggest difference is that there is no plastic pin 115 in the molding process. The shoulder 1151 is not prepared with the plastic extension 141, but in the same way, Another different plastic extension 142 of the molded body 140 is formed, the plastic extension 142 extending along the length of the lead 113 (or 114, 115). The plurality of pins 113, 114 disconnected from the pedestal are adjacent to each other and away from the pins 115 connected to the pedestal 111. In this case, the plastic extension 142 is used to cover the respective sets of pins 113, 114. The base portions 1131, 1141 and the plastic seal extension portion 142 are wrapped in such a manner that the base portions 1131, 1141 can be entirely covered or only a part of each of the base portions 1131, 1141 can be covered. Generally, the plastic seal extension portion 142 is only one plastic seal. The plastic extension 141 of the base 115 is slightly wider and occupies a larger volume. Note that the base 1151 is not covered by any plastic extension at this time.

第6A圖至第6B圖的實施方式是基於第4A圖至第4C-1圖流程,類似於4B和4C-3,最大的區別是,在塑封工序中不僅僅只是以封延伸部141塑封引腳115的肩部1151,而是以同樣的方式,還額外製備了塑封體140的另一個不同的塑封延伸部142,將該組引腳113、114各自的肩部1131、1141一併塑封在內,塑封延伸部141、142同時並存,如果塑封延伸部142沿著引腳113的長度方向延伸的長度也是L,則第6B圖中實際的爬電距離相對第5B圖又增加了約為L,大約為2L加上W。 The embodiments of FIGS. 6A to 6B are based on the processes of FIGS. 4A to 4C-1, similar to 4B and 4C-3, and the biggest difference is that not only the sealing portion 141 is molded by the sealing portion 141 in the molding process. The shoulder 1151 of the foot 115, but in the same manner, another different plastic extension 142 of the molding body 140 is additionally prepared, and the shoulders 1131, 1141 of the set of pins 113, 114 are molded together. The plastic extension portions 141, 142 coexist at the same time. If the length of the plastic extension portion 142 extending along the longitudinal direction of the lead 113 is also L, the actual creepage distance in FIG. 6B is increased by about L with respect to the fifth FIG. , about 2L plus W.

第7A圖至第7B圖類似於第4B圖和第4C-1圖,雖然也額外製備了塑封延伸部141',但包覆肩部1151的塑封延伸部141'沿基部1151的長度方向延伸的長度值相對第4B圖較小,相當於僅僅是肩部1151靠近邊緣111a的較短的一部分被包覆在塑封延伸部141'內,而肩部1151靠近引腳端部1152的較長的另一部分則裸露在塑封延伸部141'之外。或肩部1131、1141靠近鍵合區1130、1140的較短的一部分被包覆在另一未示出的塑封延伸部內,類似於塑封延伸部141',在塑封工序中,肩部1131、1141 分別靠近引腳端部1132、1142的較長的另一部分則裸露在相應塑封延伸部之外。爬電距離可依改變塑封延伸部141'的長度值的方式進行調整。 7A to 7B are similar to FIG. 4B and FIG. 4C-1, although the plastic extension portion 141' is additionally prepared, but the plastic extension portion 141' covering the shoulder portion 1151 extends along the length direction of the base portion 1151. The length value is smaller than that of FIG. 4B, which is equivalent to only a shorter portion of the shoulder 1151 near the edge 111a being wrapped within the plastic extension 141', and the shoulder 1151 being closer to the longer end of the pin end 1152. A portion is exposed outside of the plastic extension 141'. Or a shorter portion of the shoulders 1131, 1141 near the bonding regions 1130, 1140 is wrapped in another plastic extension, not shown, similar to the plastic extension 141', in the molding process, the shoulders 1131, 1141 The longer other portion adjacent the pin ends 1132, 1142, respectively, is exposed outside of the corresponding plastic extension. The creepage distance can be adjusted in such a manner as to change the length value of the plastic extension portion 141'.

第8A圖至第8B圖的實施方式也是基於第4A圖至第4C-3圖流程,類似於第4C-2圖和第4C-3圖,最大的區別是,在形成塑封體140的步驟中,雖然以塑封體140將基座111和散熱片112、以及將晶片120、鍵合區1130、1140和引線130都予以包覆,但其包覆方式為至少使基座111和散熱片112各自的底面外露於塑封體140的一個底面,以便為晶片120提供一個較好的熱量消散途徑。 The embodiments of Figs. 8A to 8B are also based on the flow of Figs. 4A to 4C-3, similar to Figs. 4C-2 and 4C-3, the biggest difference being that in the step of forming the molded body 140 Although the susceptor 111 and the heat sink 112, and the wafer 120, the bonding regions 1130, 1140, and the lead 130 are covered by the molding body 140, the coating method is at least the pedestal 111 and the heat sink 112, respectively. The bottom surface is exposed to a bottom surface of the molding body 140 to provide a better heat dissipation path for the wafer 120.

第9A圖至9D的實施方式也是基於第4A圖至第4C-3圖流程,類似於第4B圖和第4C-1圖,最大的區別是,叉狀的散熱片112被常規的帶圓形孔的方片狀的散熱片112'取代,如第9A圖所示,在基座111的與連接有引腳115的側緣111a相對的另一側緣上連接有一個散熱片112'。在形成塑封體140的步驟中,如第9B圖至第9C圖所示,以塑封體140將基座111、晶片120、引線130和鍵合區1130、1140予以包覆,但整個散熱片112'卻完全外露於塑封體140,而且還至少使基座111的底面外露於塑封體140的一個底面,如第9D圖所示。 The embodiments of Figs. 9A to 9D are also based on the flow of Figs. 4A to 4C-3, similar to Fig. 4B and Fig. 4C-1, the biggest difference is that the forked fins 112 are conventionally rounded. Instead of the square fin-shaped fin 112' of the hole, as shown in Fig. 9A, a fin 112' is connected to the other side edge of the susceptor 111 opposite to the side edge 111a to which the pin 115 is attached. In the step of forming the molding body 140, as shown in FIGS. 9B to 9C, the susceptor 111, the wafer 120, the leads 130, and the bonding regions 1130, 1140 are covered with the molding body 140, but the entire heat sink 112 is covered. 'It is completely exposed to the molding body 140, and at least the bottom surface of the base 111 is exposed to a bottom surface of the molding body 140, as shown in Fig. 9D.

在第10A圖的實施方式中,是將第3A圖的引腳114的位置進行了調整,中間的引腳114不再鄰近外側的引腳113,反而是遠離引腳113卻靠近引腳115。使彼此鄰近的引腳114、115儘量相互靠近以縮短它們間的距離,以便在多個引腳113~115中使它們形成指定的一組引腳,同時要求使該一組引腳中引腳114、115之間的間距,比該一組引腳中任意一個引腳到餘下的一個引腳113之間的間距都要小一些,該餘下的引腳113 是指所有引腳113~115中除了引腳組114~115外的餘下的引腳,從而引腳113~115間呈現為非等距離排列設置。在該實施方式中,以P溝道型的MOSFET晶片120'取代了之前的N-MOSFET晶片120,P-MOSFET一般是源極連接高電壓,這裡的高電壓是相對於漏極或柵極上的低電位而言。晶片120'正面的柵極121'通過引線130電性連接到引腳114的鍵合區1140,正面的源極122'通過引線130電性連接到引腳113的鍵合區1130,以引腳113來接高壓,此時晶片120'背面的底部漏極連接到基座111和引腳115。則增大該引腳組114、115與引腳113間的距離,相當於拉開了源極和漏極間的距離,這對改善爬電距離是有益的。假定引腳114可以設置在最靠近引腳115的極限位置,這個極限限度同樣是依賴於用於製作引線框架的沖切機台或刻蝕設備的製程精度。同樣,在肩部1131~1151各自的兩個側緣上可以都設有角部或者在其任意一個側緣上設有角部(未標注),或者不設置任何角部,這在前述內容中已經有所闡釋,不再贅述。在第10B圖的實施方式中,塑封延伸部141將與基座111相連的一個引腳115的肩部1151的至少一部分包覆在內,塑封延伸部141還同時將與基座111斷開並靠近引腳115的一個引腳114的肩部1141的至少一部分包覆在內,但與基座111斷開的遠離該一組引腳114、115的一個引腳113的肩部1131未被任何塑封延伸部包覆住。在第10C圖的實施方式中,塑封延伸部142將引腳113的肩部1131的至少一部分予以包覆,但引腳組114、115各自的肩部1141、1151未被任何塑封延伸部包覆住。在第10D圖的實施方式中,基部1141~1151各自的至少一部分或全部都被塑封延伸部141一併包覆在內,同時基部1131的至少一部分或全部被另一個塑封延伸部142包覆在內。 In the embodiment of FIG. 10A, the position of the pin 114 of FIG. 3A is adjusted, and the intermediate pin 114 is no longer adjacent to the outer pin 113, but is remote from the pin 113 but close to the pin 115. Leading the adjacent pins 114, 115 as close as possible to each other to shorten the distance between them to form a specified set of pins in the plurality of pins 113-115, and to require the pins in the set of pins The spacing between 114 and 115 is smaller than the spacing between any one of the set of pins to the remaining one of the pins 113. The remaining pins 113 It refers to the remaining pins of all pins 113~115 except the pin groups 114~115, so the pins 113~115 appear as non-equidistant arrangement. In this embodiment, the previous N-MOSFET wafer 120 is replaced with a P-channel MOSFET wafer 120'. The P-MOSFET is typically a source connected to a high voltage, where the high voltage is relative to the drain or gate. In terms of low potential. The gate 121 ′ of the front surface of the wafer 120 ′ is electrically connected to the bonding region 1140 of the pin 114 through the lead 130 , and the source 122 ′ of the front surface is electrically connected to the bonding region 1130 of the pin 113 through the lead 130 to be a pin. 113 is connected to the high voltage, at which time the bottom drain of the back side of the wafer 120' is connected to the pedestal 111 and the pin 115. Increasing the distance between the pin groups 114, 115 and the pin 113 is equivalent to pulling apart the distance between the source and the drain, which is beneficial for improving the creepage distance. It is assumed that the pin 114 can be placed at the extreme position closest to the pin 115, which is also dependent on the process accuracy of the die-cutting machine or etching apparatus used to make the lead frame. Similarly, the two side edges of the shoulders 1131 to 1151 may be provided with corners or corners (not labeled) on either side edge thereof, or no corners are provided, which is in the foregoing. Has been explained, no longer repeat them. In the embodiment of FIG. 10B, the molding extension 141 encloses at least a portion of the shoulder 1151 of one of the pins 115 connected to the susceptor 111, and the molding extension 141 is simultaneously disconnected from the pedestal 111. At least a portion of the shoulder 1141 of one of the pins 114 near the pin 115 is covered, but the shoulder 1131 of the pin 113 that is disconnected from the pedestal 111 away from the set of pins 114, 115 is not any The plastic extension is covered. In the embodiment of FIG. 10C, the plastic extension 142 covers at least a portion of the shoulder 1131 of the pin 113, but the respective shoulders 1141, 1151 of the lead sets 114, 115 are not covered by any of the plastic extensions. live. In the embodiment of FIG. 10D, at least a portion or all of each of the base portions 1141 to 1151 is integrally covered by the plastic extension portion 141 while at least a part or all of the base portion 1131 is covered by the other plastic seal extension portion 142. Inside.

晶片120、120'還可以用絕緣柵雙極電晶體(IGBT)來替換,此時相應的電極連接關係是,引腳114可作為IGBT的柵極,但引腳113、114需對應轉換為IGBT的集電極或發射極。在一些實施方式中,如果所有引腳呈等距離排列,而又將接高電壓的如源極或漏極等電極連接在並排的多個引腳中較中間的引腳上,將會消減爬電距離,因為較中間的高電位引腳到它兩側的低電位引腳的距離都比較小,這有悖於本發明的發明精神。在一些實施方式中,如果所有引腳呈等距離排列,理論上來講,試圖將每個引腳的基部都用一個單獨的塑封延伸部來包覆並無不妥,但實際中這樣改善爬電距離的效果非常有限,譬如當多個引腳中較中間的引腳接高電壓時,中間引腳到它兩側的低電位引腳的距離仍然比較小,而且即便是最外側的引腳接高電位,外側引腳到中間低電位引腳的距離仍舊屬於短爬電距離的範疇。另外,如果想將相鄰兩個引腳的基部各用一個單獨的塑封延伸部來包覆,就要保障相鄰的引腳之間必須預留一定的空間間隙來適配塑封延伸部的插入佈置,這勢必要拉開引腳的間距,只能增大整體裝置的尺寸來滿足引腳間較寬空間的要求,而這樣卻花費了更大的成本代價和犧牲了裝置的性能。顯然,這樣的方式都不如本發明利用塑封延伸部將指定的一組引腳各自的基部同時塑封,或/和將所有引腳中除了該一組引腳外餘下的引腳的基部予以塑封的方式所獲得的爬電距離效果好。 The wafers 120, 120' can also be replaced by an insulated gate bipolar transistor (IGBT). In this case, the corresponding electrode connection relationship is that the pin 114 can serve as the gate of the IGBT, but the pins 113 and 114 need to be converted into IGBTs. Collector or emitter. In some embodiments, if all the pins are arranged equidistantly, and a high voltage such as a source or a drain electrode is connected to the middle of the plurality of pins arranged side by side, the climb will be reduced. The electrical distance is because the distance between the middle high-potential pin and the low-potential pin on both sides thereof is relatively small, which is contrary to the inventive spirit of the present invention. In some embodiments, if all the pins are arranged equidistantly, in theory, it is not inappropriate to attempt to coat the base of each pin with a separate plastic extension, but in practice, the creepage is improved. The effect of the distance is very limited. For example, when the middle of the multiple pins is connected to a high voltage, the distance from the middle pin to the low potential pins on both sides is still small, and even the outermost pin is connected. The high potential, the distance from the outer pin to the middle low potential pin is still in the category of short creepage distance. In addition, if you want to cover the bases of two adjacent pins with a single plastic extension, you must ensure that a certain space gap is reserved between adjacent pins to fit the insertion of the plastic extension. Arrangement, it is necessary to open the pitch of the pins, only to increase the size of the overall device to meet the requirements of a wider space between the pins, but this costs more cost and sacrifices the performance of the device. Obviously, such a method does not use the plastic extension to simultaneously mold the respective bases of a specified set of pins, or/and to mold the base of the remaining pins of all the pins except the set of pins. The creepage distance obtained by the method is good.

以上,通過說明和附圖,給出了具體實施方式和典型實施例,但這些內容並不作為侷限。對於本領域的技術人員而言,閱讀上述說明後,各種變化和修正無疑將顯而易見。因此,所附的申請專利範圍應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍內 任何和所有等價的範圍與內容,都應認為仍屬本發明的意圖和範圍內。 The detailed description and the exemplary embodiments are given by way of illustration Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Within the scope of patent application Any and all equivalent ranges and contents are considered to be within the scope and spirit of the invention.

113、114、115‧‧‧引腳 113, 114, 115‧‧‧ pins

140‧‧‧塑封體 140‧‧‧plastic body

141‧‧‧塑封延伸部 141‧‧‧ Plastic extension

L‧‧‧長度值 L‧‧‧ length value

Claims (20)

一種功率半導體裝置,其特徵在於,包括:帶有一基座和多個引腳的一晶片安裝單元,並排設置的多個引腳位於基座的一側緣附近,多個引腳中的第一引腳連接在基座上而第二、第三引腳與基座斷開,第二、第三引腳各自靠近基座的一端均有一鍵合區,第二引腳鄰近第一和第三引腳並且第一、第二和第三引腳間以非等距離排列的方式設置;一粘貼於基座的晶片,設於晶片背面的第一電極通過導電材料電性連接於基座,設於晶片的與背面相對的一正面的第二、第三電極通過導電結構分別電性連接於第二、第三引腳各自的鍵合區上;將基座、晶片、導電結構、以及第二、第三引腳的鍵合區予以包覆的一塑封體,塑封體包括一個沿著第一、第二和第三引腳中之一的長度方向延伸的塑封延伸部。 A power semiconductor device, comprising: a wafer mounting unit having a pedestal and a plurality of pins, wherein a plurality of pins arranged side by side are located near a side edge of the pedestal, the first of the plurality of pins The pin is connected to the base and the second and third pins are disconnected from the base. The second and third pins respectively have a bonding area near one end of the base, and the second pin is adjacent to the first and third ends. a pin and the first, second and third pins are arranged in a non-equidistant manner; a wafer attached to the pedestal, the first electrode disposed on the back surface of the wafer is electrically connected to the pedestal through the conductive material, The second and third electrodes of the front surface of the wafer opposite to the back surface are respectively electrically connected to the respective bonding regions of the second and third pins through the conductive structure; the pedestal, the wafer, the conductive structure, and the second And a molding body covered by the bonding region of the third pin, the molding body comprising a plastic extending portion extending along a length direction of one of the first, second and third pins. 如申請專利範圍第1項所述的功率半導體裝置,其中,設置第三引腳到第二引腳間的距離比第一引腳到第二引腳間更近。 The power semiconductor device according to claim 1, wherein a distance between the third pin and the second pin is set closer than between the first pin and the second pin. 如申請專利範圍第2項所述的功率半導體裝置,其中,第二引腳的一個鄰近第三引腳的側緣與第三引腳的一個鄰近第二引腳的側緣平行延伸,第二引腳的該側緣沿第二引腳的長度方向從塑封體內部延伸到塑封體外部。 The power semiconductor device of claim 2, wherein a side edge of the second pin adjacent to the third pin extends parallel to a side edge of the third pin adjacent to the second pin, the second The side edge of the pin extends from the inside of the molding body to the outside of the molding body along the length of the second pin. 如申請專利範圍第2項所述的功率半導體裝置,其中,塑封延伸部沿著第二、第三引腳的長度方向延伸。 The power semiconductor device according to claim 2, wherein the plastic package extension extends along a length direction of the second and third leads. 如申請專利範圍第2項所述的功率半導體裝置,其中,第二引腳的鄰近第一引腳的側緣包括一個角部,向第一引腳和基座靠近。 The power semiconductor device of claim 2, wherein the side edge of the second pin adjacent to the first pin includes a corner portion adjacent to the first pin and the pedestal. 如申請專利範圍第1項所述的功率半導體裝置,其中,設置第一引腳到第二引腳間的距離比第三引腳到第二引腳間更近。 The power semiconductor device according to claim 1, wherein a distance between the first pin and the second pin is set to be closer to a distance between the third pin and the second pin. 如申請專利範圍第6項所述的功率半導體裝置,其中,第二引腳的一個鄰近第一引腳的側緣與第一引腳的一個鄰近第二引腳的側緣平行延伸,第二引腳的該側緣沿第二引腳的長度方向從塑封體內部延伸到塑封體外部。 The power semiconductor device of claim 6, wherein a side edge of the second pin adjacent to the first pin extends parallel to a side edge of the first pin adjacent to the second pin, the second The side edge of the pin extends from the inside of the molding body to the outside of the molding body along the length of the second pin. 如申請專利範圍第6項所述的功率半導體裝置,其中,塑封延伸部沿著第一、第二引腳的長度方向延伸。 The power semiconductor device according to claim 6, wherein the plastic package extension extends along a length direction of the first and second leads. 如申請專利範圍第6項所述的功率半導體裝置,其中,第二引腳的鄰近第三引腳的一個側緣包括一個角部,向第三引腳和向基座靠近。 The power semiconductor device of claim 6, wherein a side edge of the second pin adjacent to the third pin includes a corner portion toward the third pin and toward the pedestal. 如申請專利範圍第1項所述的功率半導體裝置,其中,晶片為MOSFET或IGBT,第一電極是漏極以及晶片正面的第二、第三電極包括源極和柵極。 The power semiconductor device according to claim 1, wherein the wafer is a MOSFET or an IGBT, the first electrode is a drain, and the second and third electrodes of the front surface of the wafer include a source and a gate. 一種功率半導體裝置的封裝方法,其特徵在於,包括以下步驟:提供具多個晶片安裝單元的一引線框架,晶片安裝單元具有一個基座和多個引腳,並排設置的多個引腳位於基座的一側緣附近,多個引腳中第一引腳連接於基座而第二、第三引腳與基座斷開,在第二、第三引腳靠近基座的一端各設有一個鍵合區,其中第二引腳鄰近第一和第三引腳,第一、第二和第三引腳間以非等距離的方式設置; 將晶片粘附在基座上,使設置在晶片背面的第一電極通過導電材料電性連接於基座;利用導電結構將晶片正面的多個電極一對一的電性連接於與基座斷開的多個引腳各自的靠近基座的鍵合區上;形成塑封體,將基座、晶片、導電結構、及與基座斷開的每個引腳的鍵合區予以包覆,塑封體包括至少一個沿著第一、第二和第三引腳中之一的長度方向延伸的塑封延伸部;切割引線框架,將各晶片安裝單元分離下來。 A method of packaging a power semiconductor device, comprising the steps of: providing a lead frame having a plurality of wafer mounting units, the wafer mounting unit having a base and a plurality of pins, the plurality of pins disposed side by side at the base Near the one side edge of the socket, the first pin of the plurality of pins is connected to the base, and the second and third pins are disconnected from the base, and the second and third pins are respectively disposed at one end of the second and third pins near the base. a bonding region, wherein the second pin is adjacent to the first and third pins, and the first, second, and third pins are disposed in a non-equidistant manner; Adhering the wafer to the pedestal, the first electrode disposed on the back surface of the wafer is electrically connected to the pedestal through the conductive material; and electrically connecting the plurality of electrodes on the front surface of the wafer to the pedestal Opening a plurality of pins on each of the bonding regions of the pedestal; forming a molding body, covering the pedestal, the wafer, the conductive structure, and the bonding area of each pin disconnected from the pedestal, and molding The body includes at least one plastic extension extending along a length of one of the first, second, and third pins; and the lead frame is cut to separate the wafer mounting units. 如申請專利範圍第11項所述的方法,其中,設置第三引腳比第一引腳更靠近第二引腳。 The method of claim 11, wherein the third pin is disposed closer to the second pin than the first pin. 如申請專利範圍第12項所述的方法,其中,第二引腳的一個鄰近第三引腳的側緣與第三引腳的一個鄰近第二引腳的側緣平行延伸,沿著第二引腳的長度方向從塑封體內部延伸到塑封體外部。 The method of claim 12, wherein a side edge of the second pin adjacent to the third pin extends parallel to a side edge of the third pin adjacent to the second pin, along the second The length of the pin extends from the inside of the molded body to the outside of the molded body. 如申請專利範圍第12項所述的方法,其中,塑封延伸部沿著第二、第三引腳的長度方向延伸。 The method of claim 12, wherein the plastic extension extends along a length of the second and third pins. 如申請專利範圍第12項所述的方法,其中,第二引腳鄰近第一引腳的側緣包括一個角部,向第一引腳和向基座靠近。 The method of claim 12, wherein the side edge of the second pin adjacent to the first pin includes a corner toward the first pin and toward the base. 如申請專利範圍第11項所述的方法,其中,第一引腳比第三引腳更接近第二引腳。 The method of claim 11, wherein the first pin is closer to the second pin than the third pin. 如申請專利範圍第16項所述的方法,其中,第二引腳的一個靠近第一引腳的側緣與第一引腳的靠近第二引腳的一個側緣平行延伸,沿著第二引腳的長度方向從塑封體內部延伸到塑封體外部。 The method of claim 16, wherein a side edge of the second pin adjacent to the first pin extends parallel to a side edge of the first pin adjacent to the second pin, along the second The length of the pin extends from the inside of the molded body to the outside of the molded body. 如申請專利範圍第16項所述的方法,其中,塑封延伸部沿著第一和第二引腳的長度方向延伸。 The method of claim 16, wherein the plastic extension extends along the length of the first and second pins. 如申請專利範圍第16項所述的方法,其中,第二引腳鄰近第三引腳的一個側緣包含一個角部,向第三引腳和向基座靠近。 The method of claim 16, wherein the second pin comprises a corner adjacent to a side edge of the third pin, toward the third pin and toward the base. 如申請專利範圍第11項所述的方法,其中,晶片為MOSFET或IGBT,第一電極為漏極,設於晶片正面的第二、第三電極包括源極和柵極。 The method of claim 11, wherein the wafer is a MOSFET or an IGBT, the first electrode is a drain, and the second and third electrodes disposed on the front surface of the wafer include a source and a gate.
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