TWI536464B - Transistor and method for fabricating the same - Google Patents
Transistor and method for fabricating the same Download PDFInfo
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- TWI536464B TWI536464B TW103101470A TW103101470A TWI536464B TW I536464 B TWI536464 B TW I536464B TW 103101470 A TW103101470 A TW 103101470A TW 103101470 A TW103101470 A TW 103101470A TW I536464 B TWI536464 B TW I536464B
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- 238000000034 method Methods 0.000 title claims description 17
- 239000000463 material Substances 0.000 claims description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 229910052738 indium Inorganic materials 0.000 claims description 20
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 20
- 239000007769 metal material Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 18
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 10
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 191
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 28
- 239000011787 zinc oxide Substances 0.000 description 14
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 12
- 229910052750 molybdenum Inorganic materials 0.000 description 12
- 239000011733 molybdenum Substances 0.000 description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 229910052733 gallium Inorganic materials 0.000 description 11
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 229910001887 tin oxide Inorganic materials 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 3
- 229910003437 indium oxide Inorganic materials 0.000 description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- -1 Al) Chemical compound 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/467—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Thin Film Transistor (AREA)
Description
本發明是有關於一種電晶體及其製造方法，且特別是有關於一種具有氧化物半導體通道層的電晶體及其製造方法。 The present invention relates to a transistor and a method of fabricating the same, and more particularly to a transistor having an oxide semiconductor channel layer and a method of fabricating the same.
近年來，相較於傳統的非晶矽(amorphous silicon,a-Si)薄膜電晶體，由於氧化物半導體(oxide semiconductor)薄膜電晶體更具有較高的載子移動率(carrier mobility)、較為穩定的臨界電壓(threshold voltage,Vth)以及適合大面積製造，因此已逐漸被廣泛的應用於顯示面板中。 In recent years, compared to conventional amorphous silicon (a-Si) thin film transistors, oxide semiconductor thin film transistors have higher carrier mobility and are more stable. The threshold voltage (Vth) and suitable for large-area manufacturing have been widely used in display panels.
一般常見的氧化物半導體薄膜電晶體有共平面(Coplanar)、蝕刻阻擋層(Island Stop/Etch Stop Layer,IS/ESL)和背通道蝕刻(Back Channel Etch,BCE)三種型態，其中背通道蝕刻與蝕刻阻擋層型態的氧化物半導體薄膜電晶體在元件特性及製程良率上較具有優勢。再者，背通道蝕刻結構相較於蝕刻阻擋層結構可進一步減省一道光罩製程，因此更具優勢。 Commonly used oxide semiconductor thin film transistors have three types of Coplanar, Island Stop/Etch Stop Layer (IS/ESL) and Back Channel Etch (BCE), in which back channel etching The oxide semiconductor thin film transistor with an etch barrier type is superior in element characteristics and process yield. Moreover, the back channel etch structure can further reduce a mask process compared to the etch stop structure, and thus is more advantageous.
然而，在背通道蝕刻型態之氧化物半導體薄膜電晶體的製程中，用以圖案化通道層之光阻會直接接觸到通道層，且光阻含有會影響電晶體之次臨限斜率(Subthreshold Swing，S.S.)的有機物溶劑，故導致電晶體的電器特性以及穩定性不佳。 However, in the process of back-channel etched type oxide semiconductor thin film transistor, the photoresist used to pattern the channel layer directly contacts the channel layer, and the photoresist contains a secondary threshold that affects the transistor (Subthreshold) Swing, SS) organic solvent, resulting in poor electrical properties and stability of the transistor.
本發明提供一種電晶體及其製造方法，能夠避免通道層受到損傷。 The present invention provides a transistor and a method of manufacturing the same that can avoid damage to the channel layer.
本發明提供一種電晶體的製造方法，其包括下列步驟。首先，於基板上形成閘極，並於基板以及閘極上形成閘絕緣層以覆蓋基板以及閘極。接著，於閘絕緣層上形成圖案化通道層以及遮罩層，其中圖案化通道層與遮罩層位於閘極上方，且遮罩層位於圖案化通道層上。之後，藉由濕式蝕刻劑於閘絕緣層上形成一源極與一汲極，並且藉由濕式蝕刻劑移除未被源極與汲極覆蓋之遮罩層的部分直到圖案化通道層被暴露為止，以形成多個圖案化遮罩層。 The present invention provides a method of manufacturing a transistor comprising the following steps. First, a gate is formed on the substrate, and a gate insulating layer is formed on the substrate and the gate to cover the substrate and the gate. Next, a patterned via layer and a mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the mask layer are above the gate, and the mask layer is on the patterned channel layer. Thereafter, a source and a drain are formed on the gate insulating layer by a wet etchant, and a portion of the mask layer not covered by the source and the drain is removed by a wet etchant until the patterned channel layer is patterned. It is exposed to form a plurality of patterned mask layers.
在本發明之一實施例中，上述之圖案化遮罩層之材質與源極及汲極之至少部分材質相同。 In an embodiment of the invention, the material of the patterned mask layer is the same as the material of at least part of the source and the drain.
在本發明之一實施例中，上述圖案化遮罩層之材質包括金屬或不含錫之氧化物半導體，而圖案化通道層之材質包括含錫之氧化物半導體或多晶型之氧化銦鎵(poly-Indium-Gallium Oxide,poly-IGO)。 In an embodiment of the invention, the material of the patterned mask layer comprises a metal or an oxide semiconductor containing no tin, and the material of the patterned channel layer comprises an oxide semiconductor containing tin or a polycrystalline indium gallium oxide. (poly-Indium-Gallium Oxide, poly-IGO).
在本發明之一實施例中，上述圖案化通道層之片電阻值(sheet resistance)介於107歐母/單位面積至1010歐母/單位面積之間。 In one embodiment of the invention, the sheet resistance of the patterned channel layer is between 10 7 ohm/unit area to 10 10 ohm/unit area.
在本發明之一實施例中，上述圖案化遮罩層、源極以及汲極的形成是藉由相同的蝕刻劑(etchant)來達成。 In one embodiment of the invention, the formation of the patterned mask layer, source and drain is achieved by the same etchant.
在本發明之一實施例中，上述濕式蝕刻劑包括硫酸、磷酸、硝酸與醋酸至少二者之混合液。 In an embodiment of the invention, the wet etchant comprises a mixture of at least two of sulfuric acid, phosphoric acid, nitric acid and acetic acid.
在本發明之一實施例中，上述濕式蝕刻劑包括硫酸、磷酸、硝酸或醋酸。 In an embodiment of the invention, the wet etchant comprises sulfuric acid, phosphoric acid, nitric acid or acetic acid.
在本發明之一實施例中，上述於閘絕緣層上形成圖案化通道層以及遮罩層的方法包括：於絕緣層上依序形成一通道材料層以及一遮罩材料層；於遮罩材料層上形成一第一圖案化光阻層，並以該第一圖案化光阻層為罩幕，移除部分未被第一圖案化光阻層覆蓋之通道材料層以及遮罩材料層，以形成圖案化通道層以及遮罩層；以及移除第一圖案化光阻層。 In an embodiment of the invention, the method for forming a patterned channel layer and a mask layer on the gate insulating layer comprises: sequentially forming a channel material layer and a mask material layer on the insulating layer; and the mask material Forming a first patterned photoresist layer on the layer, and using the first patterned photoresist layer as a mask, removing a portion of the channel material layer and the mask material layer not covered by the first patterned photoresist layer, Forming a patterned channel layer and a mask layer; and removing the first patterned photoresist layer.
在本發明之一實施例中，上述於形成源極、汲極與圖案化遮罩層的方法包括：於圖案化通道層以及遮罩層上形成一金屬材料層；於金屬材料層上形成一第二圖案化光阻層，並以第二圖案化光阻層為罩幕，藉由濕式蝕刻劑，移除未被第二圖案化光阻層覆蓋之金屬材料層，以形成源極與汲極；以及藉由濕式蝕刻劑，移除位於源極與汲極之間未被第二圖案化光阻層覆蓋之遮罩層，以形成圖案化遮罩層。 In an embodiment of the invention, the method for forming a source, a drain, and a patterned mask layer includes: forming a metal material layer on the patterned channel layer and the mask layer; forming a layer on the metal material layer The second patterned photoresist layer is coated with the second patterned photoresist layer, and the metal material layer not covered by the second patterned photoresist layer is removed by a wet etchant to form a source and a source. a drain layer; and a mask layer between the source and the drain that is not covered by the second patterned photoresist layer is removed by a wet etchant to form a patterned mask layer.
在本發明之一實施例中，上述濕式蝕刻劑對於源極與汲極的蝕刻速率為VSD，濕式蝕刻劑對於圖案化通道層的蝕刻速率為VCH，而濕式蝕刻劑對於遮罩層的蝕刻速率為VHM，且VSD、VCH與VHM滿足下列關係式：10VHM/VCH 100；以及0.1VSD/VHM 10。 In an embodiment of the invention, the wet etchant has an etch rate of V SD for the source and the drain, the etch rate of the wet etchant for the patterned via layer is V CH , and the wet etchant for the mask The etch rate of the cap layer is V HM , and V SD , V CH and V HM satisfy the following relationship: 10 V HM /V CH 100; and 0.1 V SD /V HM 10.
本發明提出一種電晶體，其包括一閘極、一閘絕緣層、一圖案化通道層、多個圖案化遮罩層以及一源極與一汲極。閘絕緣層覆蓋閘極。圖案化通道層配置於閘絕緣層上且位於閘極上方，其中圖案化通道層之片電阻值介於107歐母/單位面積至1010歐母/單位面積之間。圖案化遮罩層配置於圖案化通道層上。源極與汲極設置於閘絕緣層上，其中圖案化遮罩層位於源極與圖案化通道層之間以及汲極與圖案化通道層之間。 The invention provides a transistor comprising a gate, a gate insulating layer, a patterned channel layer, a plurality of patterned mask layers, and a source and a drain. The gate insulation covers the gate. The patterned channel layer is disposed on the gate insulating layer and above the gate, wherein the patterned channel layer has a sheet resistance value between 10 7 ohm/unit area and 10 10 ohm/unit area. The patterned mask layer is disposed on the patterned channel layer. The source and the drain are disposed on the gate insulating layer, wherein the patterned mask layer is located between the source and the patterned channel layer and between the drain and the patterned channel layer.
在本發明之一實施例中，上述圖案化遮罩層之材質包括不含錫之氧化物半導體，而圖案化通道層之材質包括含錫之氧化物半導體或多晶型之氧化銦鎵。 In an embodiment of the invention, the material of the patterned mask layer comprises an oxide semiconductor containing no tin, and the material of the patterned channel layer comprises an oxide semiconductor containing tin or a polycrystalline indium gallium oxide.
在本發明之一實施例中，上述圖案化遮罩層之材質包括銦鎵氧化物(Indium-Gallium Oxide,IGO)、銦鋅氧化物(Indium-Zinc Oxide,IZO)、銦鎵鋅氧化物(Indium-Gallium-Zinc Oxide,IGZO)、摻雜鋁氧化鋅(Al-doped ZnO,AZO)、氧化鋅(Zinc Oxide,ZnO)、氧化銦(indium oxide,In2O3)或氧化鎵(Gallium oxide,Ga2O3)，而圖案化通道層之材質包括銦錫鋅氧化物(Indium-Tin-Zinc Oxide, ITZO)、鋅錫氧化物(Zinc-Tin Oxide,ZTO)、摻雜銦之鋅錫氧化物(Zinc-Tin Oxide：Indium,ZTO：In)、摻雜鎵之鋅錫氧化物(Zinc-Tin Oxide：Gallium,ZTO：Ga)、摻雜錫之銦鎵鋅氧化物(Indium-Gallium-Zinc Oxide：Stannum,IGZO：Sn)、鎵錫氧化物(Gallium-Tin Oxide,GTO)、銦鎵錫氧化物(Indium-Gallium-Tin Oxide,IGTO)或多晶型之氧化銦鎵(poly-IGO)。 In an embodiment of the invention, the material of the patterned mask layer comprises Indium-Gallium Oxide (IGO), Indium-Zinc Oxide (IZO), Indium Gallium Zinc Oxide (Indium-Zinc Oxide (IZO)) Indium-Gallium-Zinc Oxide, IGZO), Al-doped ZnO (AZO), Zinc Oxide (ZnO), Indium Oxide (In 2 O 3 ) or Gallium Oxide (Gallium oxide) , Ga 2 O 3 ), and the material of the patterned channel layer includes Indium-Tin-Zinc Oxide (ITZO), Zinc-Tin Oxide (ZTO), and zinc-doped indium Oxide (Zinc-Tin Oxide: Indium, ZTO: In), gallium-doped zinc tin oxide (Zinc-Tin Oxide: Gallium, ZTO: Ga), tin-doped indium gallium zinc oxide (Indium-Gallium- Zinc Oxide: Stannum, IGZO: Sn), Gallium-Tin Oxide (GTO), Indium-Gallium-Tin Oxide (IGTO) or polycrystalline indium gallium oxide (poly-IGO) ).
在本發明之一實施例中，上述圖案化遮罩層暴露出部分之圖案化通道層。 In one embodiment of the invention, the patterned mask layer exposes a portion of the patterned channel layer.
基於上述，本發明之電晶體及其製造方法可避免通道層直接與光阻接觸，進而使電晶體具有較佳之次臨限斜率(S.S.)以及穩定性。 Based on the above, the transistor of the present invention and the method of fabricating the same can prevent the channel layer from directly contacting the photoresist, thereby providing the transistor with a better secondary slope (S.S.) and stability.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
100‧‧‧基板 100‧‧‧Substrate
102‧‧‧閘極 102‧‧‧ gate
104‧‧‧閘絕緣層 104‧‧‧Brake insulation
106’‧‧‧通道材料層 106’‧‧‧Channel material layer
106‧‧‧圖案化通道層 106‧‧‧ patterned channel layer
108’‧‧‧遮罩材料層 108’‧‧‧Material layer
108‧‧‧遮罩層 108‧‧‧mask layer
108a、108b‧‧‧圖案化遮罩層 108a, 108b‧‧‧ patterned mask layer
110‧‧‧第一圖案化光阻層 110‧‧‧First patterned photoresist layer
112‧‧‧金屬材料層 112‧‧‧Metal material layer
112a‧‧‧源極 112a‧‧‧ source
112b‧‧‧汲極 112b‧‧‧汲polar
114‧‧‧第二圖案化光阻層 114‧‧‧Second patterned photoresist layer
圖1A至圖1G是依照本發明之一實施例之一種電晶體的製造流程示意圖。 1A to 1G are schematic views showing a manufacturing process of a transistor according to an embodiment of the present invention.
圖2為在攝氏溫度40度的情況下，以鋁酸蝕刻液分別對鉬、銦鎵鋅氧化物以及銦錫鋅氧化物的蝕刻選擇比。 2 is an etching selectivity ratio of molybdenum, indium gallium zinc oxide, and indium tin zinc oxide by an alumina etchant at a temperature of 40 degrees Celsius.
圖3A為本發明之一實施例的電晶體之特性曲線圖。 3A is a characteristic diagram of a transistor according to an embodiment of the present invention.
圖3B為習知的電晶體之特性曲線圖。 Fig. 3B is a characteristic diagram of a conventional transistor.
圖1A至圖1G是依照本發明之第一實施例之一種電晶體的製造流程示意圖。請參照圖1A，首先，提供基板100，並於基板100上形成閘極102。在本實施例中，基板100例如為硬質基板(rigid substrate)或可撓式基板(flexible substrate)等。舉例而言，硬質基板可為玻璃基板，而可撓式基板可為塑膠基板。此外，閘極102例如是單層或多層堆疊之金屬材料，例如選自由銅(Copper,Cu)、鉬(Molybdenum,Mo)、鈦(Titanium,Ti)、鋁(Aluminum,Al)、鎢(Tungsten,W)、銀(Silver,Ag)、金(Gold,Au)及其合金所組成之族群中的至少之一，且閘極102可透過微影蝕刻製程來圖案化金屬材料而製作。 1A to 1G are schematic views showing a manufacturing process of a transistor according to a first embodiment of the present invention. Referring to FIG. 1A, first, a substrate 100 is provided, and a gate 102 is formed on the substrate 100. In the present embodiment, the substrate 100 is, for example, a rigid substrate or a flexible substrate. For example, the rigid substrate may be a glass substrate, and the flexible substrate may be a plastic substrate. In addition, the gate 102 is, for example, a single layer or a plurality of stacked metal materials, for example selected from the group consisting of copper (Copper, Cu), molybdenum (Mo), titanium (Titanium, Ti), aluminum (Aluminum, Al), and tungsten (Tungsten). At least one of the group consisting of W), silver (Silver, Ag), gold (Gold, Au), and alloys thereof, and the gate 102 can be fabricated by patterning a metal material through a photolithography process.
請參照圖1B，接著，於基板100以及閘極102上形成閘絕緣層104，其中閘絕緣層104同時覆蓋基板100以及閘極102。在本實施例中，閘絕緣層104可為單層結構或多層堆疊的複合結構，且閘絕緣層104之材質例如是氮化矽、氧化矽、氮氧化矽或其他合適之介電材料。 Referring to FIG. 1B, a gate insulating layer 104 is formed on the substrate 100 and the gate 102, wherein the gate insulating layer 104 covers both the substrate 100 and the gate 102. In the present embodiment, the gate insulating layer 104 may be a single-layer structure or a multi-layer stacked composite structure, and the material of the gate insulating layer 104 is, for example, tantalum nitride, hafnium oxide, hafnium oxynitride or other suitable dielectric material.
請參照圖1C，在完成閘絕緣層104的製作之後，在閘絕緣層104上形成通道材料層106’以及遮罩材料層108’。詳言之，在閘絕緣層104形成之後，在閘絕緣層104上依序形成通道材料層106’、遮罩材料層108’以及第一圖案化光阻層110，其中通道材料層106’覆蓋於閘絕緣層104上，而遮罩材料層108’覆蓋於通 道材料層106’上，且第一圖案化光阻層110配置於遮罩材料層108’的局部區域上，其中第一圖案化光阻層110位於閘極102的上方。 Referring to FIG. 1C, after the fabrication of the gate insulating layer 104 is completed, a channel material layer 106' and a mask material layer 108' are formed on the gate insulating layer 104. In detail, after the gate insulating layer 104 is formed, the channel material layer 106', the mask material layer 108', and the first patterned photoresist layer 110 are sequentially formed on the gate insulating layer 104, wherein the channel material layer 106' is covered. On the gate insulating layer 104, and the mask material layer 108' is overlaid The first patterned photoresist layer 110 is disposed on a partial region of the mask material layer 108', wherein the first patterned photoresist layer 110 is above the gate 102.
請同時參照圖1C與圖1D，在形成第一圖案化光阻層110之後，接著以第一圖案化光阻層110為罩幕，移除未被第一圖案化光阻層110所覆蓋之部分通道材料層106’以及部分遮罩材料層108’，以形成圖案化通道層106以及遮罩層108。在本實施例中，由於圖案化通道層106不會與圖案化光阻層110直接接觸，因此圖案化光阻層110中所含的有機物溶劑不易對圖案化通道層106造成損傷。 Referring to FIG. 1C and FIG. 1D simultaneously, after the first patterned photoresist layer 110 is formed, the first patterned photoresist layer 110 is used as a mask to remove the first patterned photoresist layer 110. A portion of the channel material layer 106' and a portion of the mask material layer 108' form a patterned channel layer 106 and a mask layer 108. In the present embodiment, since the patterned channel layer 106 does not directly contact the patterned photoresist layer 110, the organic solvent contained in the patterned photoresist layer 110 is less likely to cause damage to the patterned channel layer 106.
在本發明之一實施例中，圖案化通道層106的材質可包括含錫之氧化物半導體或多晶型之氧化銦鎵(poly-IGO)，例如是銦錫鋅氧化物(ITZO)、鋅錫氧化物(ZTO)、摻雜銦之鋅錫氧化物(ZTO：In)、摻雜鎵之鋅錫氧化物(ZTO：Ga)、摻雜錫之銦鎵鋅氧化物IGZO：Sn)、鎵錫氧化物(GTO)或銦鎵錫氧化物(IGTO)等，其中圖案化通道層106的片電阻值(sheet resistance)介於107歐母/單位面積至1010歐母/單位面積之間。此外，遮罩層108之材質可包括金屬或不含錫之氧化物半導體，例如是銦鎵氧化物(IGO)、銦鋅氧化物(IZO)、銦鎵鋅氧化物(IGZO)、摻雜鋁氧化鋅(AZO)、氧化鋅(ZnO)、氧化銦(In2O3)或氧化鎵(Ga2O3)等。為方便描述，以下將以圖案化通道層106的材質為銦錫鋅氧化物(ITZO)以及遮罩層108之材質為銦鎵鋅氧化物(IGZO)為例說明，但本發明不限定於此。 In an embodiment of the present invention, the material of the patterned channel layer 106 may include a tin-containing oxide semiconductor or a polycrystalline indium gallium oxide (poly-IGO), such as indium tin zinc oxide (ITZO), zinc. Tin oxide (ZTO), indium-doped zinc-tin oxide (ZTO:In), gallium-doped zinc-tin oxide (ZTO:Ga), tin-doped indium gallium zinc oxide IGZO:Sn), gallium Tin oxide (GTO) or indium gallium tin oxide (IGTO), etc., wherein the sheet resistance of the patterned channel layer 106 is between 10 7 ohm/unit area to 10 10 ohm/unit area . In addition, the material of the mask layer 108 may include a metal or an oxide semiconductor containing no tin, such as indium gallium oxide (IGO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), doped aluminum. Zinc oxide (AZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) or gallium oxide (Ga 2 O 3 ). For convenience of description, the material of the patterned channel layer 106 is indium tin zinc oxide (ITZO) and the material of the mask layer 108 is indium gallium zinc oxide (IGZO) as an example. However, the present invention is not limited thereto. .
請參照圖1E，在完成圖案化通道層106以及遮罩層108 的製作後，移除覆蓋於遮罩層108上的第一圖案化光阻層110，接著，再於遮罩層108以及閘絕緣層104上形成金屬材料層112。之後，在金屬材料層112上形成一第二圖案化光阻層114，此第二圖案化光阻層114是用以定義後續欲形成之源極與汲極(未繪示)之圖案。如圖1E所示，第二圖案化光阻層114配置在金屬材料層112上，且對應於部份的遮罩層108以及部份的閘絕緣層104上方。承上述，金屬材料層112可以為單層結構或多層堆疊的複合結構，且其材質例如是鋁(Al)、鉬(Mo)、銀(Ag)、鈀(Palladium,Pd)或其合金等金屬材料。金屬材料層112之材質可與閘極102之材質相同或不同。以下將以金屬材料層112之材質為鉬/鋁/鉬(Mo/Al/Mo)為例，進行實施例之說明。值得注意的是，本實施例不限定金屬材料層112必須為鉬/鋁/鉬(Mo/Al/Mo)疊層。 Referring to FIG. 1E, the patterned channel layer 106 and the mask layer 108 are completed. After the fabrication, the first patterned photoresist layer 110 overlying the mask layer 108 is removed, and then the metal material layer 112 is formed over the mask layer 108 and the gate insulating layer 104. Then, a second patterned photoresist layer 114 is formed on the metal material layer 112. The second patterned photoresist layer 114 is used to define a pattern of a source and a drain (not shown) to be subsequently formed. As shown in FIG. 1E, the second patterned photoresist layer 114 is disposed on the metal material layer 112 and corresponds to a portion of the mask layer 108 and a portion of the gate insulating layer 104. In the above, the metal material layer 112 may be a single layer structure or a multi-layer stacked composite structure, and the material thereof is, for example, metal such as aluminum (Al), molybdenum (Mo), silver (Ag), palladium (Palladium) or its alloy. material. The material of the metal material layer 112 may be the same as or different from the material of the gate 102. Hereinafter, the description of the embodiment will be made by taking the material of the metal material layer 112 as molybdenum/aluminum/molybdenum (Mo/Al/Mo) as an example. It should be noted that this embodiment does not limit the metal material layer 112 to be a molybdenum/aluminum/molybdenum (Mo/Al/Mo) laminate.
請參照圖1E與圖1F，在形成第二圖案化光阻層114之後，藉由濕式蝕刻劑移除未被第二圖案化光阻層114所覆蓋的金屬材料層112以及未被第二圖案化光阻層114所覆蓋的遮罩層108，以完成源極112a與汲極112b的製作，並使遮罩層108能夠進一步被圖案化為圖案化遮罩層108a、108b。在此，如圖1F所示，圖案化遮罩層108a、108b的數量為二，但本發明並不限定於此。接著，如圖1F所示，源極112a與汲極112b覆蓋於圖案化遮罩層108a、108b以及部分的閘絕緣層104上。具體而言，在本發明之一實施例中，圖案化遮罩層108a、108b、源極112a以及汲極112b可藉由相同的濕式蝕刻劑(etchant)蝕刻所形成，濕式蝕刻劑例如為 硫酸、磷酸、硝酸與醋酸或至少上述二者之混合。在其他實施例中，濕式蝕刻劑亦可為鋁酸蝕刻液。換言之，當濕式蝕刻劑對於源極112a與汲極112b的蝕刻速率為VSD，濕式蝕刻劑對於圖案化通道層106的蝕刻速率為VCH，而濕式蝕刻劑對於遮罩層108的蝕刻速率為VHM，則VSD、VCH與VHM滿足下列關係式：10VHM/VCH 100；以及0.1VSD/VHM 10。 Referring to FIG. 1E and FIG. 1F, after the second patterned photoresist layer 114 is formed, the metal material layer 112 not covered by the second patterned photoresist layer 114 is removed by the wet etchant and is not second. The mask layer 108 covered by the photoresist layer 114 is patterned to complete the fabrication of the source 112a and the drain 112b, and the mask layer 108 can be further patterned into the patterned mask layers 108a, 108b. Here, as shown in FIG. 1F, the number of patterned mask layers 108a, 108b is two, but the present invention is not limited thereto. Next, as shown in FIG. 1F, the source 112a and the drain 112b cover the patterned mask layers 108a, 108b and a portion of the gate insulating layer 104. In particular, in one embodiment of the invention, the patterned mask layers 108a, 108b, the source 112a, and the drain 112b may be formed by the same wet etchant etching, such as a wet etchant such as It is a mixture of sulfuric acid, phosphoric acid, nitric acid and acetic acid or at least two of the above. In other embodiments, the wet etchant can also be an alumina acid etchant. In other words, when the etch rate of the wet etchant for the source 112a and the drain 112b is V SD , the etch rate of the wet etchant to the patterned via layer 106 is V CH , and the wet etchant for the mask layer 108 The etch rate is V HM , then V SD , V CH and V HM satisfy the following relationship: 10 V HM /V CH 100; and 0.1 V SD /V HM 10.
請同時參照圖1F與圖1G，在源極112a以及汲極112b形成之後，移除第二圖案化光阻層114，即初步完成電晶體的製作。如圖1G所示，本實施例之電晶體包括閘極102、閘絕緣層104、圖案化通道層106、圖案化遮罩層108a、108b以及一源極112a與一汲極112b。閘絕緣層104覆蓋閘極102。圖案化通道層106配置於閘絕緣層104上且位於閘極102上方，其中圖案化通道層106之片電阻值介於107歐母/單位面積至1010歐母/單位面積之間。圖案化遮罩層108a、108b配置於圖案化通道層106上。源極112a與汲極112b設置於閘絕緣層104上，其中圖案化遮罩層108a、108b位於源極112a與圖案化通道層106之間以及汲極112b與圖案化通道層106之間。 Referring to FIG. 1F and FIG. 1G simultaneously, after the source 112a and the drain 112b are formed, the second patterned photoresist layer 114 is removed, that is, the fabrication of the transistor is completed. As shown in FIG. 1G, the transistor of the present embodiment includes a gate 102, a gate insulating layer 104, a patterned via layer 106, patterned mask layers 108a, 108b, and a source 112a and a drain 112b. The gate insulating layer 104 covers the gate 102. The patterned channel layer 106 is disposed on the gate insulating layer 104 and above the gate 102, wherein the patterned channel layer 106 has a sheet resistance value between 10 7 ohms/unit area and 10 10 ohms/unit area. The patterned mask layers 108a, 108b are disposed on the patterned channel layer 106. The source 112a and the drain 112b are disposed on the gate insulating layer 104, wherein the patterned mask layers 108a, 108b are located between the source 112a and the patterned via layer 106 and between the drain 112b and the patterned via layer 106.
圖2為在攝氏溫度40度的情況下，以鋁酸蝕刻液分別對鉬(Mo)、銦鎵鋅氧化物(IGZO)以及銦錫鋅氧化物(ITZO)進行蝕刻的蝕刻選擇比。請同時參照圖1E、圖1F與圖2所示，在攝氏溫度40度的情況下，鋁酸蝕刻液對於鉬(Mo)的蝕刻速率為V1，鋁 酸蝕刻液對於銦鎵鋅氧化物(IGZO)的蝕刻速率為V2，而鋁酸蝕刻液對於銦錫鋅氧化物(ITZO)的蝕刻速率為V3，且V1：V2：V3為1：0.1：0.001。換言之，當源極112a與汲極112b的材質為鉬/鋁/鉬(Mo/Al/Mo)、遮罩層108的材質為銦鎵鋅氧化物(IGZO)，且圖案化通道層106的材質為銦錫鋅氧化物(ITZO)時，鋁酸蝕刻液可以有效的蝕刻金屬材料層112以及遮罩層108以形成源極112a、汲極112b以及圖案化遮罩層108a、108b，但不會過度的損害圖案化通道層106。 2 is an etching selectivity ratio of molybdenum (Mo), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO) etched with an aluminate etching solution at a temperature of 40 degrees Celsius. Please also refer to FIG. 1E, FIG. 1F and FIG. 2, the etching rate of the alumina acid etching solution for molybdenum (Mo) is V1 at 40 degrees Celsius, aluminum The etching rate of the acid etching solution for indium gallium zinc oxide (IGZO) is V2, and the etching rate of the aluminum acid etching solution for indium tin zinc oxide (ITZO) is V3, and V1:V2:V3 is 1:0.1:0.001 . In other words, when the source 112a and the drain 112b are made of molybdenum/aluminum/molybdenum (Mo/Al/Mo), the mask layer 108 is made of indium gallium zinc oxide (IGZO), and the material of the patterned channel layer 106 is used. When it is indium tin zinc oxide (ITZO), the aluminum acid etching solution can effectively etch the metal material layer 112 and the mask layer 108 to form the source 112a, the drain 112b, and the patterned mask layers 108a, 108b, but not Excessive damage patterns the channel layer 106.
舉例而言，當遮罩層108形成厚度為10~40奈米(nm)且金屬材料層112形成厚度為400~500奈米(nm)時，則遮罩層108未被第二圖案化光阻層114覆蓋的部份，亦即遮罩層108未被上述的源極112a與汲極112b覆蓋之的部分，將會被移除直至圖案化通道層106被暴露為止，也就是遮罩層108暴露出部分之圖案化通道層106，由此遮罩層108被蝕刻而形成分隔為兩部分的圖案化遮罩層108a、108b，此時，再移除第二圖案化光阻層114之後，則可實現一電晶體結構，如圖1G中所示。 For example, when the mask layer 108 is formed to have a thickness of 10 to 40 nanometers (nm) and the metal material layer 112 is formed to have a thickness of 400 to 500 nanometers (nm), the mask layer 108 is not patterned by the second pattern. The portion of the resist layer 114, that is, the portion of the mask layer 108 that is not covered by the source 112a and the drain 112b, will be removed until the patterned channel layer 106 is exposed, that is, the mask layer. 108 exposing a portion of the patterned channel layer 106, whereby the mask layer 108 is etched to form a patterned mask layer 108a, 108b that is divided into two portions, at which time, after removing the second patterned photoresist layer 114 , a transistor structure can be realized, as shown in FIG. 1G.
此外，在本發明之另一實施例中，遮罩層108之材質以及源極112a與汲極112b之至少部分材質相同，例如為鋁、鉬、銀、鈀(Pd)或其合金等金屬材料等。如上所述，遮罩層108、源極112a以及汲極112b可藉由相同的蝕刻劑蝕刻所形成，在此省略後續重複敘述。 In addition, in another embodiment of the present invention, the material of the mask layer 108 and at least part of the source 112a and the drain 112b are made of the same material, for example, a metal material such as aluminum, molybdenum, silver, palladium (Pd) or alloy thereof. Wait. As described above, the mask layer 108, the source electrode 112a, and the drain electrode 112b can be formed by the same etchant etching, and the subsequent repeated description is omitted here.
圖3A為本發明一實施例之電晶體的特性曲線圖，其中本
發明電晶體之圖案化通道層的材質為銦錫鋅氧化物(ITZO)，圖案化遮罩層之材質為銦鎵鋅氧化物(IGZO)；而圖3B為習知的電晶體之特性曲線圖，其中習知電晶體之通道層的材質為銦錫鋅氧化物(ITZO)，但不具有圖案化遮罩層。請參考圖3A與圖3B，是由在汲極與源極之間施予一汲源極電壓0.1伏特或10伏特的條件下量測閘源極電壓自-20V變化到+20V相對應的汲極電流，以縱軸表示電晶體的汲極電流(Id)與橫軸表示電晶體的閘源極電壓(Vgs)所繪製而成。在此，特別將本發明一實施例的電晶體與習知的電晶體的次臨限斜率(S.S.)、臨界電壓(Vt)以及場效應遷移率(Ufe)等數值擷取出並整理如下表1所示：
請參照表1，本發明的電晶體的次臨限斜率、臨界電壓特性參數之數值皆小於習知的電晶體，且場效應遷移率幾乎不受影響。換句話說，由於本發明的電晶體的圖案化通道層不會與圖案化光阻層直接接觸，因此圖案化光阻層中所含的有機物溶劑不易對圖案化通道層造成損傷。因此，相較於習知的電晶體，本發明 的電晶體可在幾乎不影響場效應遷移率的情況下，具有較佳的次臨限斜率及臨界電壓等特性參數。 Referring to Table 1, the values of the secondary threshold slope and the threshold voltage characteristic parameters of the transistor of the present invention are smaller than those of the conventional transistor, and the field effect mobility is hardly affected. In other words, since the patterned channel layer of the transistor of the present invention does not directly contact the patterned photoresist layer, the organic solvent contained in the patterned photoresist layer is less likely to cause damage to the patterned channel layer. Therefore, the present invention is compared to conventional transistors. The transistor can have better characteristic parameters such as secondary threshold slope and threshold voltage without affecting the field effect mobility.
綜上所述，本發明之電晶體及其製造方法可避免通道直接與光阻接觸，進而使電晶體具有較佳之次臨限斜率及臨界電壓。 In summary, the transistor of the present invention and the method of fabricating the same can prevent the channel from directly contacting the photoresist, thereby providing the transistor with a better threshold slope and a threshold voltage.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧基板 100‧‧‧Substrate
102‧‧‧閘極 102‧‧‧ gate
104‧‧‧閘絕緣層 104‧‧‧Brake insulation
106‧‧‧圖案化通道層 106‧‧‧ patterned channel layer
108a、108b‧‧‧圖案化遮罩層 108a, 108b‧‧‧ patterned mask layer
112a‧‧‧源極 112a‧‧‧ source
112b‧‧‧汲極 112b‧‧‧汲polar
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| US14/262,802 US9484441B2 (en) | 2014-01-15 | 2014-04-27 | Method for fabricating transistor having hard-mask layer |
| US15/263,394 US20160380109A1 (en) | 2014-01-15 | 2016-09-13 | Transistor having hard-mask layers |
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