TWI536383B - Operation method of resistive random access memory cell - Google Patents

Description

Resistive random access memory cell operation method

The present invention relates to an operational method, and more particularly to a method of operating a resistive random access memory cell.

Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electronic products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

However, there are still many challenges to be overcome in resistive random access memory. For example, a filament-like conductive path in a variable impedance element may be narrowed or disappeared due to high temperature, thereby affecting bit writing. Therefore, how to reduce the influence of high temperature on the filament-shaped conductive path in the variable impedance element is to design a resistive random An important issue in accessing memory.

The invention provides a method for operating a resistive random access memory cell, which can make the ions moving in the variable impedance element have a longer moving time, so as to reduce the proportion of the moving ions staying in the active layer, thereby reducing the lost ion cause. The possibility of high temperature activation and jumping back to the filamentary conductive path. Thereby, the influence of high temperature on the filament-shaped conductive path in the variable impedance element can be reduced.

The method for operating a resistive random access memory cell of the present invention, wherein the resistive random access memory cell comprises a variable impedance component and a switching component connected in series. The method of operation includes the following steps. When the switching element is turned on, a write signal is supplied to the variable impedance element to set the impedance value of the variable impedance element. During a first period, the write signal is set to a first write voltage level to deliver a first electrical energy to the variable impedance element. During a second period, a second electrical energy is transmitted to the variable impedance element through the write signal, wherein after the first period of the second period, the first electrical energy and the second electrical energy are greater than zero, and the second electrical energy is less than the first electrical energy .

Based on the above, in the method of operating the resistive random access memory cell of the embodiment of the present invention, after the period of writing the voltage, the write signal still transmits energy to the variable impedance element to maintain the thermochemical effect of the variable impedance element. Further, the moving time of oxygen ions in the variable impedance element is extended. Thereby, the moving oxygen ions are away from the filament-shaped conductive path in the variable impedance element, thereby reducing the influence of high temperature on the filament-shaped conductive path in the variable impedance element.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Resistive random access memory cells

411~412, 421~426‧‧‧ punctuation

E1‧‧‧first electrode

E2‧‧‧second electrode

FP1‧‧‧filament conductive path

GND‧‧‧ Grounding voltage

Id‧‧‧汲polar current

INO‧‧‧Oxygen ion

LM1~LM3, LM51~LM54‧‧‧ Maintain voltage level

LW1~LW4, LW51~LW54‧‧‧ write voltage level

M1‧‧‧O crystal

During the period of P21~P22, P31~P32, P51~P58, P61~P63, P71~P73‧‧

SET1~SET4‧‧‧Write combination

SM1‧‧‧Switching medium

VD‧‧‧汲polar voltage

VG‧‧‧ gate control voltage

VRE‧‧‧Variable impedance components

WRa~WRe‧‧‧ write signal

1 is a circuit diagram of a resistive random access memory cell in accordance with an embodiment of the present invention.

2 is a schematic diagram showing driving waveforms of a write signal according to a first embodiment of the present invention.

Fig. 3 is a view showing a driving waveform of a write signal in accordance with a second embodiment of the present invention.

4A and 4B are schematic diagrams showing the effect of writing a write signal according to an embodiment of the invention.

Fig. 5 is a view showing a driving waveform of a write signal in accordance with a third embodiment of the present invention.

Fig. 6 is a view showing a driving waveform of a write signal in accordance with a fourth embodiment of the present invention.

Fig. 7 is a view showing a driving waveform of a write signal in accordance with a fifth embodiment of the present invention.

1 is a diagram of a resistive random access memory cell according to an embodiment of the invention Circuit diagram. Referring to FIG. 1 , in the embodiment, the resistive random access memory cell 100 includes, for example, a variable impedance element VRE and a transistor M1 (ie, a switching element), wherein the variable impedance element VRE may be a voltage controlled switching element or Current control switching element. The variable impedance component VRE is coupled between the drain voltage VD and the drain of the transistor M1, that is, the variable impedance component VRE is connected in series with the transistor M1, and the gate of the transistor receives a gate control voltage VG, and the electrical The source of the crystal receives a ground voltage GND. Further, the variable impedance element VRE has a first electrode E1, a switching medium SM1, and a second electrode E2, wherein the material of the first electrode E1 is, for example, titanium (Ti), and the material of the switching medium SM1 is, for example, yttrium oxide ( HfO2), the material of the first electrode E1 is, for example, titanium nitride (TiN).

When the variable impedance element VRE is set, the gate control voltage VG is supplied to the gate of the transistor M1 to conduct the crystal M1, and the positive drain voltage VD (ie, the write signal WR) is supplied to the variable. The impedance element VRE is such that the oxygen ions INO in the switching medium SM1 are moved to the first electrode E1 by the influence of the gate voltage VD. At this time, oxygen vacancies are formed in the switching medium SM1 to form the filament-shaped conductive path FP1, thereby generating the drain current Id, and the drain current Id flows through the filament-shaped conductive path FP1 formed by the switching medium SM1. Due to the generation of the filament-shaped conductive path FP1, the impedance value of the switching medium SM1 is greatly reduced, that is, the switching medium SM1 is in a low-impedance state, representing a logic level "1".

On the other hand, when the variable impedance element VRE is reset, the gate control voltage VG is also supplied to the gate of the transistor M1 to conduct the transistor M1, but provides a negative polarity of the gate voltage VD to the variable impedance element. VRE to make the first electrode E1 The oxygen ion INO is moved back to the switching medium SM1 by the influence of the drain voltage VD and the drain current Id. At this time, the oxygen vacancy in the switching medium SM1 disappears, and thus the filament-shaped conductive path FP1 disappears. Due to the disappearance of the filament-shaped conductive path FP1, the impedance value of the switching medium SM1 is greatly increased, that is, the switching medium SM1 is in a high-impedance state, representing a logic level “0”.

Further, when the variable impedance element VRE is a voltage control switching element, the gate control voltage VG may be higher than the gate voltage VD. When the variable impedance element VRE is a current control switching element, the gate control voltage VG may be lower than the gate voltage VD.

2 is a schematic diagram showing driving waveforms of a write signal according to a first embodiment of the present invention. Please refer to FIG. 1 and FIG. 2, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the write signal WRa is used to set the variable impedance element VRE. That is, when the transistor M1 is turned on, the write signal WRa is supplied to the variable impedance element VRE to set the impedance value of the variable impedance element VRE.

In the period P21 (corresponding to the first period), the write signal WRa is set to the write voltage level LW1 (corresponding to the first write voltage level) to initiate the movement of the oxygen ions INO in the switching medium SM1, and then A filament-shaped conductive path FP1 is formed in the variable impedance element VRE. Next, in the period P22 (corresponding to the second period), the set write signal WRa is decremented from the write voltage level LW1 to the ground voltage (ie, the voltage level 0) to extend the moving time of the oxygen ions INO in the switching medium SM1. The formation of the filament-shaped conductive path is increased, wherein the decrement period in which the write signal WRa is decremented from the write voltage level LW1 to the ground voltage is assumed to be equal to the period P22.

In other words, in the period P21, the write signal WRa is set to be written. The pressing level LW1 transmits a larger first electric energy (corresponding to the product of the writing voltage level LW1 and the length of the period P21) to the variable impedance element VRE to trigger the switching medium SM1 to form the filament-shaped conductive path FP1. And, in the period P22 subsequent to the period P21, the second power smaller than the first power (half the product of the time length of the write voltage level LW1 and the period P22) is transmitted through the write signal WRa to Variable impedance element VRE.

In the present embodiment, the length of the period P22 is equal to half of the length of the period P21, but in other embodiments, the length of the period P22 may be equal to 0.5 to 3 times the length of the period P21, but the embodiment of the present invention Not limited to this.

Fig. 3 is a view showing a driving waveform of a write signal in accordance with a second embodiment of the present invention. 1 and 3, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the write signal WRb is also used to set the variable impedance element VRE. That is, when the transistor M1 is turned on, the write signal WRb is supplied to the variable impedance element VRE to set the impedance value of the variable impedance element VRE.

In the period P31 (corresponding to the first period), the write signal WRb is set to the write voltage level LW2 (corresponding to the first write voltage level), that is, the pulse wave having the voltage level of the write voltage level LW2 is formed. In order to initiate the movement of the oxygen ions INO in the switching medium SM1, a filament-shaped conductive path is formed in the variable impedance element VRE. Then, in the entire period P32 (corresponding to the second period), the write signal WRb is set to the sustain voltage level LM1 (corresponding to the first sustain level), that is, the pulse wave whose voltage level is the sustain voltage level LM1 is formed. In order to extend the moving time of the oxygen ions INO in the switching medium SM1, the formation of the filament-shaped conductive path FP1 is increased.

In other words, in the period P31, the write signal WRB is set to the write voltage level LW2 to transfer a larger first electric energy (corresponding to the product of the writing voltage level LW2 and the length of the period P31) to the variable impedance. The element VRE is used to trigger the switching medium SM1 to form a filament-shaped conductive path FP1. Further, in the period P32 after the period P31, the second electric energy (corresponding to the product of the length of the sustain voltage level LM1 and the period P32) smaller than the first electric energy is transmitted to the variable impedance element VRE through the write signal WRb.

In the present embodiment, the sustain voltage level LM1 is equal to half (i.e., 1/2 times) of the write voltage level LW2, and the period P31 is not adjacent to the period P32, and the length of time of the period P32 is equal to the length of the period P31. However, in other embodiments, the sustain voltage level LM1 may be equal to 1/3~2/3 times of the write voltage level LW2, and the period P31 may be adjacent to the period P32, and the length of the period P32 may be equal to the period The time length of the P31 is 0.5 to 3 times, but the embodiment of the present invention is not limited thereto. In addition, the interval between the periods P31 and P32 may be set to be less than the length of the period P31, but the embodiment is not limited thereto.

In the first and second embodiments of the present invention, since the write signal WR is set to the write voltage level (e.g., LW1, LW2) during the first period (corresponding period P21, period P31), a thermochemical effect may occur. The resulting filament-like conductive path FP1 is narrowed or disappeared by the influence of high temperature. Therefore, the present invention reduces the write signal WR to the ground voltage or the write voltage level (eg, LW1) by setting the write signal WR to the self-write voltage level (eg, LW1, LW2) during the second period (corresponding period P22, period P32). , LW2) maintain voltage level (such as LM1), can extend the oxygen in the switching medium SM1 The movement time of the ion INO increases the formation of the filament-like conductive path FP1 and slows down the influence of the high temperature generated by the thermochemical effect on the filament-shaped conductive path FP1.

4A and FIG. 4B are schematic diagrams showing the effect of writing a write signal according to an embodiment of the present invention, wherein FIG. 4A is an example of a voltage-controlled switching variable impedance element VRE, and FIG. 4B is a current control switching. The variable impedance element VRE is taken as an example. Please refer to FIG. 1 to FIG. 3 and FIG. 4A , wherein the coordinate point 411 is used to indicate that the write signal WR only includes the first period (eg, P21, P31), and the bit error rate after the thermal test and the thermal test. Correspondence relationship, the coordinate point 412 is used to indicate that the write signal WR includes the first period (such as P21, P31) and the second period (such as P22, P32), the writing effect is before the thermal test and after the thermal test. The correspondence between the correct rates of the elements. Also, the above thermal test may be performed at 175 degrees Celsius for 24 hours.

Referring to FIG. 1 to FIG. 3 and FIG. 4B, the coordinate point 421 is used to indicate the writing effect of the write signal WR including only the first period (such as P21 and P31) for setting and resetting, and the coordinate point 422~ 426 is used to indicate the write effect of the write signal WR including the first period (such as P21, P31) and the second period (such as P22, P32) for setting and resetting, wherein the above setting is, for example, greater than 10μ. Ampere's current is applied, and the above reset is performed, for example, at a current of more than 5 μ Amperes, and the above-described writing effect is a thermally tested effect, for example, baking at 175 ° C for 24 hours.

Moreover, the coordinate points 422-426 indicate the length of time of different first periods (such as P21, P31), the length of time of different second periods (such as P22, P32), different write voltage levels (such as LW1, LW2), and Different sustain voltage levels (eg LM1) The combined write effect.

4A and 4B, the embodiment of the present invention has a higher bit correctness, that is, the high temperature has a lower influence on the filament-shaped conductive path FP1 formed in the switching medium SM1 via the embodiment of the present invention.

Fig. 5 is a view showing a driving waveform of a write signal in accordance with a third embodiment of the present invention. Please refer to FIG. 1, FIG. 3 and FIG. 5, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the write signal WRc is divided into a period P51 (corresponding to the first period), a period P52 (corresponding to the second period), periods P53, P55, and P57 (corresponding to a plurality of third periods), periods P54, P56, and P58 (corresponding to a plurality of fourth periods) and having 4 reading time points 510, 520, 530 and 540. The two adjacent periods can be regarded as a write combination (such as SET1~SET4), and the action of each write combination can be referred to the embodiment of FIG. 3, and details are not described herein again.

During the periods P51, P53, P55, and P57 (corresponding to the first period and the plurality of third periods), the write signal WRc is sequentially set to the write voltage levels LW51 and LW52 to LW54 (corresponding to the first write voltage level) The bit and the plurality of second write voltage levels) sequentially transmit a plurality of electrical energy (corresponding to the first electrical energy and the plurality of third electrical energy) to the variable impedance element VRE. In the periods P52, P54, P56, and P58 (corresponding to the second period and the plurality of fourth periods), the write signal WRc is sequentially set to the sustain voltage levels LM51 and LM52 to LM54 (corresponding to the first sustain voltage level and a plurality of second sustain voltage levels) sequentially transmitting a plurality of electrical energy (corresponding to the second electrical energy and the plurality of fourth electrical energy) to the variable impedance element VRE, wherein the periods P52, P54, P56, and P58 are respectively located during the periods P51, P53 After P55 and P57. And, the write signal WRc is during The power transmitted by P52 is less than the power transmitted by the write signal WRc during the period P51, and the power transmitted by the write signal WRc during the periods P54, P56, and P58 is less than and the write signal WRc is transmitted during the periods P53, P55, and P57. Electrical energy.

Further, after writing by the write combination SET1, write verification is performed at the reading time point 510. When the verification is correct, it is determined that the resistive random access memory cell 100 is usable and no longer writes; when the verification is an error, the write is performed via the write combination SET2, and at the time of reading 520 performs write verification. When the verification is correct, it is determined that the resistive random access memory cell 100 is usable and no longer writes; when the verification is an error, the write is performed via the write combination SET3, and at the time of reading 530 performs write verification. When the verification is correct, it is determined that the resistive random access memory cell 100 is usable and no longer writes; when the verification is an error, the write is performed via the write combination SET4, and at the time of reading 540 performs write verification. When the verification is correct, it is determined that the resistive random access memory cell 100 is usable and no longer writes; when the verification is an error, it is determined that the resistive random access memory cell 100 is usable.

In an embodiment of the invention, the write voltage levels LW51~LW54 can be set to be identical, but in other embodiments, the write voltage levels LW51~LW54 can be set to be completely different, such as the write voltage level LW51. ~LW54 can be set to increase in order.

In an embodiment of the present invention, the sustain voltage levels LM51 LM LM54 may be set to be identical, that is, the write signal WRc is identical in electrical energy transmitted during the periods P52, P54, P56, and P58, but in other embodiments, Maintain voltage level LM51~LM54 can be set to be completely different, that is, the write signal WRc is completely different in the energy transmitted during the periods P52, P54, P56 and P58. For example, the voltage levels LM51~LM54 can be set to be sequentially increased, and the write signal WRc is During the period, the power transmitted by P52, P54, P56 and P58 is sequentially increased.

In an embodiment of the present invention, the lengths of the periods P51, P53, P55, and P57 may be set to be identical, but in other embodiments, the lengths of the periods P51, P53, P55, and P57 may be set to be completely different, for example, During the period, the lengths of P51, P53, P55 and P57 are sequentially increased.

In an embodiment of the present invention, the lengths of the periods P52, P54, P56, and P58 may be set to be identical, but in other embodiments, the lengths of the periods P52, P54, P56, and P58 may be set to be completely different, for example, The length of time of P52, P54, P56 and P58 increases sequentially.

In this embodiment, the waveforms of the respective write combinations SET1 SET SET4 are similar to the drive waveforms shown in the embodiment of FIG. 3 (ie, the waveforms indicated by the write signal WRb), but in other embodiments, the write combinations SET1 SET SET4 The waveform of the waveform shown in the embodiment of FIG. 2 (ie, the waveform shown by the write signal WRa) can be used, but the embodiment of the present invention is not limited thereto.

Fig. 6 is a view showing a driving waveform of a write signal in accordance with a fourth embodiment of the present invention. Please refer to FIG. 1, FIG. 2 and FIG. 6, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the waveforms of the write signal WRd in the periods P62 and P63 are similar to the waveforms of the write signal WRa in the periods P21 and P22, respectively, wherein the write voltage level LW3 may be the same or different from the write voltage level LW1, but Embodiment of the present invention Not limited to this. Further, the waveform of the write signal WRd during the period P61 to P63 can be regarded as a write combination (for example, SET1 to SET4).

In the present embodiment, the write signal WRd further includes a period P61 (corresponding to the fifth period), and in the period P61, the write voltage WRd is raised from the ground voltage (that is, the voltage level 0) to the write voltage. The level LW3 is transmitted to transfer electrical energy (corresponding to the fifth electrical energy) to the variable impedance element VRE. The power transmitted by the write signal WRd during the period P61 (half the product of the time length of the write voltage level LW3 and the period P61) is smaller than the power transmitted by the write signal WRd during the period P62 (corresponding to the write The product of the voltage level LW3 and the length of time of the period P62).

Fig. 7 is a view showing a driving waveform of a write signal in accordance with a fifth embodiment of the present invention. Please refer to FIG. 1, FIG. 3 and FIG. 7, wherein the same or similar elements are given the same or similar reference numerals. In the present embodiment, the waveforms of the write signals WRe in the periods P72 and P73 are similar to the waveforms of the write signals WRb in the periods P31 and P32, respectively, wherein the write voltage level LW4 may be the same or different from the write voltage level LW2, maintaining The voltage level LW3 may be the same or different from the sustain voltage level LM1, but the embodiment of the present invention is not limited thereto. Further, the waveform of the write signal WRe during the periods P71 to P73 can be regarded as a write combination (for example, SET1 to SET4).

In the present embodiment, the write signal WRe further includes a period P71 (corresponding to the fifth period), and in the period P71, the set write signal WRe is set to the sustain voltage level LM2 to transmit the power (corresponding to the fifth power) to Variable impedance element VRE. The power transmitted by the write signal WRe during the period P71 (corresponding to the product of the length of the sustain voltage level LM2 and the period P71) is smaller than the write signal WRe. The electric energy transmitted during the period P72 (corresponding to the product of the writing voltage level LW4 and the length of the period P72).

In the present embodiment, the sustain voltage level LM2 is equal to half (i.e., 1/2 times) the write voltage level LW4, and the period P71 is not adjacent to the period P72, and the length of time of the period P71 is equal to the length of the period P72. However, in other embodiments, the sustain voltage level LM2 may be equal to 1/3~2/3 times of the write voltage level LW4, and the period P71 may be adjacent to the period P72, and the length of the period P71 may be equal to the period The time length of the P72 is 0.5 to 3 times, but the embodiment of the present invention is not limited thereto. In addition, the interval between the period P71 and the P72 may be set to be less than the length of the period P72. However, the embodiment of the present invention is not limited thereto.

In summary, in the method for operating a resistive random access memory cell according to an embodiment of the present invention, after a period of writing a voltage, the write signal still transmits energy to the variable impedance element to extend oxygen in the variable impedance element. The movement time of the ions increases the formation of the filamentary conductive path and slows down the effect of the high temperature generated by the thermochemical effect on the filamentous conductive path.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

LW1‧‧‧ write voltage level

During the period of P21~P22‧‧

WRa‧‧‧ write signal

Claims (14)

A method for operating a resistive random access memory cell, wherein the resistive random access memory cell includes a variable impedance component and a switching component connected in series, including: when the switching component is turned on, providing a write signal to The variable impedance element is configured to set an impedance value of the variable impedance element; in a first period, setting the write signal to a first write voltage level to transmit a first electrical energy to the variable impedance element; Transmitting, by the write signal, a second electrical energy to the variable impedance component, wherein the second period is after the first period, the first electrical energy and the second electrical energy are greater than zero, the second The electrical energy is less than the first electrical energy, and the length of time of the second period is equal to 0.5 to 3 times the length of the first period. The method for operating a resistive random access memory cell according to claim 1, further comprising: setting the write signal from the first write voltage level to a ground voltage during the second period. The method for operating a resistive random access memory cell according to claim 1, further comprising: setting the write signal to a first sustain voltage level during the second period. The method for operating a resistive random access memory cell according to claim 3, wherein the first sustain voltage level is equal to 1/3 to 2/3 times of the first write voltage level. The operation of the resistive random access memory cell as described in claim 1 The method further includes: sequentially setting the write signal to a plurality of second write voltage levels to sequentially transmit a plurality of third powers to the variable impedance component, and the third The period is after the second period; and in the plurality of fourth periods, the plurality of fourth powers are sequentially transmitted to the variable impedance element through the write signal, wherein the fourth periods are respectively located in the third period Afterwards, the third electrical energy and the fourth electrical energy are greater than zero, and each of the fourth electrical energy is less than the third electrical energy transmitted by the write signal in the corresponding third period. The method for operating a resistive random access memory cell according to claim 5, wherein the first write voltage level and the second write voltage levels are identical to each other. The method for operating a resistive random access memory cell according to claim 5, wherein the first write voltage level and the second write voltage levels are different from each other. The method for operating a resistive random access memory cell according to claim 7, wherein the first write voltage level and the second write voltage levels are sequentially increased. The method of operating a resistive random access memory cell according to claim 5, wherein the second electrical energy and the fourth electrical energy are identical to each other. The method for operating a resistive random access memory cell according to claim 5, wherein the second electrical energy and the fourth electrical energy are different from each other. Resistive random access memory cell as described in claim 10 The operating method, wherein the second electrical energy and the fourth electrical energy are sequentially increased. The method for operating a resistive random access memory cell according to claim 5, wherein the first period and the third periods have the same length of time. The method for operating a resistive random access memory cell according to claim 5, wherein the time lengths of the first period and the third periods are different from each other. The method for operating a resistive random access memory cell according to claim 13, wherein the length of time of the first period and the third periods is sequentially increased.