TW201543485A - Forming and testing method of resistive memory - Google Patents

Abstract

A resistive memory is provided. A memory array includes a plurality of resistive memory cells. A processing module provides a first forming voltage and a second forming voltage to the resistive memory cell in sequence, so as to switch the resistive memory cell from an isolation state to an impedance state. The processing module provides a reset voltage to the resistive memory cell, so as to switch the impedance state of the resistive memory cell to first impedance. The processing module provides a set voltage to the resistive memory cell, so as to switch the impedance state of the resistive memory cell from the first impedance to second impedance. The set voltage is larger than the second forming voltage, and the second forming voltage is larger than the first forming voltage.

Description

Resistive memory formation and test method

The present invention relates to a resistive memory, and more particularly to a resistive memory capable of improving data maintenance performance.

At present, non-volatile memory is dominated by flash memory (Flash), but as components continue to shrink, flash memory faces a thin gate oxide oxide layer, resulting in shortened memory time and excessive operating voltage. And so on. Therefore, various types of non-volatile memory are actively being developed to replace flash memory, in which Resistive Random Access Memory (RRAM) is achieved by changing the resistance value. The effect, and the use of its non-volatile characteristics as a memory component, has the advantages of small operating voltage, long memory time, multi-state memory, simple structure and small area.

After the fabrication of the resistive memory, a forming process is performed to switch the resistive memory from an insulated state to an impedance state. Then, by setting or resetting the resistive memory, the resistance value of the resistive memory can be changed to store the data in the resistive memory. Therefore, the impedance information of the resistive memory can be obtained by measuring the current flowing through the resistive memory (for example, the set current Iset and the reset current Ireset), thereby obtaining the stored data. However, after the baking test, the resistive memory is likely to cause the set current Iset to drop, making it impossible to clearly distinguish the settings. Current Iset and reset current Ireset. As a result, the retention performance of the resistive memory is degraded.

Therefore, there is a need for a resistive memory that can improve data retention performance.

The invention provides a forming method suitable for a resistive memory having a complex resistive memory cell. A first forming voltage and a second forming voltage are sequentially supplied to the resistive memory cell to switch the resistive memory cell from an insulating state to an impedance state. And providing a reset voltage to the resistive memory cell to convert the impedance state of the resistive memory cell to a first impedance. And providing a set voltage to the resistive memory cell to convert the impedance state of the resistive memory cell from the first impedance to a second impedance. The set voltage is greater than the second forming voltage, and the second forming voltage is greater than the first forming voltage.

Furthermore, the present invention provides a test method suitable for a resistive memory having a complex resistive memory cell. A first forming voltage and a second forming voltage are sequentially supplied to the resistive memory cell to switch the resistive memory cell from an insulating state to an impedance state. And providing a reset voltage to the resistive memory cell to convert the impedance state of the resistive memory cell to a first impedance. And providing a set voltage to the resistive memory cell to convert the impedance state of the resistive memory cell from the first impedance to a second impedance. A verification procedure is performed on the resistive memory cell described above. After the above verification procedure is completed, the above-described resistive memory is baked. The set voltage is greater than the second forming voltage, and the second forming voltage is greater than the first Form a voltage.

100‧‧‧ memory cells

110‧‧‧Metal-insulator-metal components

120‧‧‧Optoelectronics

200‧‧‧Test System

210‧‧‧Resistive memory

220‧‧‧Testing machine

BL‧‧‧ bit line

I‧‧‧current

S310-S340, S502-S518‧‧‧ steps

VC‧‧‧ endpoint

VF1, VF2‧‧‧ forming voltage

Vreset‧‧‧Reset voltage

Vset‧‧‧Set voltage

WL‧‧‧ character line

1 is a schematic view showing a memory cell of a resistive memory according to an embodiment of the present invention; FIG. 2 is a schematic view showing a test system according to an embodiment of the present invention; and FIG. 3 is a view showing a test system according to an embodiment of the present invention; The forming method according to an embodiment of the invention is applicable to a memory device having a plurality of resistive memory cells; and FIG. 4A is a view showing application of forming voltages VF1, VF2 or a set voltage Vset according to an embodiment of the invention. Schematic diagram of a resistive memory cell; FIG. 4B is a diagram showing voltage versus time on the terminal T1 in FIG. 4A; FIG. 4C is a diagram showing the application of a reset voltage Vreset to a resistive memory according to an embodiment of the invention. FIG. 5 is a schematic diagram showing a test method according to an embodiment of the present invention, which is applicable to a memory device having a plurality of resistive memory cells; and FIG. 6 is a schematic diagram showing data storage test results. Explain the differences between the traditional test methods and the test methods in Figure 5.

The above and other objects, features and advantages of the present invention will become more <RTIgt; A schematic diagram of a memory cell 100 of a resistive memory as described in the embodiments. Memory cell 100 includes metal-insulator-gold A metal-insulator-metal (MIM) 110 and a transistor 120. The MIM device 110 is coupled between the bit line BL and the transistor 120, and the transistor 120 is coupled between the MIM device 110 and the source line SL, wherein the gate of the transistor 120 is coupled to the word element. Line WL. In FIG. 1, the resistance value of the MIM element 110 can be changed by applying a bias voltage to the MIM element 110. For example, the resistance value of the MIM element 110 can be changed through the bit line BL or the source line SL. In addition, when the memory cell 100 is read, a read voltage can be supplied to the MIM component 110 through the bit line BL, and the logical bit of the data stored in the memory cell 100 can be determined according to the change in the current value of the MIM component 110. Why?

2 is a schematic diagram showing a test system 200 in accordance with an embodiment of the present invention. Test system 200 includes a resistive memory 210 and a test machine 220. Resistive memory 210 includes an array of memory formed by a plurality of memory cells (e.g., memory cell 100 of FIG. 1). The test machine 220 provides different voltages to the memory cells within the resistive memory 210. For example, the test machine 220 provides the formation voltage VF1 and the formation voltage VF2 to the memory cells in the resistive memory 210 to enable the memory cells to switch from the initial state (ie, the insulated state) to the impedance state. In other words, the test machine 220 can perform a special electrical stimulation procedure on the memory cells, also known as a forming process. In addition, the test machine 220 provides a set voltage Vset and a reset voltage Vreset to the memory cell to change the impedance of the memory cell. Moreover, the test machine 220 can determine the data stored by the memory cell according to the current I of the memory cell.

Fig. 3 is a view showing a forming method according to an embodiment of the present invention, which is suitable for a memory device having a plurality of resistive memory cells. Referring to FIG. 2 and FIG. 3 simultaneously, first, in step S310, the test machine 220 will provide formation. The voltage VF1 is to the memory cell in the resistive memory 210. Next, in step S320, the test machine 220 supplies the forming voltage VF2 to the memory cells in the resistive memory 210, wherein the forming voltage VF2 is greater than the forming voltage VF1, that is, VF2>VF1. After the steps S310 and S320, the memory cells in the resistive memory 210 are switched from the insulated state to the impedance state. Next, in step S330, the test machine 220 provides a reset voltage Vreset to the memory cells in the resistive memory 210 for initial resetting, so that the impedance state of the memory cell is converted to the first impedance. Next, in step S340, the test machine 220 supplies the set voltage Vset to the memory cell in the resistive memory 210 to convert the impedance state of the memory cell from the first impedance to the second impedance, wherein the set voltage Vset is greater than the formation. Voltage VF2, ie Vset>VF2. In this embodiment, the first impedance is high impedance and the second impedance is low impedance.

4A is a schematic view showing application of forming voltages VF1, VF2 or set voltage Vset to a resistive memory cell according to an embodiment of the invention. In FIG. 4, the memory cell includes a MIM element 400, wherein the MIM element 400 includes an electrode 410, a variable resistance layer 420, and an electrode 430. The materials of the electrodes 410 and 430 are, for example, metal or tantalum. The variable resistance layer 420 is disposed between the electrode 410 and the electrode 430, wherein the variable resistance layer 420 changes its resistivity under different bias conditions. In FIG. 4A, the electrode 410 is coupled to the terminal T1, and the electrode 430 is coupled to the terminal T2. In one embodiment, the terminal T1 is coupled to the bit line BL (eg, the bit line BL of FIG. 1), and the end point T2 is via the turned-on transistor (eg, the transistor 120 of FIG. 1). It is coupled to the source line SL (for example, the source line SL of FIG. 1). In FIG. 4A, the formation voltage VF1, the formation voltage VF2, and the set voltage Vset are applied to the same electrode 410 via the terminal T1. In addition, when forming voltage When the VF1, the formation voltage VF2, or the set voltage Vset is applied to the electrode 410, the source line SL is grounded, and the terminal T2 is coupled to the ground GND via the transistor, that is, 0V.

Fig. 4B is a graph showing the relationship between voltage and time at the terminal T1 in Fig. 4A. During the time period P1, the formation voltage VF1 is applied to the terminal T1. Next, during the time period P2, the formation voltage VF2 is applied to the terminal T1, wherein the voltage level at which the voltage VF2 is formed is greater than the voltage level at which the voltage VF1 is formed. Next, during the time period P3, the set voltage Vset is applied to the terminal T1, wherein the voltage level of the set voltage Vset is greater than the voltage level at which the voltage VF2 is formed. In this embodiment, the time period P2 is greater than the time period P3, and the time period P3 is greater than the time period P1. It should be noted that the time length and relative relationship of the time periods P1, P2 and P3 in FIG. 4B are only examples and are not intended to limit the present invention. In other embodiments, the length of time and relative relationship of time periods P1, P2, and P3 are determined by the actual application.

FIG. 4C is a schematic diagram showing application of a reset voltage Vreset to a resistive memory cell according to an embodiment of the invention. The electrode 410 of the MIM component 400 is coupled to the terminal T1, and the electrode 430 of the MIM component 400 is coupled to the terminal T2. As previously described, in one embodiment, the terminal T1 is coupled to the bit line BL (eg, the bit line BL of FIG. 1), and the end point T2 is via the turned-on transistor (eg, FIG. 1) The transistor 120) is coupled to the source line SL (for example, the source line SL of FIG. 1). In FIG. 4C, when the reset voltage Vreset is applied to the electrode 430 via the terminal T2, the bit line BL is grounded, and the terminal T1 is coupled to the ground GND via the transistor, that is, 0V. It is to be noted that, for the MIM element 400, the formation voltage VF1, the formation voltage VF2, and the set voltage Vset are applied in the same The electrode, while the reset voltage Vreset is applied to the other electrode.

Figure 5 is a diagram showing a test method according to an embodiment of the present invention, which is suitable for a memory device having a plurality of resistive memory cells. Referring to FIGS. 2 and 5 simultaneously, first, in step S502, the test machine provides a voltage VF1 to the memory cells in the resistive memory 210. Next, in step S504, the testing machine provides a forming voltage VF2 to the memory cell in the resistive memory 210, wherein the forming voltage VF2 is greater than the forming voltage VF1, that is, VF2>VF1. After the steps S502 and S504, the memory cells in the resistive memory 210 are switched from the insulated state to the impedance state. Next, in step S506, the test machine provides a reset voltage Vreset to the memory cells in the resistive memory 210 for initial resetting, so that the impedance state of the memory cell is converted to the first impedance. Next, in step S508, the test machine provides a set voltage Vset to the memory cell in the resistive memory 210 to convert the impedance state of the memory cell from the first impedance to the second impedance, wherein the set voltage Vset is greater than the forming voltage. VF2, that is, Vset>VF2. In this embodiment, the first impedance is high impedance and the second impedance is low impedance. As described previously, step S502 - step S508 can be regarded as a memory cell forming procedure. In addition, in an embodiment, the test machine repeatedly provides the reset voltage Vreset (step S506) and the set voltage Vset (step S508) to the memory cells in the resistive memory 210 to increase the performance of the memory cell. Next, in step S510, the test machine performs a verification process on the memory cells in the resistive memory 210 to confirm whether the memory cells are normal. In the verification procedure, the test machine 220 provides a reset voltage Vreset to the memory cells in the resistive memory 210 to convert the impedance state of the memory cells from the second impedance to the first impedance. Next, the test machine 220 will confirm whether the impedance state of the memory cell has been successfully converted to the first impedance. Next, the test machine 220 A set voltage Vset is supplied to the memory cell in the resistive memory 210 to convert the impedance state of the memory cell from the first impedance to the second impedance. Next, the test machine 220 will confirm whether the impedance state of the memory cell has been successfully converted to the second impedance. By analogy, the test machine performs multiple verification procedures on the memory cell, and the number of times the verification process is executed can be determined according to the actual application. After the verification process is completed, the test machine provides a set voltage Vset to the memory cell to obtain a set current Iset1 flowing through the resistive memory intracellular MIM element (step S512). Next, in step S514, the test machine will bake the resistive memory. For example, the baking is continued for a specific period of time (e.g., 24 hours) at a specific elevated temperature (e.g., a temperature of approximately 200 ° C). Next, in step S516, the test machine provides a set voltage Vset to the baked memory cell to obtain a set current Iset2 flowing through the resistive memory intracellular MIM component. Next, in step S518, the test machine can obtain the test result of the data retention according to the set current Iset1 before baking and the set current Iset2 after baking.

Figure 6 is a schematic diagram showing the results of data storage test to illustrate the differences between the traditional test method and the test method of Figure 5. In the conventional test method, only a single forming voltage is used to switch the resistive memory cell from an insulated state to an impedance state. Furthermore, in the conventional test method, the formation voltage and the set voltage have the same voltage level. In Fig. 6, the horizontal axis represents the percentage of attenuation of the set current of the memory cell after baking, and the vertical axis represents the Cumulative Distribution Function (CDF) of the set current. Further, the curve 610 represents the data storage test result of the conventional test method, and the curve 620 represents the data storage test result of the test method of FIG. Obviously, curve 620 falls within 50%. Therefore, by using two stages of forming voltage (ie VF1 By changing the impedance of the MIM element with VF2) and using a set voltage (Vset) greater than the forming voltage, the amount of attenuation of the set current is reduced after the memory cell is baked. Therefore, the effect of data preservation is better. In addition, by repeatedly providing the reset voltage Vreset and the set voltage Vset (ie, steps S506 and S508) to the memory cells in the resistive memory 210 after the voltage is formed, the performance of the memory can be increased, and the yield of the memory can be improved.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S310-S340‧‧‧Steps

Claims (10)

A forming method is applicable to a resistive memory having a plurality of resistive memory cells, comprising: sequentially providing a first forming voltage and a second forming voltage to the resistive memory cell, so as to An insulating state is switched to an impedance state; a reset voltage is supplied to the resistive memory cell to convert the impedance state of the resistive memory cell into a first impedance; and a set voltage is supplied to the resistive memory cell, In order to convert the impedance state of the resistive memory cell from the first impedance to a second impedance; wherein the set voltage is greater than the second forming voltage, and the second forming voltage is greater than the first forming voltage. The method of forming the method of claim 1, wherein the resistive memory cell comprises a first electrode, a second electrode, and a variable resistance layer disposed between the first and second electrodes. The method of forming the second aspect of the invention, wherein the first forming voltage, the second forming voltage or the set voltage is supplied to the first electrode of the resistive memory cell, and the reset voltage is provided To the second electrode of the resistive memory cell. A test method is applicable to a resistive memory having a plurality of resistive memory cells, comprising: sequentially providing a first forming voltage and a second forming voltage to the resistive memory cell, so as to Switching an insulation state into An impedance state; providing a reset voltage to the resistive memory cell to convert the impedance state of the resistive memory cell into a first impedance; providing a set voltage to the resistive memory cell to apply the resistive The impedance state of the memory cell is converted from the first impedance to a second impedance; performing a verification procedure on the resistive memory cell; and baking the resistive memory after completing the verification process; wherein the set voltage system The second forming voltage is greater than the second forming voltage, and the second forming voltage is greater than the first forming voltage. The test method of claim 4, wherein the resistive memory cell comprises a first electrode, a second electrode, and a variable resistance layer disposed between the first and second electrodes. The test method of claim 5, wherein the first forming voltage, the second forming voltage, or the set voltage is supplied to the first electrode of the resistive memory cell, and the reset voltage system The second electrode is provided to the resistive memory cell. The test method of claim 5, wherein the step of performing the verification procedure on the resistive memory cell further comprises: providing the reset voltage to the second electrode of the resistive memory cell, and verifying the resistor Whether the impedance state of the memory cell is converted from the second impedance to the first impedance; and providing the set voltage to the first electrode of the resistive memory cell, and verifying whether the impedance state of the resistive memory cell is Above first The impedance is converted to the second impedance described above. The test method of claim 5, wherein after the verification process is completed, the step of baking the resistive memory further comprises: after completing the verification process, providing the set voltage to the resistive memory cell The first electrode is configured to obtain a first current flowing through one of the resistive memory cells; and after obtaining the first current, baking the resistive memory. The test method of claim 8, further comprising: providing the set voltage to the baked resistive memory cell to obtain a second current flowing through the resistive memory; and according to the above A current and the second current are obtained to obtain a data storage test result. The test method of claim 5, wherein after the step of providing a set voltage to the resistive memory cell, the method further comprises: repeatedly providing the reset voltage to the resistive memory cell and providing the set voltage The step to the above resistive memory cell.