CN105097021B - The formation of resistance-type memory and method of testing - Google Patents
The formation of resistance-type memory and method of testing Download PDFInfo
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- CN105097021B CN105097021B CN201410217577.8A CN201410217577A CN105097021B CN 105097021 B CN105097021 B CN 105097021B CN 201410217577 A CN201410217577 A CN 201410217577A CN 105097021 B CN105097021 B CN 105097021B
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Abstract
A kind of formation of resistance-type memory and method of testing.One memory array includes multiple resistive memory cells.One processing module is to be sequentially provided one first formation voltage and one second formation voltage to above-mentioned resistive memory cell, so as to which above-mentioned resistive memory cell is switched into an impedance state by a state of insulation.Above-mentioned processing module provides a reset voltage to above-mentioned resistive memory cell, so as to which the above-mentioned impedance state of above-mentioned resistive memory cell is changed into one first impedance.Above-mentioned processing module provides a setting voltage to above-mentioned resistive memory cell, by above-mentioned first impedance transition to be one second impedance by the above-mentioned impedance state of above-mentioned resistive memory cell.Above-mentioned setting voltage is more than above-mentioned second and forms voltage, and above-mentioned second forms voltage more than the above-mentioned first formation voltage.
Description
Technical field
The present invention stores on a kind of resistance-type memory in particular to the resistance-type that can improve data dimension holding effect energy
The formation of device and method of testing.
Background technology
At present, nonvolatile memory be with flash memory (Flash) for main flow, but with the continuous micro of element,
The shortcomings of flash memory faces grid and penetrates that oxide layer is excessively thin to cause storage time to shorten, and operating voltage is excessive.Cause
This, the nonvolatile memories of various different shapes is just positive to be developed to substitute flash memory, wherein resistance-type with
Machine access memory (Resistive Random Access Memory, RRAM) reaches storage effect by the change of resistance value
Should, and by the use of its non-volatile characteristic as memory component, with operating voltage is small, storage time is long, multimode stores, knot
Structure is simple and the advantages that area is small.
Resistance-type memory after fabrication is complete, can first pass through to form processing (forming process), so that resistance
Formula memory switches to impedance state from state of insulation.Then, can be with by being set or being reset to resistance-type memory
Change the impedance value of resistance-type memory, to store data in resistance-type memory.Therefore, resistance is flowed through by measurement
The electric current (such as setting electric current Iset, reset current Ireset) of formula memory can obtain the impedance information of resistance-type memory,
And then obtain stored data.However, resistance-type memory after being tested through overbaking, easily causes setting electric current Iset
It can decline so that can not clearly distinguish setting electric current Iset and reset current Ireset.Then, the number of resistance-type memory
It can decline according to (retention) performance is maintained.
Therefore, it is necessary to a kind of resistance-type memory that can be improved data and maintain performance.
The content of the invention
It is an object of the invention to provide a kind of formation of resistance-type memory and method of testing, is deposited with that can improve resistance-type
The data of reservoir maintain performance.
The technical scheme is that a kind of forming method is provided, suitable for the electricity with multiple resistive memory cells
Resistive memory.It is sequentially provided one first formation voltage and one second forms voltage to resistive memory cell, so as to by electricity
Resistive memory cell switches to an impedance state by a state of insulation.A reset voltage is provided to resistive memory cell, so as to
The impedance state of resistive memory cell is changed into one first impedance.A setting voltage is provided to resistive memory cell, with
Just it is one second impedance by the first impedance transition by the impedance state of resistive memory cell.Set voltage and be more than the second formation electricity
Pressure, and the second formation voltage are more than first and form voltage.
Present invention also offers a kind of method of testing, is stored suitable for the resistance-type with multiple resistive memory cells
Device.One first formation voltage and one second formation voltage are sequentially provided to resistive memory cell, so as to which resistance-type is stored
Unit switches to an impedance state by a state of insulation.A reset voltage is provided to resistive memory cell, so as to by resistance-type
The impedance state of memory cell is changed into one first impedance.A setting voltage is provided to resistive memory cell, so as to by resistance
The impedance state of formula memory cell is one second impedance by the first impedance transition.A checking journey is performed to resistive memory cell
Sequence.After proving program is completed, resistance-type memory is toasted.Set voltage and be more than the second formation voltage, and second forms
Voltage is more than first and forms voltage.
Formation and method of testing by resistance-type memory provided by the invention, resistance-type memory is through overbaking
After test, the attenuation of setting electric current can diminish, and the effect that data preserve is preferable.In addition, by being repeated after voltage is formed
Memory cell in reset voltage and setting voltage to resistance-type memory is provided, the performance of memory can be increased, and lifted
The yield of memory.
Brief description of the drawings
Fig. 1 shows the schematic diagram of the memory cell of the resistance-type memory according to one embodiment of the invention；
Fig. 2 shows the schematic diagram of the test system according to one embodiment of the invention；
Fig. 3 shows the forming method according to one embodiment of the invention, suitable for multiple resistive memory cells
A storage arrangement；
Fig. 4 A show that the application according to one embodiment of the invention forms voltage VF1, VF2 or setting voltage Vset extremely
The schematic diagram of resistive memory cell；
Fig. 4 B show in Fig. 4 A voltage and the graph of a relation of time on end points T1；
Fig. 4 C show application reset voltage Vreset according to one embodiment of the invention to resistive memory cell
Schematic diagram；
Fig. 5 shows the method for testing according to one embodiment of the invention, suitable for multiple resistive memory cells
A storage arrangement；And
Fig. 6 display datas preserve the schematic diagram of test result, to illustrate the method for testing of conventional test methodologies and Fig. 5
Difference.
Main element symbol description
100~memory cell；
110~metal-insulator-metal type element；
120~transistor；
200~test system；
210~resistance-type memory；
220~test equipment；
BL~bit line；
I~electric current；
S310-S340, S502-S518~step；
VC~end points；
VF1, VF2~formation voltage；
Vreset~reset voltage；
Vset~setting voltage；And
WL~word-line.
Embodiment
For allow the present invention above and other purpose, feature and advantage can become apparent, it is cited below particularly go out preferable implementation
Example, and coordinate institute's accompanying drawings, it is described in detail below：
Fig. 1 shows the schematic diagram of the memory cell 100 of the resistance-type memory according to one embodiment of the invention.Storage
Unit 100 include metal-insulator-metal type element (metal-insulator-metal, hereinafter referred to as MIM elements) 110 and
Transistor 120.MIM elements 110 are coupled between bit line BL and transistor 120, and transistor 120 is coupled to MIM elements 110
And between source electrode line SL, the grid of wherein transistor 120 is coupled to word-line WL.In Fig. 1, can be by MIM elements 110
Apply a bias to change the resistance value of MIM elements 110.For example, MIM elements can be changed by bit line BL or source electrode line SL
110 resistance value.In addition, when memory cell 100 is read out, bit line BL can be passed through provides one and read voltage to the MIM elements
110, and be to judge the logic level of data that memory cell 100 is stored according to the change of the current values of MIM elements 110
What.
Fig. 2 shows the schematic diagram of the test system 200 according to one embodiment of the invention.Test system 200 includes electricity
Resistive memory 210 and test equipment 220.Resistance-type memory 210 is included by (such as Fig. 1 storage of multiple memory cell
Unit 100) memory array that is formed.Test equipment 220 can provide depositing in different voltage to resistance-type memory 210
Storage unit.For example, test equipment 220 can provide to be formed in voltage VF1 and formation voltage VF2 to resistance-type memory 210
Memory cell so that memory cell can switch to impedance state from original state (i.e. state of insulation).In other words, test equipment
220 can perform special electro photoluminescence program, also known as formation processing (forming process) to memory cell.In addition, test
Equipment 220 can provide setting voltage Vset and reset voltage Vreset respectively to memory cell, to change the resistance of memory cell
It is anti-.Also, test equipment 220 can judge data that memory cell is stored according to the electric current I of memory cell.
Fig. 3 shows the forming method according to one embodiment of the invention, suitable for multiple resistive memory cells
A storage arrangement.With reference to Fig. 2 and Fig. 3, first, in step S310, test equipment 220 can provide to form voltage VF1
Memory cell to resistance-type memory 210.Then, can provide to form voltage VF2 extremely in step S320, test equipment 220
Memory cell in resistance-type memory 210, voltage VF1, i.e. VF2 are formed wherein forming voltage VF2 and being more than>VF1.By walking
After rapid S310 and S320, the memory cell in resistance-type memory 210 can switch to impedance state by state of insulation.Then,
In step S330, test equipment 220 can provide the memory cell in reset voltage Vreset to resistance-type memory 210, to enter
Row initialization is reset so that the impedance state of memory cell is changed into the first impedance.Then, in step S340, test equipment 220
Memory cell in setting voltage Vset to resistance-type memory 210 can be provided, so as to by the impedance state of memory cell by the
One impedance transition is the second impedance, wherein setting voltage Vset, which is more than, forms voltage VF2, i.e. Vset>VF2.In this embodiment,
First impedance is high impedance, and the second impedance is Low ESR.
Fig. 4 A show that the application according to one embodiment of the invention forms voltage VF1, VF2 or setting voltage Vset extremely
The schematic diagram of resistive memory cell.In Fig. 4, memory cell includes MIM elements 400, and wherein MIM elements 400 include electrode
410th, variable resistance layer 420 and electrode 430.The material of electrode 410 and 430 is, for example, metal or silicon respectively.Variable resistor
Layer 420 is arranged between electrode 410 and electrode 430, and wherein variable resistance layer 420 can change its electricity under different bias conditions
Resistance rate.In Figure 4 A, electrode 410 is coupled to end points T1, and electrode 430 is coupled to end points T2.In one embodiment, end points T1 couplings
Be connected to bit line BL (such as Fig. 1 bit line BL), and end points T2 via the transistor (such as Fig. 1 transistor 120) of conducting coupling
It is connected to source electrode line SL (such as Fig. 1 source electrode line SL).In Figure 4 A, voltage VF1 is formed, form voltage VF2 and sets voltage
Vset is applied to same electrode 410 via end points T1.Voltage VF1 is formed, form voltage VF2 or sets voltage in addition, working as
When Vset is applied to electrode 410, source electrode line SL can be grounded, and then end points T2 can be coupled to earth terminal GND via transistor,
That is 0V.
Fig. 4 B show in Fig. 4 A voltage and the graph of a relation of time on end points T1.The P1 during the time, forming voltage VF1 can apply
It is added on end points T1.Then, the P2 during the time, forming voltage VF2 can be applied on end points T1, wherein forming voltage VF2's
Voltage level is more than the voltage level for forming voltage VF1.Then, the P3 during the time, setting voltage Vset can be applied to end points
On T1, wherein setting voltage Vset voltage level is more than the voltage level for forming voltage VF2.In this embodiment, phase time
Between P2 be more than the time during P3, and during the time P3 be more than the time during P1.It is worth noting that, P1 during the time in Fig. 4 B,
P2 and P3 time span is only an example with relativeness, is not limited to the present invention.In other embodiments, phase time
Between P1, P2 and P3 time span and relativeness be to be determined by practical application.
Fig. 4 C show application reset voltage Vreset according to one embodiment of the invention to resistive memory cell
Schematic diagram.The electrode 410 of MIM elements 400 is coupled to end points T1, and the electrode 430 of MIM elements 400 is coupled to end points T2.Such as elder generation
Preceding described, in one embodiment, end points T1 is coupled to bit line BL (such as Fig. 1 bit line BL), and end points T2 is via conducting
Transistor (such as Fig. 1 transistor 120) and be coupled to source electrode line SL (such as Fig. 1 source electrode line SL).In figure 4 c, replacement is worked as
When voltage Vreset is applied to electrode 430 via end points T2, bit line BL can be grounded, then end points T1 can via transistor and
It is coupled to earth terminal GND, i.e. 0V.It is worth noting that, for MIM elements 400, formed voltage VF1, formed voltage VF2 with
And setting voltage Vset is consequently exerted at same electrode, and reset voltage Vreset is consequently exerted at another electrode.
Fig. 5 shows the method for testing according to one embodiment of the invention, suitable for multiple resistive memory cells
A storage arrangement.With reference to Fig. 2 and Fig. 5, first, in step S502, test equipment can provide to form voltage VF1 to electricity
Memory cell in resistive memory 210.Then, in step S504, test equipment, which can provide, to be formed voltage VF2 and deposits to resistance-type
Memory cell in reservoir 210, voltage VF1, i.e. VF2 are formed wherein forming voltage VF2 and being more than>VF1.By step S502 with
After S504, the memory cell in resistance-type memory 210 can switch to impedance state by state of insulation.Then, in step
S506, test equipment can provide the memory cell in reset voltage Vreset to resistance-type memory 210, to carry out initialization weight
Put so that the impedance state of memory cell is changed into the first impedance.Then, in step S508, test equipment can provide setting electricity
The memory cell in Vset to resistance-type memory 210 is pressed, to be by the first impedance transition by the impedance state of memory cell
Second impedance, wherein setting voltage Vset, which is more than, forms voltage VF2, i.e. Vset>VF2.In this embodiment, the first impedance is height
Impedance, and the second impedance is Low ESR.As described previously, step S502- steps S508 can be considered the formation journey of memory cell
Sequence.In addition, in one embodiment, test equipment can repeat to provide reset voltage Vreset (step S506) and setting voltage
Memory cell in Vset (step S508) to resistance-type memory 210, to increase the performance of memory cell.Then, in step
S510, just whether test equipment can perform proving program to the memory cell in resistance-type memory 210, to confirm memory cell
Often.In proving program, test equipment 220 can provide the memory cell in reset voltage Vreset to resistance-type memory 210,
By the second impedance transition to be the first impedance by the impedance state of memory cell.Then, test equipment 220 can confirm that storage is single
Whether the impedance state of member has been successfully transitioned to the first impedance.Then, test equipment 220 can provide setting voltage Vset to electricity
Memory cell in resistive memory 210, by the first impedance transition to be the second impedance by the impedance state of memory cell.Connect
, test equipment 220 can confirm whether the impedance state of memory cell has been successfully transitioned to the second impedance.By that analogy, survey
Multiple authentication program can be performed to memory cell by trying equipment, wherein performing the number of proving program can determine according to practical application
It is fixed.After proving program is completed, test equipment can provide setting voltage Vset to memory cell, be deposited with obtaining flowing through resistance-type
The setting electric current Iset1 (step S512) of MIM elements in storage unit.Then, resistance-type can be deposited in step S514, test equipment
Reservoir is toasted (baking).For example, with a specific high temperature (such as close to 200 DEG C of high temperature) one special time of continuous baking
(such as 24 hours).Then, in step S516, test equipment can provide setting voltage Vset to the memory cell toasted, with
Obtain flowing through the setting electric current Iset2 of MIM elements in resistive memory cell.Then, can basis in step S518, test equipment
Setting electric current Iset1 before the baking and setting electric current Iset2 after baking obtains the test that data preserve (retention)
As a result.
Fig. 6 display datas preserve the schematic diagram of test result, to illustrate the method for testing of conventional test methodologies and Fig. 5
Difference.In conventional test methodologies, resistive memory cell is set to be switched to by state of insulation using only voltage is unitarily formed
Impedance state.In addition, in conventional test methodologies, forming voltage and setting voltage has identical voltage level.In Fig. 6
In, transverse axis represents the attenuation percentage of the setting electric current of memory cell after baking, and the longitudinal axis represents the accumulative of setting electric current
Distribution function (Cumulative Distribution Function, CDF).In addition, curve 610 represents conventional test methodologies
Data preserve test result, and curve 620 represents that the data of Fig. 5 method of testing preserve test result.It is apparent that curve 620
All fall within 50%.Therefore, electricity is formed by using the formation voltage (i.e. VF1 and VF2) in two stages and using being more than
The setting voltage (Vset) of pressure changes the impedance of MIM elements, and can to make memory cell setting electric current declines after overbaking
Decrement diminishes.Then, the effect that data preserve is preferable.In addition, by repeating to provide reset voltage Vreset after voltage is formed
And setting voltage Vset (i.e. step S506 and S508) can increase memory to the memory cell in resistance-type memory 210
Performance, and lift the yield of memory.
Although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention, any affiliated technology
Field includes usual skill, without departing from the spirit and scope of the present invention, when that can make a little change and retouching, therefore
The scope of protection of the present invention is defined by those of the claims.
Claims (10)
- A kind of 1. forming method, suitable for the resistance-type memory with multiple resistive memory cells, it is characterised in that institute Stating forming method includes：One first is sequentially provided during a very first time to form voltage and one second formation is provided during one second time Voltage is to the resistive memory cell, so as to which the resistive memory cell is switched into an impedance shape by a state of insulation State；A reset voltage is provided to the resistive memory cell, so as to by the impedance state of the resistive memory cell It is changed into one first impedance；AndA setting voltage is provided during one the 3rd time to the resistive memory cell, it is single so as to which the resistance-type is stored The impedance state of member is one second impedance by first impedance transition；Wherein described setting voltage is more than described second and forms voltage, and the second formation voltage is more than described first and formed Voltage,It is greater than during being greater than above-mentioned 3rd time during wherein above-mentioned second time, and during above-mentioned 3rd time above-mentioned During the very first time.
- 2. forming method as claimed in claim 1, it is characterised in that the resistive memory cell include a first electrode, One second electrode and the variable resistance layer being arranged between the first electrode and the second electrode.
- 3. forming method as claimed in claim 2, it is characterised in that described first forms voltage, the second formation voltage Or the setting voltage is provided to the first electrode of the resistive memory cell, and the reset voltage and provided to institute State the second electrode of resistive memory cell.
- A kind of 4. method of testing, suitable for the resistance-type memory with multiple resistive memory cells, it is characterised in that institute Stating method of testing includes：One first is sequentially provided during a very first time to form voltage and one second formation is provided during one second time Voltage is to the resistive memory cell, so as to which the resistive memory cell is switched into an impedance shape by a state of insulation State；A reset voltage is provided to the resistive memory cell, so as to by the impedance state of the resistive memory cell It is changed into one first impedance；A setting voltage is provided during one the 3rd time to the resistive memory cell, it is single so as to which the resistance-type is stored The impedance state of member is one second impedance by first impedance transition；One proving program is performed to the resistive memory cell；AndAfter the proving program is completed, the resistance-type memory is toasted；Wherein described setting voltage is more than described second and forms voltage, and the second formation voltage is more than described first and formed Voltage,It is greater than during being greater than above-mentioned 3rd time during wherein above-mentioned second time, and during above-mentioned 3rd time above-mentioned During the very first time.
- 5. method of testing as claimed in claim 4, it is characterised in that the resistive memory cell include a first electrode, One second electrode and the variable resistance layer being arranged between the first electrode and the second electrode.
- 6. method of testing as claimed in claim 5, it is characterised in that described first forms voltage, the second formation voltage Or the setting voltage is provided to the first electrode of the resistive memory cell, and the reset voltage provide to The second electrode of the resistive memory cell.
- 7. method of testing as claimed in claim 5, it is characterised in that the checking journey is performed to the resistive memory cell The step of sequence, also includes：The reset voltage is provided to the second electrode of the resistive memory cell, and verifies that the resistance-type storage is single Whether the impedance state of member is first impedance by second impedance transition；AndThe setting voltage is provided to the first electrode of the resistive memory cell, and verifies that the resistance-type storage is single Whether the impedance state of member is second impedance by first impedance transition.
- 8. method of testing as claimed in claim 5, it is characterised in that after the proving program is completed, toast the electricity The step of resistive memory, also includes：After the proving program is completed, there is provided first electricity of the setting voltage to the resistive memory cell Pole, to obtain flowing through one first electric current of the resistive memory cell；AndAfter obtaining first electric current, the resistance-type memory is toasted.
- 9. method of testing as claimed in claim 8, it is characterised in that the method for testing also includes：The setting voltage is provided to the resistive memory cell toasted, to obtain flowing through the resistance-type memory One second electric current；AndAccording to first electric current and second electric current, obtain a data and preserve test result.
- 10. method of testing as claimed in claim 5, it is characterised in that stored providing setting voltage a to resistance-type After the step of unit, in addition to：Repeat to provide the reset voltage to the resistive memory cell and provide the setting voltage to the resistance-type The step of memory cell.
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| CN109215709B (en) * | 2017-07-03 | 2020-12-22 | 华邦电子股份有限公司 | Resistive memory device and method for setting resistive memory cell thereof |
| CN110060722B (en) | 2018-01-17 | 2021-10-08 | 华邦电子股份有限公司 | Power-on reset method of resistive memory storage device |
| CN110675906B (en) * | 2018-07-03 | 2021-10-08 | 华邦电子股份有限公司 | Method for detecting resistance type random access memory unit |
| CN111145811B (en) * | 2019-12-31 | 2021-11-09 | 清华大学 | Resistive random access memory array, operation method thereof and resistive random access memory circuit |
| CN111091858B (en) * | 2019-12-31 | 2021-11-09 | 清华大学 | Operation method of resistive random access memory array |
| TWI739381B (en) * | 2020-04-09 | 2021-09-11 | 新唐科技股份有限公司 | Integrated circuit, power verification circuit and power verification method |
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| CN102099863A (en) * | 2009-06-08 | 2011-06-15 | 松下电器产业株式会社 | Method of writing for resistance-change non-volatile memory element, and resistance-change non-volatile memory device |
| CN102667947A (en) * | 2010-09-28 | 2012-09-12 | 松下电器产业株式会社 | Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device |
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| CN102099863A (en) * | 2009-06-08 | 2011-06-15 | 松下电器产业株式会社 | Method of writing for resistance-change non-volatile memory element, and resistance-change non-volatile memory device |
| CN102667947A (en) * | 2010-09-28 | 2012-09-12 | 松下电器产业株式会社 | Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device |
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