CN105097021A - Resistive memory formation and test method - Google Patents
Resistive memory formation and test method Download PDFInfo
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- CN105097021A CN105097021A CN201410217577.8A CN201410217577A CN105097021A CN 105097021 A CN105097021 A CN 105097021A CN 201410217577 A CN201410217577 A CN 201410217577A CN 105097021 A CN105097021 A CN 105097021A
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Abstract
A resistive memory formation and test method is disclosed. A memory array comprises a plurality of resistive storage units; a processing module is used for sequentially providing a first formation voltage and a second formation voltage for the resistive storage units so as to enable the resistive storage units to switch from an insulation state to an impedance state; the processing module provides a reset voltage to the resistive storage units so as to transform the impedance state of the resistive storage units to first impedance; the processing module provides a set voltage to the resistive storage units so as to transform the impedance state of the resistive storage units from the first impedance to second impedance; and the set voltage is higher than the second formation voltage, and the second formation voltage is higher than the first formation voltage.
Description
Technical field
The present invention, about a kind of resistance-type memory, relates to formation and the method for testing of the resistance-type memory that can improve data dimension holding effect energy especially.
Background technology
At present, nonvolatile memory is with flash memory (Flash) for main flow, but along with the continuous micro of element, and flash memory faces grid and penetrates that oxide layer is excessively thin causes shorten storage time, and the shortcoming such as operating voltage is excessive.Therefore, what the nonvolatile memory of various different shape was just positive is developed to replace flash memory, wherein resistive random access memory (ResistiveRandomAccessMemory, RRAM) storage effect is reached by the change of resistance value, and the characteristic utilizing it non-volatile is as memory component, the advantage such as have that operating voltage is little, storage time is long, multimode stores, structure is simple and area is little.
Resistance-type memory after fabrication is complete, first through formation processing (formingprocess), can switch to impedance state to make resistance-type memory from state of insulation.Then, by setting resistance-type memory or resetting, the resistance value of resistance-type memory can be changed, to store data in resistance-type memory.Therefore, the impedance information of resistance-type memory can be obtained by measuring the electric current (such as setting electric current I set, reset current Ireset) flowing through resistance-type memory, and then obtain stored data.But resistance-type memory, after overbaking test, easily causes setting electric current I set to decline, and makes clearly to distinguish setting electric current I set and reset current Ireset.So the data of resistance-type memory maintain (retention) performance and can decline.
Therefore, a kind of resistance-type memory that can improve data maintenance performance is needed.
Summary of the invention
The object of this invention is to provide a kind of formation and method of testing of resistance-type memory, maintain performance with the data that can improve resistance-type memory.
Technical scheme of the present invention is to provide a kind of formation method, is applicable to a resistance-type memory with multiple resistive memory cell.Sequentially provide one first coating-forming voltage and one second coating-forming voltage to resistive memory cell, resistive memory cell is switched to an impedance state by a state of insulation.There is provided a reset voltage to resistive memory cell, to change the impedance state of resistive memory cell into one first impedance.There is provided a setting voltage to resistive memory cell, to be one second impedance by the impedance state of resistive memory cell by the first impedance transition.Setting voltage is greater than the second coating-forming voltage, and the second coating-forming voltage is greater than the first coating-forming voltage.
Present invention also offers a kind of method of testing, be applicable to a resistance-type memory with multiple resistive memory cell.Sequentially provide one first coating-forming voltage and one second coating-forming voltage to resistive memory cell, resistive memory cell is switched to an impedance state by a state of insulation.There is provided a reset voltage to resistive memory cell, to change the impedance state of resistive memory cell into one first impedance.There is provided a setting voltage to resistive memory cell, to be one second impedance by the impedance state of resistive memory cell by the first impedance transition.One proving program is performed to resistive memory cell.After completing proving program, baking resistance-type memory.Setting voltage is greater than the second coating-forming voltage, and the second coating-forming voltage is greater than the first coating-forming voltage.
By formation and the method for testing of resistance-type memory provided by the invention, resistance-type memory is after overbaking test, and the damping capacity of setting electric current can diminish, and the effect that data are preserved is better.In addition, by repeating to provide reset voltage and setting voltage to the storage unit in resistance-type memory after coating-forming voltage, the performance of storer can be increased, and promote the yield of storer.
Accompanying drawing explanation
The schematic diagram of the storage unit of the resistance-type memory of Fig. 1 display according to one embodiment of the invention;
The schematic diagram of the test macro of Fig. 2 display according to one embodiment of the invention;
The formation method of Fig. 3 display according to one embodiment of the invention, is applicable to a storage arrangement with multiple resistive memory cell;
Fig. 4 A shows the schematic diagram of applying coating-forming voltage VF1, VF2 according to one embodiment of the invention or setting voltage Vset to resistive memory cell;
Fig. 4 B shows the graph of a relation of voltage and time on end points T1 in Fig. 4 A;
Fig. 4 C shows the schematic diagram of the applying reset voltage Vreset according to one embodiment of the invention to resistive memory cell;
The method of testing of Fig. 5 display according to one embodiment of the invention, is applicable to a storage arrangement with multiple resistive memory cell; And
Fig. 6 shows the schematic diagram that data preserve test result, in order to the difference of the method for testing of conventional test methodologies and Fig. 5 to be described.
Main element symbol description
100 ~ storage unit;
110 ~ metal-insulator-metal type element;
120 ~ transistor;
200 ~ test macro;
210 ~ resistance-type memory;
220 ~ testing apparatus;
BL ~ bit line;
I ~ electric current;
S310-S340, S502-S518 ~ step;
VC ~ end points;
VF1, VF2 ~ coating-forming voltage;
Vreset ~ reset voltage;
Vset ~ setting voltage; And
WL ~ character line.
Embodiment
For above and other object of the present invention, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate institute's accompanying drawings, be described in detail below:
The schematic diagram of the storage unit 100 of the resistance-type memory of Fig. 1 display according to one embodiment of the invention.Storage unit 100 comprises metal-insulator-metal type element (metal-insulator-metal, hereinafter referred to as MIM element) 110 and transistor 120.MIM element 110 is coupled between bit line BL and transistor 120, and transistor 120 is coupled between MIM element 110 and source electrode line SL, and wherein the grid of transistor 120 is coupled to character line WL.In FIG, by applying a bias voltage to MIM element 110 to change the resistance value of MIM element 110.Such as, the resistance value of MIM element 110 is changed by bit line BL or source electrode line SL.In addition, when storage unit 100 is read, provide a reading voltage to this MIM element 110 by bit line BL, and why carry out the logic level of the data that determining storage unit 100 stores according to the change of the current value of MIM element 110.
The schematic diagram of the test macro 200 of Fig. 2 display according to one embodiment of the invention.Test macro 200 comprises resistance-type memory 210 and testing apparatus 220.Resistance-type memory 210 comprises the memory array formed by multiple storage unit (storage unit 100 of such as Fig. 1).Testing apparatus 220 can provide different voltage to the storage unit in resistance-type memory 210.For example, testing apparatus 220 can provide coating-forming voltage VF1 and coating-forming voltage VF2 to the storage unit in resistance-type memory 210, can switch to impedance state to make storage unit from original state (i.e. state of insulation).In other words, testing apparatus 220 can perform special electro photoluminescence program to storage unit, is also called formation processing (formingprocess).In addition, testing apparatus 220 can provide setting voltage Vset and reset voltage Vreset to storage unit respectively, to change the impedance of storage unit.Further, testing apparatus 220 can judge according to the electric current I of storage unit the data that storage unit stores.
The formation method of Fig. 3 display according to one embodiment of the invention, is applicable to a storage arrangement with multiple resistive memory cell.Simultaneously with reference to figure 2 and Fig. 3, first, in step S310, testing apparatus 220 can provide coating-forming voltage VF1 to the storage unit in resistance-type memory 210.Then, in step S320, testing apparatus 220 can provide coating-forming voltage VF2 to the storage unit in resistance-type memory 210, and wherein coating-forming voltage VF2 is greater than coating-forming voltage VF1, i.e. VF2>VF1.After step S310 and S320, the storage unit in resistance-type memory 210 can switch to impedance state by state of insulation.Then, in step S330, testing apparatus 220 can provide reset voltage Vreset to the storage unit in resistance-type memory 210, to carry out initialization replacement, makes the impedance state of storage unit change the first impedance into.Then, in step S340, testing apparatus 220 can provide setting voltage Vset to the storage unit in resistance-type memory 210, to be the second impedance by the impedance state of storage unit by the first impedance transition, wherein setting voltage Vset is greater than coating-forming voltage VF2, i.e. Vset>VF2.In this embodiment, the first impedance is high impedance, and the second impedance is Low ESR.
Fig. 4 A shows the schematic diagram of applying coating-forming voltage VF1, VF2 according to one embodiment of the invention or setting voltage Vset to resistive memory cell.In the diagram, storage unit comprises MIM element 400, and wherein MIM element 400 comprises electrode 410, variable resistance layer 420 and electrode 430.The material of electrode 410 and 430 is such as metal or silicon respectively.Variable resistance layer 420 is arranged between electrode 410 and electrode 430, and wherein variable resistance layer 420 can change its resistivity under different bias condition.In Figure 4 A, electrode 410 is coupled to end points T1, and electrode 430 is coupled to end points T2.In one embodiment, end points T1 is coupled to bit line BL (the bit line BL of such as Fig. 1), and end points T2 is coupled to source electrode line SL (the source electrode line SL of such as Fig. 1) via the transistor (transistor 120 of such as Fig. 1) of conducting.In Figure 4 A, coating-forming voltage VF1, coating-forming voltage VF2 and setting voltage Vset are applied to same electrode 410 via end points T1.In addition, when coating-forming voltage VF1, coating-forming voltage VF2 or setting voltage Vset are applied to electrode 410, source electrode line SL can be grounded, so end points T2 can be coupled to earth terminal GND via transistor, i.e. and 0V.
Fig. 4 B shows the graph of a relation of voltage and time on end points T1 in Fig. 4 A.At time durations P1, coating-forming voltage VF1 can be applied on end points T1.Then, at time durations P2, coating-forming voltage VF2 can be applied on end points T1, and wherein the voltage level of coating-forming voltage VF2 is greater than the voltage level of coating-forming voltage VF1.Then, at time durations P3, setting voltage Vset can be applied on end points T1, and wherein the voltage level of setting voltage Vset is greater than the voltage level of coating-forming voltage VF2.In this embodiment, time durations P2 is greater than time durations P3, and time durations P3 is greater than time durations P1.It should be noted that the time span of time durations P1, P2 and P3 in Fig. 4 B and relativeness are only examples, and be not used to limit the present invention.In other embodiments, the time span of time durations P1, P2 and P3 and relativeness determined by practical application.
Fig. 4 C shows the schematic diagram of the applying reset voltage Vreset according to one embodiment of the invention to resistive memory cell.The electrode 410 of MIM element 400 is coupled to end points T1, and the electrode 430 of MIM element 400 is coupled to end points T2.As described previously, in one embodiment, end points T1 is coupled to bit line BL (the bit line BL of such as Fig. 1), and end points T2 is coupled to source electrode line SL (the source electrode line SL of such as Fig. 1) via the transistor (transistor 120 of such as Fig. 1) of conducting.In figure 4 c, when reset voltage Vreset is applied to electrode 430 via end points T2, bit line BL can be grounded, so end points T1 can be coupled to earth terminal GND via transistor, i.e. and 0V.It should be noted that MIM element 400, coating-forming voltage VF1, coating-forming voltage VF2 and setting voltage Vset are applied to same electrode, and reset voltage Vreset is applied to another electrode.
The method of testing of Fig. 5 display according to one embodiment of the invention, is applicable to a storage arrangement with multiple resistive memory cell.Simultaneously with reference to figure 2 and Fig. 5, first, in step S502, testing apparatus can provide coating-forming voltage VF1 to the storage unit in resistance-type memory 210.Then, in step S504, testing apparatus can provide coating-forming voltage VF2 to the storage unit in resistance-type memory 210, and wherein coating-forming voltage VF2 is greater than coating-forming voltage VF1, i.e. VF2>VF1.After step S502 and S504, the storage unit in resistance-type memory 210 can switch to impedance state by state of insulation.Then, in step S506, testing apparatus can provide reset voltage Vreset to the storage unit in resistance-type memory 210, to carry out initialization replacement, makes the impedance state of storage unit change the first impedance into.Then, in step S508, testing apparatus can provide setting voltage Vset to the storage unit in resistance-type memory 210, to be the second impedance by the impedance state of storage unit by the first impedance transition, wherein setting voltage Vset is greater than coating-forming voltage VF2, i.e. Vset>VF2.In this embodiment, the first impedance is high impedance, and the second impedance is Low ESR.As described previously, step S502-step S508 can be considered the formation program of storage unit.In addition, in one embodiment, testing apparatus can repeat to provide reset voltage Vreset (step S506) and setting voltage Vset (step S508) to the storage unit in resistance-type memory 210, to increase the performance of storage unit.Then, in step S510, testing apparatus can perform proving program, to confirm that whether storage unit is normal to the storage unit in resistance-type memory 210.In proving program, testing apparatus 220 can provide reset voltage Vreset to the storage unit in resistance-type memory 210, to be the first impedance by the impedance state of storage unit by the second impedance transition.Then, testing apparatus 220 can confirm whether the impedance state of storage unit successfully changes the first impedance into.Then, testing apparatus 220 can provide setting voltage Vset to the storage unit in resistance-type memory 210, to be the second impedance by the impedance state of storage unit by the first impedance transition.Then, testing apparatus 220 can confirm whether the impedance state of storage unit successfully changes the second impedance into.By that analogy, testing apparatus can perform multiple authentication program to storage unit, and the number of times wherein performing proving program can determine according to practical application.After completing proving program, testing apparatus can provide setting voltage Vset to storage unit, to obtain flowing through the setting electric current I set1 (step S512) of MIM element in resistive memory cell.Then, in step S514, testing apparatus can be toasted (baking) resistance-type memory.Such as, with a specific high temperature (such as close to the high temperature of 200 DEG C) baking one special time (such as 24 hours) continuously.Then, in step S516, testing apparatus can provide the storage unit of setting voltage Vset to having toasted, to obtain flowing through the setting electric current I set2 of MIM element in resistive memory cell.Then, in step S518, testing apparatus can obtain according to the setting electric current I set2 after the setting electric current I set1 before baking and baking the test result that data preserve (retention).
Fig. 6 shows the schematic diagram that data preserve test result, in order to the difference of the method for testing of conventional test methodologies and Fig. 5 to be described.In conventional test methodologies, single coating-forming voltage is only used to switch to impedance state to make resistive memory cell by state of insulation.In addition, in conventional test methodologies, coating-forming voltage and setting voltage have identical voltage level.In figure 6, transverse axis represents the setting electric current attenuation percentage after baking of storage unit, and the longitudinal axis represents the Cumulative Distribution Function (CumulativeDistributionFunction, CDF) of setting electric current.In addition, curve 610 represents that the data of conventional test methodologies preserve test result, and curve 620 represents that the data of the method for testing of Fig. 5 preserve test result.Significantly, curve 620 all drops within 50%.Therefore, by using the coating-forming voltage in two stages (i.e. VF1 and VF2) and using the setting voltage (Vset) being greater than coating-forming voltage to change the impedance of MIM element, storage unit can be made after overbaking, and the damping capacity of setting electric current diminishes.So the effect that data are preserved is better.In addition, by repeating to provide reset voltage Vreset and setting voltage Vset (i.e. step S506 and S508) to the storage unit in resistance-type memory 210 after coating-forming voltage, the performance of storer can be increased, and promote the yield of storer.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any art comprises knows the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (10)
1. a formation method, is applicable to a resistance-type memory with multiple resistive memory cell, it is characterized in that, described formation method comprises:
Sequentially provide one first coating-forming voltage and one second coating-forming voltage to described resistive memory cell, described resistive memory cell is switched to an impedance state by a state of insulation;
There is provided a reset voltage to described resistive memory cell, to change the described impedance state of described resistive memory cell into one first impedance; And
There is provided a setting voltage to described resistive memory cell, to be one second impedance by the described impedance state of described resistive memory cell by described first impedance transition;
Wherein said setting voltage is greater than described second coating-forming voltage, and described second coating-forming voltage is greater than described first coating-forming voltage.
2. form method as claimed in claim 1, it is characterized in that, the variable resistance layer that described resistive memory cell comprises one first electrode, one second electrode and is arranged between described first electrode and described second electrode.
3. form method as claimed in claim 2, it is characterized in that, described first coating-forming voltage, described second coating-forming voltage or described setting voltage are provided to described first electrode of described resistive memory cell, and described reset voltage is provided to described second electrode of described resistive memory cell.
4. a method of testing, be applicable to a resistance-type memory with multiple resistive memory cell, it is characterized in that, described method of testing comprises:
Sequentially provide one first coating-forming voltage and one second coating-forming voltage to described resistive memory cell, described resistive memory cell is switched to an impedance state by a state of insulation;
There is provided a reset voltage to described resistive memory cell, to change the described impedance state of described resistive memory cell into one first impedance;
There is provided a setting voltage to described resistive memory cell, to be one second impedance by the described impedance state of described resistive memory cell by described first impedance transition;
One proving program is performed to described resistive memory cell; And
After completing described proving program, toast described resistance-type memory;
Wherein said setting voltage is greater than described second coating-forming voltage, and described second coating-forming voltage is greater than described first coating-forming voltage.
5. method of testing as claimed in claim 4, is characterized in that, the variable resistance layer that described resistive memory cell comprises one first electrode, one second electrode and is arranged between described first electrode and described second electrode.
6. method of testing as claimed in claim 5, it is characterized in that, described first coating-forming voltage, described second coating-forming voltage or described setting voltage are provided to described first electrode of described resistive memory cell, and described reset voltage is provided to described second electrode of described resistive memory cell.
7. method of testing as claimed in claim 5, it is characterized in that, the step described resistive memory cell being performed to described proving program also comprises:
There is provided described reset voltage to described second electrode of described resistive memory cell, and whether the described impedance state verifying described resistive memory cell is described first impedance by described second impedance transition; And
There is provided described setting voltage to described first electrode of described resistive memory cell, and whether the described impedance state verifying described resistive memory cell is described second impedance by described first impedance transition.
8. method of testing as claimed in claim 5, it is characterized in that, after completing described proving program, the step of toasting described resistance-type memory also comprises:
After completing described proving program, provide described setting voltage to described first electrode of described resistive memory cell, to obtain one first electric current flowing through described resistive memory cell; And
After obtaining described first electric current, toast described resistance-type memory.
9. method of testing as claimed in claim 8, it is characterized in that, described method of testing also comprises:
There is provided the described resistive memory cell of described setting voltage to having toasted, to obtain one second electric current flowing through described resistance-type memory; And
According to described first electric current and described second electric current, obtain data and preserve test result.
10. method of testing as claimed in claim 5, is characterized in that, after providing a setting voltage to the step of described resistive memory cell, also comprises:
Repeat provide described reset voltage to described resistive memory cell and provide described setting voltage to the step of described resistive memory cell.
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