TWI535162B - Multiphase voltage regulator with advanced phase number control, control circuit and method thereof - Google Patents

Description

Multiphase voltage regulator with advanced phase number control, control circuit and method thereof

This invention relates to a multiphase voltage regulator, and more particularly to a method for controlling the number of phases in a multiphase voltage regulator.

Cross-references to related applications

The present invention claims to be entitled "Advanced phase number control for improving efficiency and fast transient response in multiphase converter applications" ("Attorney Profile No. INTS-29, 041") filed on July 14, 2008. Application No. 61/080,380, the entire disclosure of which is incorporated herein by reference.

A multiphase converter is a circuit topology in which a plurality of voltage regulator circuits are placed in parallel between an input and a load. Each phase is turned on at equal intervals during a switching cycle. This circuit is typically coupled to a non-synchronous buck topology. The main advantage of this type of converter is that the load current is shunted between multiple end phases of the multiphase converter. This load split allows the heat loss on each switch to be spread over a large area. Another important advantage provided by multiphase configuration is that the output chopping is separated by the number of phases. The load then experiences a chopping frequency equivalent to the number of phases multiplied by the switching frequency. This multiphase topology provides An additional benefit of improved system response to dynamic changes in current. A large increase in load current can be solved by turning on additional phase as needed.

In multiphase buck converters, the efficiency may not be maximized because all phases operate at different current load levels. In order to achieve better efficiency, it is necessary to adjust the number of phases of operation based on the current load current. Under light load conditions, the number of phases of operation is reduced to produce fewer drivers and switching losses, resulting in improved efficiency. The conventional technical solution monitors the load current by sensing the output inductor current to determine the optimal number of phases under different load conditions. This technical solution works well for applications with low transient response. However, in a voltage regulator application of a central processing unit, the load current may jump from 10 amps to 100 amps in 100 nanoseconds. When only one phase operates at a load of 10 amps, the transient response is very bad if the transient current is processed in an accelerated manner without quickly adding back the other phases. Therefore, it is not sufficient to control the number of phases within a multiphase converter based solely on the sensed inductor current. The ability to quickly reduce and add one of the number of phases in a multiphase converter is such that the multiphase converter is sufficiently responsive to fast transient response within the multiphase voltage regulator. This is because during a fast transient event, the load current can jump very high for a short period of time, and the inductor current will vary greatly between the load current and the inductor current. Slowly climbed. These would require fewer phase numbers to handle the initial step load current variation under the same load conditions. When phase addition is based solely on the sensed inductor current, these require very poor initial response due to the number of phases that are less operational.

One aspect of the present invention as disclosed and described herein includes more than one Phase voltage regulator. The multiphase voltage regulator includes switching circuitry for generating an output voltage responsive to an input voltage. An error amplifier generates an error correction voltage responsive to the output voltage and a reference voltage. The PWM logic generates a phase signal for each phase of the multiphase voltage regulator in response to the error correction voltage and at least one ramp voltage. The drive logic generates a plurality of control signals to the switching circuitry to respond to the respective phase signals. The control circuitry generates at least one control signal to add a phase as an output of the PWM logic in response to a determination that the error correction voltage has exceeded a threshold value.

102‧‧‧ single phase buck converter

104‧‧‧Chip switch

106‧‧‧Chip switch

108‧‧‧ Phase node

110‧‧‧Drive Logic

112‧‧‧Output inductor

114‧‧‧Output voltage node

116‧‧‧ capacitor

118‧‧‧Error amplifier

120‧‧‧PWM Logic

121‧‧‧PWM comparator

122‧‧‧Voltage feedback sensing circuit system

123‧‧‧Reference ramp voltage

202‧‧‧Multiphase Converter

204‧‧‧Inductors

206‧‧‧Input voltage node

208‧‧‧phase node

210‧‧‧ capacitor

212‧‧‧Resistors

214‧‧‧Upper gate switching transistor

216‧‧‧lower gate switching transistor

217‧‧‧Multiphase controller

302‧‧‧Load current

402‧‧‧ Output COMP signal

502‧‧‧ nodes

504‧‧‧Compensation voltage original

506‧‧‧ comparator

508‧‧‧Sampling switch

510‧‧‧ nodes

512‧‧‧Sampling clock signal

514‧‧‧ capacitor

602‧‧‧I _LOAD signal

604‧‧‧RAMP signal

606‧‧‧sampled_V _COMP +△V signal

608‧‧‧sampled_COMP signal

610‧‧‧COMP signal

612‧‧‧sampling_clock signal

614‧‧‧PWM phase signal

616‧‧‧ Downward ramp

618‧‧‧ Downward ramp

702-712‧‧‧Steps

802‧‧‧ nodes

804‧‧‧Sampling switch

806‧‧‧Sampling clock signal

808‧‧‧ nodes

810‧‧‧ capacitor

812a-812c‧‧‧ nodes

814‧‧‧Compensation voltage

902‧‧‧ nodes

906‧‧‧ switch

908‧‧‧Down ramp comparator

1002‧‧‧Load current

1004‧‧‧COMP_SH2 signal

1006‧‧‧COMP_SH1 signal

1008‧‧‧sampled COMP signal

1010‧‧‧COMP error voltage signal

1012‧‧‧sample_clock signal

1014‧‧‧PWM phase signal

1102-1114‧‧‧Inquiry steps

1402-1404‧‧‧Transient

For a more complete understanding of the present invention, reference has been made to the above description and the accompanying drawings in which: FIG. 1 is a schematic block diagram of a buck regulator; FIG. 2 is a multi-phase buck regulator converter; 3 is a diagram illustrating a manner in which the number of phases can be controlled based on a load current; FIG. 4 is a diagram illustrating a manner in which a COMP signal from a voltage error amplifier can be controlled to control the number of phases; FIG. 5 is based on the V of the voltage error amplifier. _COMP voltage is a schematic diagram of a first control circuit for controlling the number of phases; FIG. 6 is a waveform diagram associated with the operation of the first control circuit of FIG. 5; FIG. 7 is a diagram illustrating the first control of FIG. A flowchart of the operation of the circuit; FIG. 8 is a circuit diagram showing a second embodiment for generating a control signal in response to the V _COMP voltage of the voltage error amplifier; FIG. 9 is a diagram showing the number of phases generated in response to the voltage. further circuitry of a second embodiment of the error amplifier voltage V _COMP; waveform diagram associated with the system described in FIG. 10 and FIG. 8 and 9 of the circuitry; FIG. 11 is described in FIG. 8 and the circuit 9 A flowchart illustrating the operation of the system; FIG. 12 One of the phase control system described alternative method; FIG. 13 described patented system 12 using the hysteresis range (Hysteresis) control method; and FIG. 14 illustrates another system of a phase control method.

Referring now to the drawings in which like reference numerals are used throughout the the the the the the the the the Other possible embodiments. The drawings are not necessarily to scale, and are in the In general, the skilled person will understand numerous possible applications and variations based on the examples of the various possible embodiments described below.

1 is a schematic block diagram of a standard single phase buck converter 102. A pair of transistor switches 104 and 106 are connected in series between the input voltage node V _IN and ground. The source of transistor switch 104 is coupled to the drain of transistor switch 106 at phase node 108. The upper transistor switch 104 is such that its drain is coupled to the input voltage node V _IN and its gate receives a control signal from the drive logic 110. The source of the transistor switch 104 is coupled to the drain of the lower transistor switch 106 at the phase node 108. The lower transistor switch 106 has its drain coupled to the phase node 108 and receives a lower gate control signal from the drive logic 110. The phase node 108 is coupled through an output inductor 112 coupled between it and the output voltage node V _OUT 114. A capacitor 116 is coupled between the output voltage node V _OUT 114 and the ground.

The control circuitry of the pair of transistor switches 104 and 106 includes an error amplifier 118, PWM logic 120, and the drive logic 110. In a typical configuration, the error amplifier 118 senses the output voltage _VOUT using a certain type of voltage feedback sensing circuitry 122. In response to the sensed output voltage and a reference voltage VREF, the error amplifier 118 produces a compensation signal COMP at its output to provide to the PWM logic 120. The sensed feedback voltage from the output voltage node V _OUT 114 is provided to the inverting input of the error amplifier 118. The PWM logic 120 includes a PWM comparator 121 that compares the error voltage signal V _COMP applied to the non-inverting input of the PWM comparator 121 to the PWM comparator 121 from an oscillator. A reference ramp voltage 123 of the inverting input. The output of the PWM comparator 121 is applied to the driver circuitry 110. This process provides a pulse width modulation (PWM) waveform having an amplitude V _IN at the phase node 108. The pulse width modulation waveform provided from the phase node 108 is smoothed by an output filter composed of the output inductor 112 and the capacitor 116.

Based on the pulse width modulation signal, the drive logic 110 asserts the UGATE signal to a logic "high" to turn on the switching transistor 104, and establishes the LGATE signal to a logic "low" to turn off the switching transistor 106 to The input voltage V _{IN is} coupled through the output inductor L to drive the voltage level of V _OUT . The drive logic 110 asserts the UGATE signal to a logic "low" and the LGATE signal to a logic "high" to turn off the switching transistor 104 and turn on the switching transistor 106. In this manner, this operation is based on a duty cycle of the PWM signal provided by the PWM logic 120.

Referring now to FIG. 2, within one of the multiphase converter circuits illustrated at 202, multiple inductors 204 are coupled between input voltage node 206 and a phase node 208. One A capacitor 210 and a resistor 212 are connected in parallel between the phase node 208 and ground. Each inductor 204 has a pair of switching transistors associated therewith. The manner in which upper gate switching transistor 214 and lower gate switching transistor 216 operate is similar to that discussed herein with respect to the standard single phase buck converter of FIG. The upper gate switching transistor 214 and the lower gate switching transistor 216 are responsive to a plurality of switching control signals from the polyphase control logic 217.

The multiphase converter 202 is a circuit topology in which a plurality of basic buck converter circuits are placed in parallel between an input and a load. Each of the "phases" is turned on at equal intervals during the switching period. This circuit is typically coupled to a non-synchronous buck topology. The main advantage of this type of converter is that the load current is shunted between multiple end phases of the multiphase converter. This load split allows the heat loss on each switch to be spread over a large area. Another important advantage provided by multiphase configurations is that the output chopping is separated by the number of phases N. The load then experiences a chopping frequency equivalent to the number of phases N multiplied by the switching frequency. This multiphase topology provides an additional benefit in that the system response to dynamic changes in current can be improved. A large increase in load current can be solved by turning on additional phase as needed.

In multiphase buck converters, the efficiency may not be maximized because all phases operate at different current load levels. In order to achieve better efficiency, it is necessary to adjust the number of phases of operation based on the current load current. Under light load conditions, the number of phases of operation is reduced to produce fewer drivers and switching losses, resulting in improved efficiency. The conventional technical solution monitors the load current by sensing the output inductor current to determine the optimal number of phases under different load conditions. This technical solution works well for applications with low transient response. However, in a voltage regulator application of a central processing unit, the load current may be at 100 The nanosecond system jumped from 10 amps to 100 amps. When only one phase operates at a load of 10 amps, the transient response is very bad if the transient current is processed in an accelerated manner without quickly adding back the other phases. Therefore, it is not sufficient to control the number of phases within a multiphase converter based solely on the sensed inductor current. The ability to quickly reduce and add one of the number of phases in a multiphase converter is such that the multiphase converter is sufficiently responsive to fast transient response within the multiphase voltage regulator. This is because during a fast transient event, the load current can jump very high for a short period of time, and the inductor current will vary greatly between the load current and the inductor current. Slowly climbed. These would require fewer phase numbers to handle the initial step load current variation under the same load conditions. When phase addition is based solely on the sensed inductor current, these require very poor initial response due to the number of phases that are less operational.

Referring now to Figure 3, the manner indicated is where load current I _L 302 can be used to control the number of phases provided within a multiphase converter. As can be seen, the load at _a level I system provides only a single phase PWM1. Similarly, the phase PWM1 and PWM2 provided at the load level at _two lines I. Level as the load increases, the number of phases provided by the Department still increased until the current load above the level I _5, wherein each of the six PWM signals are phase system is utilized. In this way, by adjusting the number of phases in accordance with the load current, the optimum efficiency over the entire load range can be achieved.

Referring now to Figure 4, the manner of illustration is based on the output of the error amplifier of the multiphase voltage regulator rather than controlling the number of phases based on the load current I _L . These enable the system to rapidly reduce and add the number of phases to a regulator based on the output voltage V _OUT or the output voltage V _{COMP of} the error amplifier. Based on the voltage step change strength and slew rate at the error amplifier, one or more phase systems can be added back in a relatively rapid manner to handle transient responses, such as in a central processing unit VR application. If the load current drops rapidly, one or more phase systems can be reduced in one step to further improve efficiency. Within the VR controller, the phase is often reduced to include operational efficiency in the low power state. During a fast transient event, the output voltage will drop rapidly due to the ESL and ESR of the output capacitor, and the output COMP signal 402 of the error amplifier will increase to a high level.

The proposed phase number control scheme adds multiple phases back to the system based on the deviation of the COMP signal 402. The system will have multiple levels and join the phases one by one. Thus, when the total number of COMP phase signal 402 at time T ₀ to the bit time has already started to increase as indicated by the number of single phase system will be added back. When the COMP signal 402 continues to increase from the time T ₀ to the time T ₁ , a second phase is added back at time T ₁ . Similarly, by the COMP signal 402 continuing to increase from the time T ₀ to the time T ₄ , the plurality of phases are added at the respective COMP voltage levels associated with the addition of another phase until all phases are at the time T ₄ The office has been put back and operated.

Referring now to FIG. 5, a first embodiment of a circuitry for generating a plurality of control signals to the polyphase controller 217 is illustrated for adding a plurality of phases to a polyphase conversion in response to an output voltage V _{COMP of the} error amplifier. And removing multiple phases from the multiphase converter. The output voltage V _COMP of the error amplifier is provided to a node 502. A compensation voltage source 504 is coupled between the node 502 and a non-inverting input of a comparator 506. A sampling switch 508 is coupled between the node 502 and the node 510. The node 510 is coupled to the inverting input of the comparator 506. The sampling switch 508 is controlled in response to a sampled clock signal 512. A capacitor 514 is connected between the node 510 and ground. The output of the comparator 506 provides a control signal for providing an indication to add a phase to the multiphase controller 217.

The output voltage V _COMP of the error amplifier is sampled by the sampling switch 508 at its rising edge on the rising edge of each pulse width modulated signal of each active phase. If the voltage V _COMP is higher than the voltage of V _COMP of the receiving node 502 from the premises plus an applied voltage △ V compensation voltage source 504 of the compensation, the phase of a multiphase system by the addition of the voltage regulator in response to the comparator The output of 506 goes to a logical "high" level. The output voltage V _COMP of the error amplifier at the node 502 is again sampled by the sampling switch 508 to adjust the threshold voltage for the next triggering action. If the output voltage V _{COMP of} the error amplifier continues to increase and reaches an updated threshold, another phase is added to go back to a logical "high" level in response to the output of the comparator 506.

Referring now to Figure 6, various waveforms associated with the operation of the circuit system of Figure 5 are illustrated. The I _LOAD signal 602 represents the load current flowing through the inductor of the buck regulator. The RAMP1 signal 604 includes a ramp signal applied in the PWM logic to generate the PWM control signal. The sampled_COMP+ΔV signal 606 illustrates the voltage applied to the non-inverting input of the comparator 506. The sampled_COMP signal 608 indicates the V _COMP voltage sampled by the sampling switch 508. The COMP signal 610 includes the V _COMP error voltage to be applied at the node 502. The sample_clock signal 612 controlling the sampling switch 508 includes a sampling clock pulse at each rising edge of the PWM signal. PWM1 through PWM3 illustrate various PWM phase signals 614 that can be added to the multiphase voltage regulator in response to the V _COMP signal 610.

It can be seen from time T ₀ that only a single phase signal PWM1 614 will be utilized due to the low error voltage signal 610. When the PWM1 pulse rise at time T _0, this pulse train 612 to establish the pulse signal 608 sampled_comp lock at the level 610 V _COMP signal is sampled at a time at a time T _0. Since the sampled_comp signal 608 is lower than the sampled_comp+ΔV signal 606, it is not necessary to add an extra phase. Similar results were also achieved at times T ₁ and T ₂ . When this 610 V at _{the COMP} signal at a time T ₄ jumped to the top of sampled_comp + △ V signal 606, an additional phase PWM2 signal lines 614 at a time T ₄ is initialized. Further, at time T ₄ due to the increase of the voltage signal COMP 610, so that sampled_comp + △ V signal 606 is updated to a higher level in line ₄ time T, the order of addition of the phase needs to be prepared next. At time T ₅ , the COMP voltage signal 610 has continued to increase and reaches a new critical level at time T ₅ , causing the next phase PWM 3 signal 614 to be turned on, and the critical signal 606 (sampled_comp + ΔV) is It was updated to a new level again. Such PWM2 and PWM3 respectively based phase signal 614 at time T ₇ and T ₈ is produced in response to its own ramp 616 and downlink 618, which actuation system response by the PWM logic associated with some of the phase Was produced.

Referring now to Figure 7, a flow chart depicting the operation of the circuit system of Figure 5 is illustrated. Once the operation of the circuitry is initialized, the error voltage V _COMP is sampled by the sampling switch 508 (step 702). The threshold voltage including the sampled V _COMP voltage and the voltage compensation ΔV is determined (step 704). The critical signal including the compensation V _COMP and the sample V _COMP is compared (step 706) such that the query (step 708) determines if the sample voltage is much greater than the critical compensation voltage. If not the foregoing, then control returns to step 702. If the query (step 708) determines that the sampled voltage is much greater than the compensation threshold, then an additional phase is added to the multiphase converter (step 708) and the critical compensation V _COMP + ΔV is updated (step 708) such that The V _COMP voltage is compared to a new critical level during the next iteration to determine if an additional phase is required.

Referring now to Figures 8 and 9, an alternative embodiment of a control circuit for adding multiple phases to a multi-phase voltage regulator is illustrated in response to monitoring of the error amplifier voltage. FIG. 8 illustrates the error voltage V _COMP applied at node 802. A sampling switch 804 samples the error voltage V _COMP in response to a sampled clock signal 806. The sampling clock signal 806 causes the error voltage V _COMP to sample its peak value at the rising edge of each PWM pulse signal of each phase. The sampling switch 804 is coupled between the nodes 802 and 808. A capacitor 810 is connected between the node 808 and ground. Connected between the node 808 and the nodes 812a through 812e is a series of compensation voltages 814.

Each of the nodes 812a through 812e is associated with an inverting input of the reduced-phase downstream ramp-wave comparator 908. The downstream ramp comparator 908 corresponds to the comparator 121 previously described with respect to FIG. The non-inverting input of the downstream ramp comparator 908 is coupled to receive the error voltage V _COMP . The inverting input of the downstream ramp comparator 908 is coupled to a switch 906. The switch 906 is coupled to a ramp signal (applied to the downstream ramp comparator 908 at node 902) and a compensation threshold (V _COMP + ΔV) (from the circuit system of FIG. 8 supplied to the node 812) Choose between. The circuit system of Figure 9 will include multiple iterations, each of which is associated with one of a plurality of outputs 812 that provide critical compensation from the circuitry of Figure 8. The switch 906 is coupled to the node 902 while the phase associated with the downstream ramp comparator 908 is operating, and the ramp signal is driving the phase associated with the downstream ramp comparator 908. When the phase is not running, the switch 906 connects the inverting input to the nodes 812 such that the compensation threshold voltage can be compared to the error voltage V _COMP . When the down-ramp comparator 908 determines that the error voltage V _COMP exceeds the threshold compensation voltage, the switch 906 is coupled to the ramp voltage provided at the node 902 to initiate actuation of the phase. The first pulse supplied to the phase is generated in response to the output of the down-ramp comparator 908 to a logic "high" level, when the COMP voltage exceeds the compensation threshold voltage and the remaining phases are subjected to a ramp voltage control.

Referring now to Figure 10, there are illustrated waveforms associated with the operation of the circuitry of Figures 8 and 9. As seen in the load current line 1002 can be held to a relatively low level, until the time T ₃ starts increasing. The COMP_SH2 signal 1004 represents the output of the down-ramp comparator associated with one phase of the multi-phase voltage regulator. The COMP_SH1 signal 1006 is associated with a downstream phase ramp comparator of a second phase. The sampled_COMP signal 1008 is a voltage that is included in the sampling switch 804 for sampling. The COMP error voltage signal 1010 represents the V _COMP voltage input at the node 802. The sampled_clock signal 1012 represents a control signal applied to the sampling switch 804, and the sampling switch 804 provides a pulse on each rising edge of one of the PWM signals of the system signals. The sampled_clock signal 1012 is only generated on the rising edge of one of the PWM pulses within one of the plurality of phase signals. The COMP error voltage signal 1010 is sampled in response to the sampling clock signal.

When the time T ₀ to T ₂ is sampled, when the V _COMP voltage 1010 does not increase beyond the COMP_SH1 signal 1006 or the COMP_SH2 signal 1004, the sampled_comp signal 1008 remains at the same level. The COMP_SH1 signal 1006 is sent to the phase ramp 2 downlink ramp comparator 908, and the COMP_SH2 signal 1004 is sent to the phase number 3 down ramp comparator 908. When the error voltage signal COMP 1010 jumped over the COMP_SH1 signal 1006, PWM2 based 1014 phase signal immediately at time T ₄ is turned on. When the error voltage signal COMP 1010 rises above the signal COMP_SH2 1004, PWM3 phase signal line 1014 is turned on immediately at time T _5. After the foregoing time, the PWM2 and PWM3 phase signals 1014 are respectively generated at times T ₇ and T ₈ by the ramps they have connected by the switch 906, once the down ramp comparator 908 Indicates that the V _COMP voltage has exceeded the COMP_SHX threshold voltage.

Referring now to Figure 11, a flow diagram of one of the operations of the circuit system of Figures 8 and 9 is illustrated. Once the process is initialized, the V _COMP voltage is sampled by sampling switch 906 (step 1102). The various ΔV compensations associated with each phase are added to the sampled signal (step 1104), and the critical compensation voltages are provided from the compensation circuitry to the input of the downstream ramp comparator 908. The next down ramp comparator is currently selected in association with an operational phase (step 1106). The query (step 1108) determines whether the error voltage V _COMP associated with the currently selected lower ramp comparator 908 is much greater than the compensated threshold voltage applied to the comparator. If so, the ramp signal associated with the downstream ramp comparator is coupled to the comparator (step 1110) instead of the critical compensation signal. This causes the phase to be turned on and added to the multiphase voltage regulator (step 1112). If the query (step 1108) determines that the error compensation voltage does not exceed the critical compensation voltage, or once a new phase has been added, then a query (step 1114) determines if there is another downstream ramp comparator 908. If so, the control passes back to step 1106 and the error voltage/critical compensation decision is repeated for the new downstream ramp comparator. If there is no additional downstream ramp comparator, then the control passes back to step 1102 where the error voltage can begin sampling.

In an additional embodiment, a plurality of phase load windows can be programmed into the controller IC at the power-on time of the buck regulator circuit. These phase load windows are determined The number of phases of a voltage regulator should be given in response to the average load current being sent by the buck regulator circuit. The phase load windows are effectively stacked on top of each other, and the plurality of transitions are defined to add an extra phase or remove a phase threshold. Thus, as illustrated in Figure 12, five different phase windows are illustrated and each has a 15 amp window associated with it. Therefore, a single phase operating system is associated with a current between 0 and 15 amps. The two-phase operating system is associated with one of 15 to 30 amps of current. The three phase operating system is associated with one of 30 to 45 amps of current. The four-phase operating system is associated with one of 45 to 60 amps of current, and the five-phase operating system is associated with one of 60 to 75 amps of current. Adding such additional phases or removing the phase occurs when passing a critical level of 15 amps, 30 amps, 45 amps, or 60 amps. Once passed a critical level, the number of phases associated with the critical level is then generated. Therefore, when the sensed average load current is in a particular current window, the current phase window is first entered, and the appropriate number of phases associated with the current window is sequentially added or shifted after a set of time periods. except.

Referring now to Figure 13, there is illustrated a method for adding multiple phases, wherein the phase load window will be programmed into and out of the controller IC when the power is turned on, a hysteresis level. Also established. The hysteresis level sets the current level to place the voltage regulator in the next higher or lower load window. Therefore, the hysteresis level is above the falling threshold. For example, continue to refer to the 15 amp load window previously described for Figure 12. If a hysteresis level of 15 amps is established, the voltage regulator currently in the lowest load window of 0 to 15 amps will not enter 15 30 amps of the second load window until it has exceeded one of the current levels of 20 amps. Once the sensed load current has exceeded the rise threshold, the additional phase is added immediately. Similarly, moving from two phase levels In a phase level, the load current will have to be reduced to a level of 10 amps, 5 amps below the 15 amp window level.

Referring now to Figure 14, in an alternative embodiment for entering multiple phases, two different voltage levels are programmed into the controller IC when the power is turned on. These voltage levels set two APA open levels. The output voltage is continuously monitored, and if a fast transient has caused the output voltage to change rapidly and violates a threshold, the APA will be turned off. When the first threshold is violated, both phases are immediately added to the circuitry. When the second critical value is destroyed, all remaining non-valid phase systems are added immediately. None of the above actions have any associated delays therein. The above described operation illustrates Figure 14 in which the transient 1402 is shown rising only above two phase levels. When the foregoing occurs, two additional phase systems will be added immediately. Similarly, when transient 1404 exceeds all phase levels, each non-valid phase is added.

Using the embodiments described above, multiple phase systems can be quickly added in response to changes in multiple error compensation voltages. The number of phases added is based only on the strength of the COMP voltage and the conversion rate to conform to the transient response.

It will be appreciated by those skilled in the art having the advantages of this disclosure that the present disclosure provides an advanced phase number control for a multiphase converter. The drawings and detailed description are to be considered as illustrative and not restrict In contrast, any further modifications, changes, re-compositions, substitutions, substitutions, design choices, and various embodiments are apparent to those of ordinary skill in the art without departing from the invention The spirit and scope defined by the scope. Therefore, the scope of the patent application to be described later is interpreted. All such further modifications, variations, re-configurations, substitutions, alternatives, design choices, and various embodiments are included.

302(I _LOAD )‧‧‧Load current

I ₁ -I ₅ ‧‧‧load level

PWM1-PWM6‧‧‧ phase signal

Claims (17)

A multiphase voltage regulator comprising: a switching circuit system for generating an output voltage in response to an input voltage; an error amplifier for generating an error correction voltage responsive to the input voltage and a reference voltage a PWM logic for generating a phase signal for each phase of the multiphase voltage regulator in response to the error correction voltage and at least one ramp voltage; driving logic for generating a plurality of control signals to The switching circuitry is responsive to the phase signals; and the control circuitry is operative to generate at least one control signal during a clock cycle of the sampling clock to drop a phase as one of the PWM logic outputs In response to the error, the voltage is determined to be less than a critical level. The multiphase voltage regulator of claim 1, wherein the control circuit system further comprises: a sampling circuit for sampling the error correction voltage during a previous clock cycle to generate a a sampling error correction voltage; a compensation generator circuit for providing a voltage compensation to the sampled error correction voltage to establish a threshold voltage; and a comparator for using the error correction voltage and the threshold The voltage is compared, wherein when the error correction voltage is less than the threshold voltage and during the clock cycle of the sampling clock, the comparator generates the at least one control signal to drop the phase as the output of the PWM logic. A multiphase voltage regulator according to claim 2, wherein the sampling circuit comprises a switch. The multiphase voltage regulator of claim 2, wherein the control circuit system further comprises: a sampling circuit for sampling the error correction voltage; and a plurality of compensation generator circuits for Providing a plurality of voltage compensations to the sampled error correction voltage to establish a plurality of threshold voltages; and a plurality of comparators each associated with a phase of the multiphase voltage regulator and having a first mode of operation And wherein when the phase associated with the comparator is not operational, the comparator compares the error correction voltage to one of the plurality of threshold voltages and has a second mode of operation, wherein when compared to the comparison When the phase associated with the device is operating, the comparator compares the error correction voltage to one of the ramp voltages associated with the phase. The multiphase voltage regulator of claim 4, wherein the sampling circuit includes a switch for switching between the ramp voltage and the plurality of threshold voltages, the open relationship from the plurality One of the threshold voltages is switched to the ramp voltage in response to a decision made by the comparator for the error correction voltage being less than one of the plurality of threshold voltages. A control circuit for generating a control signal for dropping a plurality of phases from a multiphase voltage regulator, the control circuit comprising: an input for receiving one of the multiphase voltage regulators An error correction voltage of the error amplifier; at least one output for providing a PWM control signal; and control circuitry for generating at least one during a clock cycle of a sampling clock The PWM control signals are used to drop a phase of the multiphase voltage regulator in response to a decision that the error correction voltage has been less than a critical level. The control circuit of claim 6, wherein the control circuit system further comprises: a sampling circuit for sampling the error correction voltage during a previous clock cycle to generate a sample error correction a compensation generator circuit for providing a voltage compensation to the error correction voltage to establish the threshold voltage; and a comparator for comparing the sampled error correction voltage with the threshold voltage And wherein the comparator generates the at least one PWM control signal to add the phase to the multiphase voltage regulator when the sampled error correction voltage is less than the threshold voltage and during the clock cycle of the sampling clock This phase is lowered. The control circuit of claim 7, wherein the sampling circuit comprises a switch. The control circuit of claim 6, wherein the control circuit system further comprises: a sampling circuit for sampling the error correction voltage; and a plurality of compensation generator circuits for providing a plurality of Voltage compensating to the error correction voltage to establish a plurality of threshold voltages; and a plurality of comparators each associated with a phase of the multiphase voltage regulator having a first mode of operation, wherein When the phase associated with the comparator is not operating, the comparator compares the sampled error correction voltage to one of the plurality of threshold voltages and has a second mode of operation, wherein when associated with the comparator When the phase is working, The comparator compares the error correction voltage to one of the ramp voltages associated with the phase. The control circuit of claim 9, wherein the sampling circuit includes a switch for switching between the ramp voltage and the plurality of threshold voltages, the switching relationship being from the plurality of threshold voltages One of the switches switches to the ramp voltage in response to a decision made by the comparator for the error correction voltage to be less than one of the plurality of threshold voltages. A method for dropping a plurality of phases from a multiphase voltage regulator, the method comprising the steps of: receiving an error correction voltage from an error amplifier of one of the multiphase voltage regulators; determining the error correction voltage Whether it is less than a threshold voltage level; generating at least one PWM control signal during a clock cycle of a sampling clock to lower a phase of the multi-phase voltage regulator, in response to the error correction voltage being less than the threshold voltage a decision of the level; and providing the control operation of the at least one PWM control signal to the multiphase voltage regulator. The method of claim 11, wherein the determining step further comprises the steps of: sampling the error correction voltage during a previous clock cycle to generate a sampled error correction voltage; adding a voltage compensation to The sampled error correction voltage is used to establish the threshold voltage level; and the error correction voltage is compared to the threshold voltage level. The method of claim 12, wherein the generating step further comprises the step of: generating the at least one PWM control when the error correction voltage is less than the threshold voltage level The signal is signaled to drop the phase from the multiphase voltage regulator. The method of claim 12, wherein the sampling step further comprises the step of switching a value of the error correction voltage to store the value of the error correction voltage. The method of claim 11, wherein the determining step further comprises the steps of: sampling the error correction voltage; adding a plurality of voltage compensations to the sampled error correction voltage to establish a plurality of threshold voltage levels; Comparing the error correction voltage to one of the plurality of threshold voltage levels for each of the plurality of comparators in a first mode of operation when the phase associated with the comparator is not operating; and when comparing When the phase associated with the device is operating, the error correction voltage is compared to a ramp voltage for each of the plurality of comparators in a second mode of operation. The method of claim 15, wherein the generating step further comprises the step of: generating the at least one PWM signal corresponding to the comparison result when the error correction voltage is less than at least one of the plurality of threshold voltage levels To reduce the phase from the multiphase voltage regulator. The method of claim 15, further comprising the steps of: determining whether the error correction voltage is less than one of the plurality of threshold voltage levels; and in the ramp voltage and the plurality of threshold voltage levels Switching between the ones is responsive to a determination of whether the error correction voltage is less than one of the plurality of threshold voltage levels.