TWI534986B - High voltage ed nmos embedded high voltage lateral njfet - Google Patents

Description

High voltage ED NMOS device embedded in high voltage lateral NJFET

Particular embodiments of the present invention are generally associated with semiconductor devices and, more particularly, with an n-channel metal oxide field effect transistor (NMOS) including an embedded high voltage junction gate field effect transistor (JFET).

High press cycles have been widely used in power management integrated circuits (PMICs) and switched power supplies (SMPS), both of which are commonly used as LED drivers.

In recent years, the steadily increasing number of effective "green" electronic devices of interest has forced device manufacturers to seek higher conversion efficiency and lower standby power consumption. Switching mode power ICs require integrated start-up circuitry and pulse width modulation (PWM) circuitry. Unfortunately, a typical high voltage starting circuit uses a power resistor approach in which power is continuously dissipated by the power resistor after starting. The power resistor is selected such that it will provide a charging current for the capacitor and PWM circuitry during the startup operation. The PWM circuit will continue to operate until its Vcc voltage is below the minimum operating voltage rating at which point the auxiliary voltage is applied to Vcc of the PWM circuit. The PWM circuit operates normally between 5V and 30V.

In recent years, the power line voltage (ie, AC100~240V) is used to drive the LED in the LED driver IC. These LED driver ICs conventionally use a buck converter and include a high voltage switching type NMOS to provide current to drive the LEDs. Conventional solutions also use high voltage depletion MOS to provide a reference voltage or power to supply internal circuitry. However, high voltage depletion MOS requires additional circuit areas and additional masks for formation. Therefore, there is a need for an alternative to existing traditional solutions.

Some example embodiments thus point to an n-channel metal oxide field effect transistor (NMOS or nMOSFET) that includes an embedded high voltage junction gate field effect transistor (JFET). In some examples, an NMOS embedded JFET may be provided based at least in part on modifications to a standard high voltage (HV) process, and may not require additional masking or programming. In this manner, embodiments of the present invention may use existing semiconductor device processes to provide a high voltage JFET in a relatively small area by embedding the HV JFET in the source or drain edge of the NMOS.

In an exemplary embodiment, a semiconductor device is provided that includes a P-type substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and disposed adjacent to the N-type A well and an N+ doped region on opposite sides of the first and second P-type well regions. The P-type well region includes a P+ doped region, a third N+ doped region, and a gate structure, and a third N+ doped region is interposed between the P+ doped region and the gate structure.

According to a second exemplary embodiment, there is provided a semiconductor device including a P-type substrate, an N-type well region disposed adjacent to the substrate, first and second P-type well regions disposed adjacent to the N-type well region, and setting It is adjacent to the N-type well region and a third P-type well region of the substrate. The N-type well region includes first and second P-type well regions such that at least a portion of the N-type well region is interposed in the first and second, second, and third, and first and third P-type well regions between. The semiconductor device still further includes first and second N+ doped regions disposed adjacent to the N-type well and on opposite sides of the first and second P-type well regions. The third P-type well includes a third P+ doped region, the second P-type well region includes a second P+ doped region, and the first P-type well includes a first P+ doped region, a third N+ doped region, and a first P-type well region A gate structure, a third N+ doped region is interposed between the first P+ doped region and the gate structure. At least a portion of the first P-type well region is interposed between the first P+ doped region and the first N+ doped region.

According to a third exemplary embodiment, there is provided a semiconductor device including a P-type substrate, an N-type well region disposed adjacent to the substrate, a first P-type well region disposed adjacent to the N-type well region, and disposed adjacent to the N-type well region And a second P-type well region of the substrate, and first and second N+ doped regions disposed adjacent to the N-type well region and on opposite sides of the first P-type well region. The N-type well region includes a first P-type well region such that at least a portion of the N-type well region is between the first and second P-type well regions. The second P-type well includes a second P+ doped region, and the first P-type well region includes a first P+ doped region, a third N+ doped region, and a gate structure, the third N+ doped region being between P+ Doped region and gate junction Between the structures. At least a portion of the second P-type well region is interposed between the first P+ doped region and the first N+ doped region.

The above described embodiments and other details of the invention are described below, and corresponding and other embodiments of the NMOS with embedded JFETs in the present invention are also described below.

101‧‧‧JFET

102‧‧‧NMOS

103‧‧‧IC package

201‧‧‧P type material substrate

205‧‧‧Additional P-type well area

207‧‧‧First P-type well area

208‧‧‧N type well area

209‧‧‧First N+ doped area

210‧‧‧Second N+ doped region

211‧‧‧ gate structure

212‧‧‧P-top part

213‧‧‧N-type layer

214‧‧‧P+ doped area

215‧‧‧ Third N+ doped area

216‧‧ ‧ field oxidation

305‧‧‧ Third P-type well area

307, 405‧‧‧Second P-type well area

308, 409‧‧‧Second P+ doped area

309‧‧‧ Third P+ doped area

The invention has been described in detail above with reference to the drawings, which are not necessarily drawn to scale, and wherein: FIG. 1a depicts a block diagram of a conventional buck converter circuit; FIG. 1b depicts a block of an example embodiment Figure 2a depicts an equivalent circuit representation in accordance with a first exemplary embodiment of the present invention; Figure 2b depicts a top view of a semiconductor device in accordance with the first exemplary embodiment; and Figure 2c depicts a semiconductor device illustrated in Figure 2b along line A Two cross-sectional views of -A' and BB'; FIG. 3a depicts an equivalent circuit representation in accordance with a second exemplary embodiment of the present invention; and FIG. 3b depicts a top view of the semiconductor device in accordance with the second exemplary embodiment; Figure 3c depicts two cross-sectional views of the semiconductor device illustrated along Figure 3b along lines A-A' and BB'; Figure 4a depicts an equivalent circuit representation in accordance with a third exemplary embodiment of the present invention; Figure 4b depicts A top view of the semiconductor device according to the third exemplary embodiment; FIG. 4c depicts two cross-sectional views of the semiconductor device illustrated in FIG. 4b along lines AA' and BB'; FIG. 5a depicts a fourth exemplary embodiment Electrical map; Figure 5b depicts A top view of the semiconductor device according to the fourth exemplary embodiment; FIG. 5c depicts two cross-sectional views of the semiconductor device illustrated in FIG. 5b along lines AA' and BB'; FIG. 6a depicts a fifth example implementation a top view of the semiconductor device of the example; and FIG. 6b depicts two horizontal lines of the semiconductor device along the line A-A' and BB' illustrated in FIG. 6a Sectional view.

Some embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings in which, In fact, the various embodiments of the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. .

Some example embodiments of the present invention may provide an NMOS, such as a high voltage switching type NMOS with an embedded JFET (eg, a high voltage JFET). For example, the JFET can be embedded at the source or drain edge of the NMOS. The JFET of the example embodiment can thus be provided in a relatively small area. Moreover, the JFET of the example embodiment can provide a breakdown voltage that is the same or nearly the same as the high voltage switching type NMOS in some examples. An example embodiment may use an N-type well to form the JFET-embedded channel, such as an NJFET. Example embodiments may allow the clamping voltage of the embedded JFET to be varied, for example, by adjusting the spacing of the P-well or high voltage N-well (HVNW) associated with the NMOS source. Another example embodiment may allow for changing the characteristics of the linear and saturated regions by adjusting the width of the P-type well associated with the NMOS source. For example, the conversion of a JFET from a linear to a saturated region can be more impulsive, such as a sudden increase in the width of a P-well.

Example embodiments may be made, at least in part, using standard high pressure (HV) processes, such as without the use of any additional masks or processes, in some examples. Example embodiments may use a germanium local oxidation (LOCOS) process, a shallow trench isolation (STI) process, a deep trench isolation (DTI) process, a silicon-on-insulator (SOI) process, epitaxial (EPI) (eg, N/P). -EPI) Process, and / or non-EPI process. N-channels embedded in JFETs, such as NJFETs, can be embodied, for example, as N-type wells, N-type drift layers, N-type buffer layers, or/and N-type deep wells. According to an example embodiment, the HV JFET may be embedded in a HV NMOS of various structures, such as a circular structure HV NMOS or an elliptical structure HV NMOS. Example embodiments of the invention may be applied to current sources or decompression devices in some examples. Certain example embodiments may be configured to supply power between 5V and 30V to a pulse width modulation (PWM) circuit, for example, by adjusting the HV JFET pinch voltage as discussed above.

Figure 1a depicts a block diagram of a conventional buck conversion circuit that can be used, for example, to drive an LED. As shown in Figure 1a, the conventional buck converter circuit requires high voltage depletion. The NMOS is used to provide a reference voltage or power to supply internal circuitry and individual MOSFETs to provide current to drive the load. Because HV depletion NMOS and HV MOSFETs are present in separate integrated circuit (IC) packages, the overall size of a conventional buck conversion circuit can be relatively large. In contrast, FIG. 1b depicts a block diagram of an example embodiment of the present invention in which JFET 101 and HV NMOS 102 are provided in a single IC package 103 by embedding JFET 101 in NMOS 102. Thus, the overall circuit maintains similar electrical performance compared to the conventional buck conversion circuit depicted in Figure 1a, but with a reduced footprint.

Turning now to Figures 2a through 6b, the various structures of the exemplary embodiments of the present invention will now be discussed below.

Figure 2a depicts a block diagram of an equivalent circuit of the first exemplary embodiment in which the gate (G) of the embedded JFET 101 is combined with the source (S) of the NMOS 102. 2b depicts a top view of an example configuration of the first example embodiment in which the gate of the embedded JFET 101 is combined with the source of the NMOS 102. As shown, this example configuration provides two embedded JFETs near the source terminal of NMOS 102. The approximate location of one of the embedded JFETs 101 is surrounded by a dashed line. To understand the structure of the embedded JFET 101 and how it conforms to the structure of the NMOS, please refer to Figure 2c, in which two cross-sectional views are depicted along lines A-A' and BB' of Figure 2b. According to some embodiments, the cross-sectional view taken along line BB' (from the perspective of the top view of Figure 2b) may be the same as the cross-sectional view taken along line A-A', such as the second dotted line A -A' line pointed out. According to this embodiment, the distance between the first P-type well region 207 through which the A-A' solid line passes and the first P-type well region 207 through which the A-A' dashed line passes can be adjusted to adjust the embedding. The clamping voltage of JFET 101. However, according to the structure of other example embodiments of the structure, the cross-sectional views may not be the same.

From the cross-sectional view along line AA' in Figure 2c, it can be seen that, according to the depicted example embodiment, the P-type material substrate 201 can be provided with an N-type well region 208 disposed thereon, such as a high pressure N-type well. (HVNW) area. A first P-well region 207 can be disposed adjacent to the N-well region 208. It will be understood by comparing two cross-sectional views along the two AA' lines and the cross-sectional views along the line BB' in the top view depicted in Figure 2b, according to an example embodiment, second The P-type well region may be further disposed adjacent to the N-type well region. The N-type well region 208 can thus include the first and second P-type well regions 207 such that at least a portion of the N-type well region 208 is between the first and second P-type well regions 207. As shown in FIG. 2c, the first and second N+ doping regions 209, 210 can It is disposed adjacent to the N-well region 208 and on the opposite side of the first P-well region 207. As shown, the first N+ doped region 209 corresponds to the source embedded in the JFET 101, and the second N+ doped region 210 corresponds to the NMOS 102 and the drain of the JFET 101. As further shown in FIG. 2c, the first P-type well region 207 can include a P+ doped region 214, a third N+ doped region 215, and a gate structure 211, the third N+ doped region 215 being interposed between P+ doping The region 214 is between the gate structure 211. The gate structure 211 can be coupled to the common operation of the third N+ doping region 215 and the P+ doping region 214. As shown, the third N+ doping region 215 and the P+ doping region 214 collectively correspond to the source of the NMOS 102. The pole is also embedded in the gate of JFET 101.

The field oxidation portion (FOX) 216 may be further disposed adjacent to the N-type well region 208. For example, the first FOX portion may be disposed adjacent one end of the first N+ doping region 209, and the second FOX portion may be interposed between the end of the first N+ doping region 209 and the end of the P+ doping region 214, and the third FOX Portions may be interposed between the P-well region and the end of the second N+ doped region 210, and more between the gate structure 211 and the first P-well region 207. Additional P-type well regions 205 may also be disposed adjacent to the N-type well region 208 and between the first FOX portion 216 and the P-type substrate. The N-type layer 213 and the P-top portion 212 may also be disposed adjacent to the N-type well region 208, and the N-type layer 213 is interposed between the third FOX portion 216 and the P-top portion 212.

Fig. 3a depicts a block diagram of an equivalent circuit of the second exemplary embodiment in which the gate (G) embedded in the JFET 101 is isolated. Figure 3b depicts a top view of an example configuration of a second example embodiment in which the gates embedded in JFET 101 are isolated. Although only half of the NMOS 102 is shown in FIG. 3b, this example configuration can also provide two embedded JFETs near the source terminal of NMOS 102. To understand the structure of the embedded JFET 101 and how it conforms to the structure of the NMOS, please refer to Figure 3c, in which two cross-sectional views are depicted along lines A-A' and BB' of Figure 3b.

As can be seen from the cross-sectional view of line B-B' in Figure 3c, in accordance with the depicted example embodiment, P-type material substrate 201 can be provided with an N-type well region 208 disposed thereon. Referring to the first embodiment depicted in FIG. 2c, the first P-well region 207 can be disposed adjacent to the N-well region 208, and the first and second N+ doped regions 209, 210 can be disposed adjacent to the N-type The well region 208 is on the opposite side of the first P-well region 207. As shown, the first N+ doped region 209 corresponds to the source embedded in the JFET 101, and the second N+ doped region 210 corresponds to the NMOS 102 and the drain of the JFET 101. As shown in Fig. 2c, the first P-type well region 207 A first P+ doped region 214, a third N+ doped region 215, and a gate structure 211 may be included, the third N+ doped region 215 being interposed between the first P+ doped region 214 and the gate structure 211. The gate structure 211 can be coupled to the third N+ doping region 215 and the first P+ doping region to operate together. As shown, the third N+ doping region 215 and the first P+ doping region collectively correspond to the HV NMOS. The source of 102.

A second P-well region 307 can also be disposed adjacent to the N-well region 208. As shown, the N-type well region can include first and second P-type well regions 207, 307 such that a portion of the N-type well region 208 is between the two. The distance between the first P-well region 207 and the second P-well region 307 can be adjusted to adjust the clamping voltage of the embedded JFET. As shown, the second P-well region can include a second P+ doped region 308 that corresponds to the isolated gate embedded in the JFET.

As shown in the cross-sectional view along line A-A', the third P-well region 305 can also be disposed adjacent to the N-well region 208 and the P-type substrate 201. As shown, the third P-well region 305 can have a third P+ doped region 309 disposed thereon that can correspond to the base of the embedded JFET 101. As will be more readily understood by referring back to FIG. 3b, portions of the third P-type well region 305 may be interposed between the third P+ doped region 309 and the first N+ doped region 209. Furthermore, a portion of the N-type well region 208 can be interposed between the second P-type well region 307 and the third P-type well region 305 and between the first P-type well region 207 and the third P-type well region 305. .

The FOX portion 216 can also be disposed adjacent to the N-well region 208. For example, with reference to a cross-sectional view along line BB', a first FOX portion can be disposed adjacent the end of the first N+ doped region 209, and a second FOX portion can be interposed between the end of the first N+ doped region 209 and a second Between the ends of the P+ doping region 308, the third FOX portion may be between the end of the second P+ doping region 308 and the end of the first P+ doping region 214, and the fourth FOX portion may be interposed between the first P Between the well region 207 and the end of the second N+ doped region 210, and the fourth FOX portion is further between the gate structure 211 and the first P-type well region 207. The N-type layer 213 and the P-top portion 212 may also be disposed adjacent to the N-type well region 208 between the fourth FOX portion 216 and the P-top portion 212.

Figure 4a depicts a block diagram of an equivalent circuit of a third example embodiment in which the gate (G) embedded in JFET 101 is separate. Figure 4b depicts a top view of an example configuration of a second example embodiment in which the gates embedded in JFET 101 are separate. Although only half of the NMOS 102 As shown in FIG. 3b, this example configuration can also provide two embedded JFETs near the source terminal of NMOS 102. To understand the structure of the embedded JFET 101 and how it conforms to the structure of the NMOS, please refer to Figure 4c, in which two cross-sectional views are depicted along lines A-A' and BB' of Figure 4b.

As can be seen from the cross-sectional view of line B-B' in Figure 4c, in accordance with the depicted example embodiment, P-type material substrate 201 can be provided with an N-type well region 208 disposed thereon. Referring to the first embodiment depicted in FIG. 2c, the first P-well region 207 can be disposed adjacent to the N-well region 208, and the first and second N+ doped regions 209, 210 can be disposed adjacent to the N-type The well region 208 is on the opposite side of the first P-well region 207. As shown, the first N+ doped region 209 corresponds to the source embedded in the JFET 101, and the second N+ doped region 210 corresponds to the NMOS 102 and the drain of the JFET 101. As further shown in FIG. 2c, the first P-type well region 207 can include a P+ doped region 214, a third N+ doped region 215, and a gate structure 211, the third N+ doped region 215 being interposed between P+ doping The region 214 is between the gate structure 211. The gate structure 211 can be coupled to the common operation of the third N+ doping region 215 and the P+ doping region 214. As shown, the third N+ doping region 215 and the P+ doping region 214 collectively correspond to the source of the NMOS 102. pole.

The second P-well region 405 can also be disposed adjacent to the N-well region 208 and the P-type substrate 201 as shown along the cross-sectional view of line A-A'. As shown, the second P-well region 405 can have a second P+ doped region 409 disposed thereon that can correspond to a gate embedded in the JFET 101. As will be more readily understood by referring back to FIG. 4b, a portion of the second P-well region 405 can be interposed between the first P+ doped region 409 and the first N+ doped region 209. With continued reference to Figure 4b, the distance between the "upper" P-well 405 and the "lower" P-well 405 (that is, the P-well 405 on either side of the HVNW 208) can be adjusted. To adjust the clamping voltage embedded in JFET 101.

The FOX portion 216 can be disposed adjacent to the N-well region 208. For example, the first FOX portion may be disposed adjacent to an end of the first N+ doping region 209; the second FOX portion may be interposed between an end of the first N+ doping region 209 and an end of the first P+ doping region 214; The third FOX portion may be between the first P-type well region and the end of the second N+ doped region 210 and more between the gate structure 211 and the first P-type well region 207. The N-type layer 213 and the P-top portion 212 may also be disposed adjacent to the N-type well region 208, and the N-type layer 213 is interposed between the third FOX portion 216 and the P-top portion 212.

Referring now to Figures 5a, 5b, and 5c, the gates of the JFET 101 embedded in the third exemplary embodiment are separate, and the third exemplary embodiment can form the basis of a multi-channel embedded JFET structure that can add JFETs. Extreme current. For example, Figure 5a depicts a comparison between the five-channel JFET and the single-channel JFET's drain current. As shown, the five-channel JFET structure can produce more than five times the drain current of a single-channel JFET structure below the comparable Vds voltage. As shown in Figure 5b, the multi-channel embedded JFET structure can be provided by replicating the structure of the JFET embedded along the single channel of the NMOS periphery depicted in Figure 4b. More precisely, as can be seen from the cross-sectional views of A-A' and BB' depicted in Figure 5c, the internal structure is nearly identical to the internal structure of a single channel single gate embedded JFET depicted in Figure 4c. . However, certain example embodiments may present differences, such as in the configuration of the second P+ doped region 409 depicted in Figures 5b and 5c, which may, for example, be offset inward.

Figures 6a and 6b depict other variations of the individual gate-embedded JFETs of Figures 4b and 4c. In this example embodiment, the embedded JFET is formed adjacent to the NMOS drain 210 instead of the adjacent NMOS source. As shown in Figures 6a and 6b, there may be minor to insignificant structural differences between the drain side embedded JFET and the source side embedded JFET as discussed above.

The N-type well region 208 of the example embodiment may be formed of an N-type well, an N-type drift layer, an N-type buffer layer, and an N-type deep well. The P-well region of the example embodiment can be stacked using a P-well and a P+ buried layer or P-implant. In some examples, the N-well region 208 of the example embodiment may also be an N-implant.

Example embodiments may thus provide a relatively small size JFET embedded in an NMOS (eg, HV NMOS), such as an NJFET or HV NJFET. Again, example embodiments can be applied to standard HV processes without the need for additional masks or processes. Thus, circuits that can include both JFETs and NMOSs (eg, buck conversion circuits) can benefit from the reduced circuit package provided by the NMOS embedded JFET structures provided herein.

Other embodiments of the invention and many modifications presented herein will be apparent to those skilled in the art, which are intended to cover the teachings of the foregoing description and related drawings. Therefore, it is understood that the invention is not limited to the specific embodiments disclosed, and modifications and other embodiments are included in the scope of the appended claims. The exemplary embodiments of the present invention are described by way of example only, and the combination of different elements and/or functions may be provided by different embodiments without departing. The scope of the attached request. In this regard, for example, not only the foregoing is explicitly described, but in addition to the above, various combinations of elements and/or functions are also included in some of the appended claims. Although specific nouns are used herein, they are used for general purposes and description only, and not for purposes of limitation.

201‧‧‧P type material substrate

205‧‧‧Additional P-type well area

207‧‧‧First P-type well area

208‧‧‧N type well area

209‧‧‧First N+ doped area

210‧‧‧Second N+ doped area

211‧‧‧ gate structure

212‧‧‧P-top part

213‧‧‧N-type layer

214‧‧‧P+ doped area

215‧‧‧ Third N+ doped area

216‧‧ ‧ field oxidation

Claims (20)

A semiconductor device comprising: a P-type substrate; an N-type well region disposed adjacent to the substrate; a P-type well region disposed adjacent to the N-type well region; and first and second N+ doped regions Provided adjacent to the N-type well and on opposite sides of the first and second P-type well regions; wherein the P-type well region includes a P+ doped region, a third N+ doped region, and a gate structure The third N+ doped region is between the P+ doped region and the gate structure. The semiconductor device of claim 1, further comprising a second P-type well region, the N-type well region including the first and second P-type well regions, such that at least a portion of the N-type well region is Between the first and second P-type well regions. The semiconductor device of claim 1, further comprising first, second, and third field oxidation (FOX) portions disposed adjacent to the N-type well region, the first FOX portion being further configured to Adjacent to the first N+ doping region, the second FOX portion is between the first N+ doping region and the P+ doping region, and the third FOX portion is interposed between the P-well and the second N+ doping Between the interstitial zones and between the gate structure and the P-well. The semiconductor device of claim 3, further comprising an N-type layer disposed adjacent to the N-type well region and a P-top portion interposed between the third FOX portion and the P - between the top parts. The semiconductor device of claim 3, further comprising an additional P-type well region disposed adjacent to the N-type well and between the first FOX portion and the P-type substrate. The semiconductor device of claim 1, wherein a source of a junction gate field effect transistor (JFET) is associated with the first N+ doped region, and a drain of the JFET is associated with The second N+ doped region, and a gate of the JFET are associated with the P+ doped region and the third N+ doped region. The semiconductor device of claim 6, wherein a source of an n-channel metal oxide field effect transistor (NMOS) is associated with the P+ doped region and the third N+ doped region, and A drain of the NMOS is associated with the second N+ doped region. A method for fabricating a semiconductor device, comprising: providing a P-type substrate; providing an N-type well region disposed adjacent to the substrate; providing a P-type well region disposed adjacent to the N-type well region; Providing first and second N+ doped regions disposed adjacent to the N-type well and opposite sides of the first and second P-type well regions; wherein the P-type well region includes a P+ doped region, a first And a third N+ doped region interposed between the P+ doped region and the gate structure. The method of claim 8, further comprising providing a second P-type well region, the N-type well region including the first and second P-type well regions, such that at least a portion of the N-type well region is interposed Between the first and second P-type well regions. The method of claim 8, further comprising providing a first, second, and third field oxidation (FOX) portion disposed adjacent to the N-well region, the first FOX portion being further configured to Adjacent to the first N+ doping region, the second FOX portion is further between the first N+ doping region and the P+ doping region, and the third FOX portion is interposed between the P-well and the second N+ Doping Between the zones and more between the gate structure and the P-well. The method of claim 10, further comprising providing an N-type layer and a P-top portion disposed adjacent to the N-type well region, the N-type layer being interposed between the third FOX portion and the P - between the top parts. The method of claim 10, further comprising providing an additional P-type well region disposed adjacent to the N-type well and between the first FOX portion and the P-type substrate. The method of claim 8, wherein a source of a junction gate field effect transistor (JFET) is associated with the first N+ doped region, and a drain of the JFET is associated with the a second N+ doping region, a gate of the JFET is associated with the P+ doping region and the third N+ doping region, and a source relationship of an n-channel metal oxide field effect transistor (NMOS) The P+ doped region and the third N+ doped region, and a drain of the NMOS are associated with the second N+ doped region. A semiconductor device comprising: a P-type substrate; an N-type well region disposed adjacent to the substrate; a first P-type well region disposed adjacent to the N-type well region; and a second P-type well region, Arranged adjacent to the N-type well region and the substrate, the N-type well region including the first P-type well region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions And first and second N+ doped regions disposed adjacent to the N-type well region and opposite sides of the first P-type well region; wherein the second P-type well region includes a second P+ doping Zone, and the first P-type well zone contains a a P+ doped region, a third N+ doped region, and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure; and wherein the second P-type well region At least a portion of the first P+ doped region and the first N+ doped region. The semiconductor device of claim 14, further comprising a field oxidation (FOX) portion disposed adjacent to the N-type well region and between the first P-type well region and the second N+ doped region And between the gate structure and the first P-type well region. The semiconductor device of claim 15, further comprising a P-top portion disposed adjacent to the N-type well region and an N-type layer interposed between the FOX portion and the P-top Between the points. The semiconductor device of claim 14, further comprising a third P-type well region including a third P+ doping region disposed adjacent to the N-type well region and The substrate is such that at least a portion of the third P-type well region is between the third P+ doped region and the first N+ doped region. The semiconductor device of claim 14, wherein a source of a junction gate field effect transistor (JFET) is associated with the first N+ doped region, and a drain of the JFET is associated with The second N+ doped region, and a gate of the JFET are associated with the second P+ doped region. The semiconductor device of claim 18, wherein a source of an n-channel metal oxide field effect transistor (NMOS) is associated with the first P+ doped region and the third N+ doped region And a drain of the NMOS is associated with the second N+ doped region. The semiconductor device of claim 17, further comprising: fourth, fifth, sixth and seventh P-type well regions, respectively comprising fourth, fifth, sixth and a seventh P+ doped region; and fourth, fifth, sixth, and seventh N+ doped regions disposed adjacent to the N-type well region, the fourth, fifth, sixth, and seventh N+ doped regions An opposite side of the second P-type well region from the second N+ doping region; wherein the fourth N+ doping region is between the second and fourth P-type well regions, the fifth An N+ doped region is interposed between the fourth and fifth P-type well regions, the sixth N+ doped region is between the fifth and sixth P-type well regions, and the seventh N+ doped region is interposed Between the sixth and seventh P-type well regions.