TWI534973B - Chip bonding structure and bonding method thereof - Google Patents
Chip bonding structure and bonding method thereof Download PDFInfo
- Publication number
- TWI534973B TWI534973B TW103101443A TW103101443A TWI534973B TW I534973 B TWI534973 B TW I534973B TW 103101443 A TW103101443 A TW 103101443A TW 103101443 A TW103101443 A TW 103101443A TW I534973 B TWI534973 B TW I534973B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric layer
- wafers
- wafer
- wafer bonding
- metal pads
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Micromachines (AREA)
- Wire Bonding (AREA)
Description
本揭露係關於一種晶片結構,特別是一種晶片接合結構及其接合方法。 The present disclosure relates to a wafer structure, particularly a wafer bonding structure and bonding method thereof.
現今電子產品朝向輕薄短小、高效能發展,高度系統整合與無線化的方向發展。而三維積體電路(3D IC)為晶片三維堆疊整合模式,不僅可縮短金屬導線長度及連線電阻,更能減少晶片面積,具體積小、整合度高、耗電量低、成本低等特性,被認為是下世代半導體新技術。 Today's electronic products are developing in a light, short, high-efficiency, highly integrated system and wireless direction. The three-dimensional integrated circuit (3D IC) is a three-dimensional stack integration mode of the wafer, which not only shortens the length of the metal wire and the wiring resistance, but also reduces the wafer area, and has the characteristics of small accumulation, high integration, low power consumption, low cost, and the like. It is considered to be the next generation of semiconductor new technology.
三維積體電路堆疊對於元件間內部電路之電性接觸可靠度具有高度要求,以確保整合系統運作正常。然而,在晶圓級的積體電路堆疊卻遭遇到接合表面不夠平整的問題,使得製造廠商不易實現晶圓級的積體電路堆疊製程。其中,接合表面不平整的問題尤其易發生在混合式晶片接合(hybrid bond)製程上。混合式晶片接合係指晶片同時具有介電層及金屬。於混合式晶片接合時,同時將介電層對接與金屬對接,其中容易因介電層與金屬的高度不一致,或是金屬或介電層容易產生凹陷而造成晶片接合度(密合度)不足的問題。當晶片接合度不足時,晶片接合處就會產生空隙,位於金屬接合處的空間會造成電性開路現象,位於介電層處之空隙會增加晶片在後續熱製程發生破裂的機率。如此一來,就會造成晶片接合的 良率下降。 The three-dimensional integrated circuit stack has high requirements for electrical contact reliability of internal circuits between components to ensure that the integrated system operates normally. However, the stacking of integrated circuits at the wafer level suffers from a problem that the bonding surface is not flat enough, making it difficult for manufacturers to implement a wafer-level integrated circuit stacking process. Among them, the problem of unevenness of the bonding surface is particularly likely to occur in a hybrid wafer bonding process. Hybrid wafer bonding means that the wafer has both a dielectric layer and a metal. When the hybrid wafer is bonded, the dielectric layer is butted to the metal, and the height of the dielectric layer and the metal are not uniform, or the metal or the dielectric layer is likely to be recessed, resulting in insufficient wafer bonding degree (adhesion). problem. When the wafer bonding is insufficient, a gap is formed at the wafer joint, and a space at the metal joint causes an electrical open circuit, and a gap at the dielectric layer increases the probability of the wafer being broken in a subsequent thermal process. As a result, wafer bonding is caused. The yield is reduced.
本揭露之一實施例所述的晶片接合方法,其步驟包含提供二晶片。每一晶片的製造方法包含形成第一介電層於基板上。嵌合多個金屬墊於第一介電層上。形成多個凹陷於至少一晶片之第一介電層。這些凹陷分別介於這些金屬墊之間。形成第二介電層於具有這些凹陷之晶片之第一介電層上,並覆蓋於晶片之這些凹陷上及這些金屬墊上。接合二晶片,令二晶片之這些金屬墊彼此接觸,以及令其中一晶片之這些凹陷與另一晶片之表面構成多個空腔,且第二介電層位於這些空腔內。以機械驅動方式令第二介電層填滿這些空腔。壓合二晶片,並固化第二介電層,且令二晶片相互固定。 The wafer bonding method of one embodiment of the present disclosure includes the steps of providing two wafers. The method of fabricating each wafer includes forming a first dielectric layer on the substrate. A plurality of metal pads are mated on the first dielectric layer. Forming a plurality of first dielectric layers recessed in at least one of the wafers. These depressions are respectively between these metal pads. A second dielectric layer is formed on the first dielectric layer of the wafer having the recesses and overlying the recesses of the wafer and the metal pads. The two wafers are bonded such that the metal pads of the two wafers are in contact with each other, and the recesses of one of the wafers and the surface of the other wafer form a plurality of cavities, and the second dielectric layer is located in the cavities. The second dielectric layer is filled with mechanical cavities to fill the cavities. The two wafers are pressed together, and the second dielectric layer is cured, and the two wafers are fixed to each other.
本揭露之另一實施例所述的晶片接合方法,其步驟包含提供二晶片。每一晶片的製造方法包含形成第一介電層於基板上。嵌合多個金屬墊於第一介電層上,且每一金屬墊包含一基部及一凸出部。基部嵌合於第一介電層。凸出部連接於基部。形成第二介電層於第一介電層上。第二介電層覆蓋於這些基部,且這些凸出部貫穿第二介電層,並於凸出部之間構成多個凹陷。接合二晶片,令二晶片之這些金屬墊彼此接觸,以及令二晶片之這些凹陷構成多個空腔,且第二介電層位於這些空腔內。以機械驅動方式令第二介電層填滿這些空腔。壓合二晶片,並固化第二介電層,且令二晶片相互固定。 In a wafer bonding method according to another embodiment of the present disclosure, the method includes the steps of providing two wafers. The method of fabricating each wafer includes forming a first dielectric layer on the substrate. A plurality of metal pads are mated on the first dielectric layer, and each of the metal pads includes a base and a protrusion. The base is fitted to the first dielectric layer. The projection is connected to the base. A second dielectric layer is formed on the first dielectric layer. A second dielectric layer covers the bases, and the protrusions penetrate the second dielectric layer and form a plurality of recesses between the protrusions. The two wafers are bonded such that the metal pads of the two wafers are in contact with each other, and the recesses of the two wafers form a plurality of cavities, and the second dielectric layer is located in the cavities. The second dielectric layer is filled with mechanical cavities to fill the cavities. The two wafers are pressed together, and the second dielectric layer is cured, and the two wafers are fixed to each other.
本揭露之一實施例所述的晶片接合結構,包含二晶片及第二介電層。每一晶片包含基板、第一介電層及多個金屬墊。第一介電層置 於基板上。第一介電層具有一表面。這些金屬墊嵌設於第一介電層之表面。其中至少一晶片之第一介電層具有多個凹陷。這些凹陷位於表面且位於這些金屬墊之間。第二介電層置於二晶片之第一介電層之間,並覆蓋第一介電層之表面上與這些凹陷上。第二介電層具有相對的二接合面。第二介電層之二接合面分別和二第一介電層彼此相互接觸且相互黏著,以令二晶片相互固定,且其中一晶片之這些金屬墊與另一晶片之這些金屬墊接觸。 The wafer bonding structure of one embodiment of the present disclosure includes a second wafer and a second dielectric layer. Each wafer includes a substrate, a first dielectric layer, and a plurality of metal pads. First dielectric layer On the substrate. The first dielectric layer has a surface. These metal pads are embedded on the surface of the first dielectric layer. The first dielectric layer of at least one of the wafers has a plurality of recesses. These depressions are located on the surface and between these metal pads. A second dielectric layer is interposed between the first dielectric layers of the two wafers and overlies the surface of the first dielectric layer and the recesses. The second dielectric layer has opposing two bonding faces. The two bonding faces of the second dielectric layer and the two first dielectric layers are in contact with each other and adhere to each other to fix the two wafers to each other, and the metal pads of one of the wafers are in contact with the metal pads of the other wafer.
本揭露之另一實施例所述的晶片接合結構,包含二晶片。每一晶片包含基板、第一介電層、多個金屬墊及一第二介電層。第一介電層置於基板上。第一介電層具有表面。每一金屬墊包含基部及凸出部。這些基部嵌合於第一介電層。凸出部連接於基部,並凸出表面。第二介電層置於二晶片之第一介電層之間,並覆蓋二第一介電層之表面上與這些基部上。第二介電層具有相對的二接合面。第二介電層之二接合面分別和二第一介電層彼此相互接觸且相互黏著,以令二晶片相互固定,且其中一晶片之這些凸出部與另一晶片之這些凸出部接觸。 A wafer bonding structure according to another embodiment of the present disclosure includes two wafers. Each of the wafers includes a substrate, a first dielectric layer, a plurality of metal pads, and a second dielectric layer. The first dielectric layer is placed on the substrate. The first dielectric layer has a surface. Each metal pad includes a base and a protrusion. These bases are fitted to the first dielectric layer. The projection is attached to the base and protrudes from the surface. A second dielectric layer is disposed between the first dielectric layers of the two wafers and overlying the surfaces of the two first dielectric layers and the bases. The second dielectric layer has opposing two bonding faces. The two bonding faces of the second dielectric layer and the two first dielectric layers are in contact with each other and adhere to each other to fix the two wafers to each other, and wherein the protrusions of one of the wafers are in contact with the protrusions of the other wafer .
以上關於本揭露內容的說明及以下實施方式的說明係用以示範與解釋本揭露的原理,並且提供本揭露的專利申請範圍更進一步的解釋。 The above description of the disclosure and the following description of the embodiments are intended to illustrate and explain the principles of the disclosure, and to provide a further explanation of the scope of the disclosure.
5、5’、5”‧‧‧晶片接合結構 5, 5', 5" ‧ ‧ wafer bonding structure
10、10’‧‧‧晶片 10, 10'‧‧‧ wafer
20、20’‧‧‧空腔 20, 20’‧‧‧ cavity
100‧‧‧基板 100‧‧‧Substrate
200‧‧‧第一介電層 200‧‧‧First dielectric layer
210‧‧‧表面 210‧‧‧ surface
220‧‧‧凹陷 220‧‧‧ dent
300、300’‧‧‧金屬墊 300, 300’‧‧‧Metal pads
310‧‧‧基部 310‧‧‧ base
320‧‧‧凸出部 320‧‧‧protrusion
400‧‧‧第二介電層 400‧‧‧Second dielectric layer
410‧‧‧接合面 410‧‧‧ joint surface
第1圖為根據本揭露一實施例的晶片接合結構的剖面示意圖。 1 is a schematic cross-sectional view of a wafer bonding structure in accordance with an embodiment of the present disclosure.
第2A圖至第2E圖為第1圖之晶片接合結構的接合方法示意圖。 2A to 2E are schematic views showing a bonding method of the wafer bonding structure of Fig. 1.
第3A圖為根據本揭露另一實施例的晶片接合方法的其中一步驟的剖面 示意圖。 3A is a cross section of one step of a wafer bonding method according to another embodiment of the present disclosure. schematic diagram.
第3B圖為第3A圖之晶片接合結構的剖面示意圖。 Fig. 3B is a schematic cross-sectional view showing the wafer bonding structure of Fig. 3A.
第4圖為根據本揭露再一實施例的晶片接合方法的其中一步驟的剖面示意圖。 4 is a cross-sectional view showing one step of a wafer bonding method according to still another embodiment of the present disclosure.
第5圖為根據本揭露又一實施例的晶片接合結構的剖面示意圖。 FIG. 5 is a cross-sectional view of a wafer bonding structure according to still another embodiment of the present disclosure.
第6A圖至第6D圖為第5圖之晶片接合結構的接合方法示意圖。 6A to 6D are schematic views showing a bonding method of the wafer bonding structure of Fig. 5.
第7圖為根據本揭露再一實施例的晶片接合結構的剖面示意圖。 Figure 7 is a cross-sectional view showing a wafer bonding structure according to still another embodiment of the present disclosure.
請參照第1圖至第2E圖。第1圖為根據本揭露一實施例的晶片接合結構的剖面示意圖。第2A圖至第2E圖為第1圖之晶片接合結構的接合方法示意圖。 Please refer to Figures 1 to 2E. 1 is a schematic cross-sectional view of a wafer bonding structure in accordance with an embodiment of the present disclosure. 2A to 2E are schematic views showing a bonding method of the wafer bonding structure of Fig. 1.
本實施例之晶片接合方法的步驟如下:提供二晶片10,每一晶片10的製造方法如下:如第2A圖所示,形成一第一介電層200於一基板100上。其中,形成第一介電層200的方法包含化學氣相沉積(chemical vapor deposition,CVD)、印刷(print)或旋塗(spin on)等。第一介電層200的材料為二氧化矽(SiO2)、氮化矽(SiN)或低介電材料(Low-K material),亦可為多層介電材料之結合。第一介電層200具有一表面210。接著,嵌合多個金屬墊300於第一介電層200上。金屬墊300的材料可包含銅、鋁、鎢等導電材料或其組合。 The steps of the wafer bonding method of this embodiment are as follows: Two wafers 10 are provided, and each wafer 10 is manufactured as follows: As shown in FIG. 2A, a first dielectric layer 200 is formed on a substrate 100. The method of forming the first dielectric layer 200 includes chemical vapor deposition (CVD), printing, or spin on. The material of the first dielectric layer 200 is ceria (SiO 2 ), tantalum nitride (SiN) or low dielectric material (Low-K material), and may also be a combination of multilayer dielectric materials. The first dielectric layer 200 has a surface 210. Next, a plurality of metal pads 300 are fitted on the first dielectric layer 200. The material of the metal pad 300 may comprise a conductive material such as copper, aluminum, tungsten or the like or a combination thereof.
如第2B圖所示,於第一介電層表面210上形成多個凹陷220。這些凹陷220分別介於這些金屬墊300之間。其中,形成多個凹陷220 的方法可選自例如由研磨、蝕刻回蝕、濕蝕刻或選擇性蝕刻所構成之群組的其中之一及其組合。 As shown in FIG. 2B, a plurality of recesses 220 are formed on the first dielectric layer surface 210. These recesses 220 are interposed between these metal pads 300, respectively. Wherein, forming a plurality of recesses 220 The method can be selected from one of the group consisting of, for example, grinding, etching etch back, wet etching, or selective etching, and combinations thereof.
如第2C圖所示,形成一第二介電層400於其中一晶片10之上,且第二介電層400覆蓋於這些凹陷220上及這些金屬墊300上。其中,形成第二介電層400的方法例如為化學氣相沉積、旋塗或印刷。第二介電層400的材料例如為液態二氧化矽(SOG)、苯環丁烯(Benzocyclobutene,BCB)或氧化鉛(PBO),但本揭露並不以此為限。 As shown in FIG. 2C, a second dielectric layer 400 is formed over one of the wafers 10, and the second dielectric layer 400 covers the recesses 220 and the metal pads 300. The method of forming the second dielectric layer 400 is, for example, chemical vapor deposition, spin coating or printing. The material of the second dielectric layer 400 is, for example, liquid cerium oxide (SOG), benzocyclobutene (BCB) or lead oxide (PBO), but the disclosure is not limited thereto.
如第2D圖所示,接合二晶片10,第二介電層400具有相對的二接合面410。二接合面410分別與二晶片10之第一介電層接觸,以令二晶片10之這些金屬墊300彼此接觸,以及令二晶片10之這些凹陷220構成多個空腔20,且第二介電層400位於這些空腔20內。 As shown in FIG. 2D, the two wafers 10 are bonded, and the second dielectric layer 400 has opposing two bonding faces 410. The two bonding faces 410 are respectively in contact with the first dielectric layer of the two wafers 10 such that the metal pads 300 of the two wafers 10 are in contact with each other, and the recesses 220 of the two wafers 10 constitute a plurality of cavities 20, and the second dielectric layer Electrical layer 400 is located within these cavities 20.
值得注意的是,本實施例中,二晶片10之第一介電層上皆具有多個凹陷220,但並不以此為限,在其他實施例中,上述之這些凹陷220可僅形成於其中一晶片10上,使得其中一晶片上之各凹陷220與另一晶片之表面210構成多個空腔20。 It should be noted that, in this embodiment, the first dielectric layer of the two wafers 10 has a plurality of recesses 220, but is not limited thereto. In other embodiments, the recesses 220 may be formed only in the other embodiments. On one of the wafers 10, the recesses 220 on one of the wafers and the surface 210 of the other wafer form a plurality of cavities 20.
如第2E圖所示,以機械驅動方式令位於這些空腔20內之第二介電層400填滿這些空腔20。其中,機械驅動方式可例如為旋轉、翻轉或震盪,而本實施例係採用翻轉(沿箭頭a所指示的方向)。在一實施例中,機械驅動方式令位於這些空腔20內之第二介電層400填滿這些空腔20的操作環境可為一真空環境。 As shown in FIG. 2E, the second dielectric layer 400 located in the cavities 20 is filled with mechanical cavities to fill the cavities 20. Wherein, the mechanical driving mode can be, for example, rotating, flipping or oscillating, and the embodiment adopts flipping (in the direction indicated by the arrow a). In one embodiment, the mechanically driven manner allows the second dielectric layer 400 located within the cavities 20 to fill the cavity 20 in an operating environment that can be a vacuum environment.
壓合二晶片10(施加壓合外力F),並固化第二介電層400,以令第二介電層400塞滿這些空腔20,使得二晶片10可相互固定。其中, 固化第二介電層400的方法例如是對二晶片10加溫。於一實施例中,在晶片10固化前,空腔20內可能存在空隙,在晶片10加溫的過程中,金屬墊300會發生熔融現象,使得二晶片10彼此更靠近而縮小空腔20的體積,而第二介電層400的體積藉由固化膨脹而塞滿這些空腔20。於另一實施例中,在晶片10固化前,空腔20內之第二介電層400在經過機械驅動方式後,因表面張力或毛細現象而充滿於空腔20之內,接著在晶片10加溫過程中,第二介電層400被固化。如此一來,則能夠藉由第二介電層400來增加二晶片10的接合度(密合度),進而提升二晶片10的接合良率。 The two wafers 10 are pressed (the pressing force F is applied), and the second dielectric layer 400 is cured to fill the cavity 20 with the second dielectric layer 400 so that the two wafers 10 can be fixed to each other. among them, The method of curing the second dielectric layer 400 is, for example, heating the two wafers 10. In an embodiment, a gap may exist in the cavity 20 before the wafer 10 is cured. During the heating of the wafer 10, the metal pad 300 may be melted, so that the two wafers 10 are closer to each other and the cavity 20 is narrowed. The volume, while the volume of the second dielectric layer 400 fills the cavities 20 by curing expansion. In another embodiment, before the wafer 10 is cured, the second dielectric layer 400 in the cavity 20 is filled in the cavity 20 due to surface tension or capillary phenomenon after mechanically driving, and then on the wafer 10. During the heating process, the second dielectric layer 400 is cured. As a result, the bonding degree (adhesion) of the two wafers 10 can be increased by the second dielectric layer 400, thereby improving the bonding yield of the two wafers 10.
如第1圖所示,由上述晶片接合方法形成之晶片接合結構5包含二晶片10,每一晶片10包含一基板100、一第一介電層200、多個金屬墊300及至少一晶片之一第二介電層400。 As shown in FIG. 1, the wafer bonding structure 5 formed by the above wafer bonding method includes two wafers 10, each of which includes a substrate 100, a first dielectric layer 200, a plurality of metal pads 300, and at least one wafer. A second dielectric layer 400.
第一介電層200配置於基板100。如圖2B所示,這些第一介電層200具有一表面210及多個凹陷220。這些凹陷220位於表面210。其中一晶片10之凹陷220與另一晶片10之凹陷220間的間距介於1至2微米。在本實施例中,凹陷220之表面為一曲面。 The first dielectric layer 200 is disposed on the substrate 100. As shown in FIG. 2B, the first dielectric layer 200 has a surface 210 and a plurality of recesses 220. These recesses 220 are located on the surface 210. The spacing between the recess 220 of one of the wafers 10 and the recess 220 of the other wafer 10 is between 1 and 2 microns. In the present embodiment, the surface of the recess 220 is a curved surface.
這些金屬墊300嵌設於第一介電層200之表面210,且這些凹陷220位於這些金屬墊300之間,凹陷220之邊緣可例如是接觸相對兩側之二金屬墊300。 The metal pads 300 are embedded in the surface 210 of the first dielectric layer 200, and the recesses 220 are located between the metal pads 300. The edges of the recesses 220 may be, for example, two metal pads 300 contacting the opposite sides.
在本實施例中,第二介電層400配置於第一介電層200之表面210上與這些凹陷220上。第二介電層400具有一接合面410。接合面410位於第二介電層400相對遠離第一介電層200之一側。其中,二晶片10之第二介電層400的二接合面410彼此相互接觸且相互黏著,以令二晶片10 相互固定,且其中一晶片10之這些金屬墊300與另一晶片10之這些金屬墊300電性接觸。 In the embodiment, the second dielectric layer 400 is disposed on the surface 210 of the first dielectric layer 200 and the recesses 220. The second dielectric layer 400 has a bonding surface 410. The bonding surface 410 is located on a side of the second dielectric layer 400 that is relatively far from the first dielectric layer 200. The two bonding surfaces 410 of the second dielectric layer 400 of the two wafers 10 are in contact with each other and adhere to each other to make the two wafers 10 The metal pads 300 of one of the wafers 10 are electrically connected to the metal pads 300 of the other wafer 10.
請參閱第3A圖與第3B圖,第3A圖為根據本揭露另一實施例的晶片接合方法的其中一步驟的剖面示意圖。第3B圖為第3A圖之晶片接合結構的剖面示意圖。 Please refer to FIGS. 3A and 3B. FIG. 3A is a schematic cross-sectional view showing one step of the wafer bonding method according to another embodiment of the present disclosure. Fig. 3B is a schematic cross-sectional view showing the wafer bonding structure of Fig. 3A.
為了讓二晶片10之各金屬墊300具有更佳的電性接觸效果,本實施例於形成第二介電層400於第一介電層200上的步驟後,去除接觸於金屬墊300之第二介電層400(如第3A圖所示),以令其中一晶片10之各金屬墊300能夠分別與另一晶片10之各金屬墊300直接接觸(如第3B圖所示),進而提升二晶片10之電性接觸效果。 In order to make the metal pads 300 of the two wafers 10 have better electrical contact effects, the first embodiment removes the contact with the metal pads 300 after the step of forming the second dielectric layer 400 on the first dielectric layer 200. The two dielectric layers 400 (shown in FIG. 3A) are such that the metal pads 300 of one of the wafers 10 can be in direct contact with the metal pads 300 of the other wafer 10 (as shown in FIG. 3B), thereby enhancing The electrical contact effect of the two wafers 10.
請參閱第4圖,第4圖為根據本揭露再一實施例的晶片接合方法的其中一步驟的剖面示意圖。 Please refer to FIG. 4, which is a cross-sectional view showing a step of the wafer bonding method according to still another embodiment of the present disclosure.
若於第一介電層200上形成多個凹陷220後,仍覺得凹陷220深度不足時可再進行一次蝕刻,以加深凹陷220的深度,進而讓凹陷220可容納更大量的第二介電層400。 If a plurality of recesses 220 are formed on the first dielectric layer 200, it is still considered that the recess 220 may be further etched when the depth is insufficient to deepen the depth of the recess 220, thereby allowing the recess 220 to accommodate a larger amount of the second dielectric layer. 400.
上述晶片10之金屬墊300之頂面係與第一介電層200之表面210共平面,但並不以此為限。在其他實施例中,金屬墊300也可以凸出第一介電層200之表面210。 The top surface of the metal pad 300 of the wafer 10 is coplanar with the surface 210 of the first dielectric layer 200, but is not limited thereto. In other embodiments, the metal pad 300 may also protrude from the surface 210 of the first dielectric layer 200.
請參閱第5圖至第6D圖。第5圖為根據本揭露又一實施例的晶片接合結構的剖面示意圖。第6A圖至第6D圖為第5圖之晶片接合結構的接合方法示意圖。 Please refer to Figures 5 to 6D. FIG. 5 is a cross-sectional view of a wafer bonding structure according to still another embodiment of the present disclosure. 6A to 6D are schematic views showing a bonding method of the wafer bonding structure of Fig. 5.
本實施例之晶片接合方法的步驟如下: 提供二晶片10’,每一晶片10’的製造方法如下:如第6A圖所示,形成一第一介電層200於一基板100上。其中,形成第一介電層200的方法包含化學氣相沉積、印刷或旋塗等。第一介電層200的材料為二氧化矽(SiO2)、氮化矽(SiN)或低介電材料(Low-K material),亦可為多層介電材料之結合。接著,嵌合多個金屬墊300’於第一介電層200上。每一金屬墊300’包含一基部310及一凸出部320。基部310嵌合於第一介電層200。凸出部320連接於基部310。金屬墊300’的材料可包含銅、鋁、鎢等導電材料或其組合。值得注意的是,凸出部320與基部310可為相同或不同的導電材料。 The steps of the wafer bonding method of this embodiment are as follows: Two wafers 10' are provided, and each wafer 10' is manufactured as follows: As shown in FIG. 6A, a first dielectric layer 200 is formed on a substrate 100. Among them, the method of forming the first dielectric layer 200 includes chemical vapor deposition, printing or spin coating, and the like. The material of the first dielectric layer 200 is ceria (SiO 2 ), tantalum nitride (SiN) or low dielectric material (Low-K material), and may also be a combination of multilayer dielectric materials. Next, a plurality of metal pads 300' are fitted on the first dielectric layer 200. Each metal pad 300 ′ includes a base portion 310 and a protrusion portion 320 . The base 310 is fitted to the first dielectric layer 200. The projection 320 is coupled to the base 310. The material of the metal pad 300' may comprise a conductive material such as copper, aluminum, tungsten or the like or a combination thereof. It should be noted that the protrusion 320 and the base 310 may be the same or different conductive materials.
如第6B圖所示,形成一第二介電層400於第一介電層200上。第二介電層400覆蓋於這些金屬墊300’之基部310上,且第二介電層400的高度接近或等於凸出部320凸出第一介電層200的高度。本實施例之第二介電層400的高度為略小於金屬墊300’之凸出部320凸出第一介電層200的高度。也就是說,這些金屬墊300’之凸出部320貫穿第二介電層400。其中,形成第二介電層400的方法例如為化學氣相沉積、旋塗或印刷。第二介電層400的材料為液態二氧化矽(SOG)、苯環丁烯(Benzocyclobutene,BCB)或氧化鉛(PBO)等。 As shown in FIG. 6B, a second dielectric layer 400 is formed on the first dielectric layer 200. The second dielectric layer 400 covers the base portion 310 of the metal pads 300', and the height of the second dielectric layer 400 is close to or equal to the height of the protruding portion 320 protruding from the first dielectric layer 200. The height of the second dielectric layer 400 of the present embodiment is slightly smaller than the height of the protruding portion 320 of the metal pad 300' protruding from the first dielectric layer 200. That is, the projections 320 of the metal pads 300' penetrate the second dielectric layer 400. The method of forming the second dielectric layer 400 is, for example, chemical vapor deposition, spin coating or printing. The material of the second dielectric layer 400 is liquid cerium oxide (SOG), benzocyclobutene (BCB) or lead oxide (PBO).
如第6C圖所示,接合二晶片10’,令二晶片10’之這些金屬墊300’之凸出部320彼此接觸,以及令二晶片10’之這些金屬墊300’間構成多個空腔20’,且二晶片10’之第二介電層400位於這些空腔20’內。 As shown in FIG. 6C, the two wafers 10' are bonded such that the projections 320 of the metal pads 300' of the two wafers 10' are in contact with each other, and the plurality of cavities are formed between the metal pads 300' of the two wafers 10'. 20', and the second dielectric layer 400 of the two wafers 10' is located within the cavities 20'.
本實施例之二凸出部320係凸出於第二介電層400之接合面 410,故於接合二晶片10’前無需再多一去除覆蓋於金屬墊300’上之第二介電層400的步驟,即可確保二晶片10’間具有良好的電性接觸效果。 The two protrusions 320 of the embodiment protrude from the joint surface of the second dielectric layer 400. 410, so that there is no need to remove the second dielectric layer 400 over the metal pad 300' before bonding the two wafers 10', so that a good electrical contact effect between the two wafers 10' can be ensured.
如第6D圖所示,以機械驅動方式令第二介電層400填滿這些空腔20’。其中,機械驅動方式可例如為旋轉、翻轉或震盪,而本實施例係採用翻轉(沿箭頭a所指示的方向)。在一實施例中,機械驅動方式令位於這些空腔20’內之二第二介電層400填滿這些空腔20’的操作環境可為一真空環境。 As shown in Fig. 6D, the second dielectric layer 400 is filled with the cavities 20' by mechanical driving. Wherein, the mechanical driving mode can be, for example, rotating, flipping or oscillating, and the embodiment adopts flipping (in the direction indicated by the arrow a). In one embodiment, the mechanically driven manner allows the operating environment of the second dielectric layer 400 located within the cavities 20' to fill the cavities 20' to be a vacuum environment.
壓合二晶片10(施加壓合外力F),並固化二第二介電層400,以令第二介電層400塞滿這些空腔20’,使得二晶片10’可相互固定。其中,固化二第二介電層400的方法例如是對二晶片10’加溫。於一實施例中,在晶片10’固化前,空腔20’內可能存在空隙,在晶片10’加溫的過程中,金屬墊300’會發生熔融現象,使得二晶片10’彼此更靠近而縮小空腔20’的體積,而第二介電層400的體積藉由固化膨脹而塞滿這些空腔20’。如此一來,則能夠藉由第二介電層400來增加二晶片10’的接合度(密合度),進而提升二晶片10’的接合良率。 The two wafers 10 are pressed (the pressing force F is applied), and the second dielectric layers 400 are cured to fill the cavities 20' with the second dielectric layer 400 so that the two wafers 10' can be fixed to each other. Among them, the method of curing the second dielectric layer 400 is, for example, heating the two wafers 10'. In one embodiment, there may be voids in the cavity 20' before the wafer 10' is cured. During the heating of the wafer 10', the metal pad 300' may melt, causing the two wafers 10' to be closer to each other. The volume of the cavity 20' is reduced, and the volume of the second dielectric layer 400 is filled with these cavities 20' by curing expansion. As a result, the bonding degree (adhesion) of the two wafers 10' can be increased by the second dielectric layer 400, thereby improving the bonding yield of the two wafers 10'.
如第5圖所示,由上述晶片接合方法形成之晶片接合結構5’包含二晶片10’,每一晶片10’包含一基板100、一第一介電層200、多個金屬墊300’及一第二介電層400。 As shown in FIG. 5, the wafer bonding structure 5' formed by the above wafer bonding method includes two wafers 10'. Each wafer 10' includes a substrate 100, a first dielectric layer 200, and a plurality of metal pads 300'. A second dielectric layer 400.
第一介電層200配置於基板100。這些第一介電層200具有一表面210。 The first dielectric layer 200 is disposed on the substrate 100. These first dielectric layers 200 have a surface 210.
這些金屬墊300’嵌設於第一介電層200之表面210。每一金屬墊300’包含一基部310及一凸出部320。基部310嵌合於第一介電層 200。凸出部320連接於基部310,並凸出於第一介電層200。二晶片10’之表面的間距介於1至10微米。 These metal pads 300' are embedded in the surface 210 of the first dielectric layer 200. Each metal pad 300' includes a base portion 310 and a projection portion 320. The base 310 is fitted to the first dielectric layer 200. The protrusion 320 is connected to the base 310 and protrudes from the first dielectric layer 200. The surface of the two wafers 10' has a pitch of from 1 to 10 μm.
在本實施例中,第二介電層400配置於第一介電層200之表面210上與這些金屬墊300’之基部310上,且這些凸出部320可貫穿第二介電層400。第二介電層400具有一接合面410。接合面410位於第二介電層400相對遠離第一介電層200之一側。其中,二晶片10’之二第二介電層400的二接合面410彼此相互接觸且相互黏著,以令二晶片10’相互固定,且其中一晶片10’之這些金屬墊300與另一晶片10’之這些金屬墊300’電性接觸。 In this embodiment, the second dielectric layer 400 is disposed on the surface 210 of the first dielectric layer 200 and the base portion 310 of the metal pads 300', and the protrusions 320 may penetrate the second dielectric layer 400. The second dielectric layer 400 has a bonding surface 410. The bonding surface 410 is located on a side of the second dielectric layer 400 that is relatively far from the first dielectric layer 200. The two bonding surfaces 410 of the second dielectric layer 400 of the two wafers 10' are in contact with each other and adhere to each other, so that the two wafers 10' are fixed to each other, and the metal pads 300 of one wafer 10' and another wafer are These metal pads 300' of 10' are in electrical contact.
上述晶片接合結構5、5’為對稱式結構(將二相同結構之晶片10對接或將二相同結構之晶片10’對接),但並不以此為限,在其他實施例中,晶片接合結構5、5’也可以為非對稱式結構。請參閱第7圖。第7圖為根據本揭露再一實施例的晶片接合結構的剖面示意圖。本實施例之晶片接合結構5”係將相異結構之二晶片10、10’對接,詳細來說,本實施例其中一晶片10之結構同上述第1圖之晶片10,另一晶片10’之結構同上述第5圖之晶片10’。 The wafer bonding structure 5, 5' is a symmetric structure (butting the wafers 10 of the same structure or docking the wafers 10 of the same structure), but not limited thereto. In other embodiments, the wafer bonding structure 5, 5' can also be an asymmetric structure. Please refer to Figure 7. Figure 7 is a cross-sectional view showing a wafer bonding structure according to still another embodiment of the present disclosure. The wafer bonding structure 5" of the present embodiment is abutting the two wafers 10, 10' of the different structures. In detail, in the embodiment, one wafer 10 has the same structure as the wafer 10 of the first drawing, and the other wafer 10' The structure is the same as the wafer 10' of the above fifth drawing.
根據上述本揭露一實施例所述的晶片接合結構及其接合方法,將第二介電層容置於各介電層之間的各凹陷中,而於晶片加溫的過程(固化)中,金屬墊會發生熔融現象,使得二晶片彼此更靠近而縮小空腔的體積,而第二介電層的體積會膨脹而塞滿這些空腔,或者,在晶片固化前,凹陷內之第二介電層在經過機械驅動方式後,因表面張力或毛細現象而充滿於凹陷之內,接著第二介電層在晶片加溫過程中被固化。如此一來,則能夠 藉由第二介電層來增加二晶片的接合度(密合度),進而提升二晶片的接合良率。 According to the wafer bonding structure and the bonding method thereof according to the embodiment of the present disclosure, the second dielectric layer is accommodated in each of the recesses between the dielectric layers, and in the process of curing the wafer (curing), The metal pad may melt, causing the two wafers to be closer to each other to reduce the volume of the cavity, and the volume of the second dielectric layer may expand to fill the cavity, or the second dielectric in the recess before the wafer is cured After mechanically driving, the electrical layer is filled with recesses due to surface tension or capillary phenomena, and then the second dielectric layer is cured during wafer warming. In this way, you can The bonding degree (adhesion) of the two wafers is increased by the second dielectric layer, thereby improving the bonding yield of the two wafers.
雖然本揭露的實施例揭露如上所述,然並非用以限定本揭露,任何熟習相關技藝者,在不脫離本揭露的精神和範圍內,舉凡依本揭露申請範圍所述的形狀、構造、特徵及數量當可做些許的變更,因此本揭露的專利保護範圍須視本說明書所附的申請專利範圍所界定者為準。 While the embodiments of the present disclosure are disclosed as described above, it is not intended to limit the scope of the present disclosure, and the scope, structure, and features described in the scope of the application of the present disclosure, without departing from the spirit and scope of the disclosure. And the number of modifications may be made, and the scope of patent protection of this disclosure is subject to the scope of the patent application attached to this specification.
5‧‧‧晶片接合結構 5‧‧‧ wafer bonding structure
10‧‧‧晶片 10‧‧‧ wafer
100‧‧‧基板 100‧‧‧Substrate
200‧‧‧第一介電層 200‧‧‧First dielectric layer
300‧‧‧金屬墊 300‧‧‧Metal pad
400‧‧‧第二介電層 400‧‧‧Second dielectric layer
410‧‧‧接合面 410‧‧‧ joint surface
Claims (26)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103101443A TWI534973B (en) | 2014-01-15 | 2014-01-15 | Chip bonding structure and bonding method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW103101443A TWI534973B (en) | 2014-01-15 | 2014-01-15 | Chip bonding structure and bonding method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201528463A TW201528463A (en) | 2015-07-16 |
TWI534973B true TWI534973B (en) | 2016-05-21 |
Family
ID=54198396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103101443A TWI534973B (en) | 2014-01-15 | 2014-01-15 | Chip bonding structure and bonding method thereof |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI534973B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10381322B1 (en) * | 2018-04-23 | 2019-08-13 | Sandisk Technologies Llc | Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same |
-
2014
- 2014-01-15 TW TW103101443A patent/TWI534973B/en active
Also Published As
Publication number | Publication date |
---|---|
TW201528463A (en) | 2015-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5183708B2 (en) | Semiconductor device and manufacturing method thereof | |
TWI698925B (en) | Stacked dies and methods for forming bonded structures | |
JP3646720B2 (en) | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus | |
TWI433244B (en) | Method of fabricating integrated circuit device with three-dimensional stacked structure | |
JP4694305B2 (en) | Manufacturing method of semiconductor wafer | |
CN100517623C (en) | Wafer press welding and bonding method and structure thereof | |
JP5663607B2 (en) | Semiconductor device | |
JP2015115446A (en) | Semiconductor device manufacturing method | |
JP2009181981A (en) | Manufacturing process of semiconductor device, and the semiconductor device | |
JP5797873B2 (en) | Integrated circuit having bond pads with improved thermal and mechanical properties | |
JP2012501077A (en) | A semiconductor device including a stress relaxation gap to enhance chip-package interaction stability. | |
JP6017297B2 (en) | Manufacturing method of semiconductor device | |
JP3673094B2 (en) | Multi-chip semiconductor device | |
JP2016021497A (en) | Semiconductor device and manufacturing method for the same | |
JP2014103395A (en) | Electrical coupling method between wafers using batting contact system and semiconductor device achieved by using the same | |
TW202137423A (en) | Power module having interconnected base plate with molded metal and method of making the same | |
JP4147433B2 (en) | Semiconductor device and manufacturing method thereof | |
TWI534973B (en) | Chip bonding structure and bonding method thereof | |
CN112397394B (en) | Semiconductor structure and manufacturing method thereof | |
CN110517992B (en) | Fan-out chip packaging structure and packaging method | |
JP2013214558A (en) | Wiring board and manufacturing method of the same, and semiconductor device and manufacturing method of the same | |
US8389404B2 (en) | Semiconductor device and method for manufacturing the same | |
JP6473897B2 (en) | Manufacturing method of semiconductor device | |
JP2009111063A (en) | Through-hole electrode forming method, and semiconductor chip | |
JPH11111761A (en) | Packaged semiconductor chip parts |