TWI533116B - Power saving circuit - Google Patents

Power saving circuit Download PDF

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TWI533116B
TWI533116B TW104103803A TW104103803A TWI533116B TW I533116 B TWI533116 B TW I533116B TW 104103803 A TW104103803 A TW 104103803A TW 104103803 A TW104103803 A TW 104103803A TW I533116 B TWI533116 B TW I533116B
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variable resistor
switch
power
processing module
nmos transistor
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TW104103803A
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Chinese (zh)
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TW201629683A (en
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林昇源
范多蘄
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正崴精密工業股份有限公司
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Description

省電電路 Power saving circuit

本發明涉及一種省電電路,更具體的是涉及一種透過壓力感測功能實現減少電源消耗的省電電路及其電子設備。 The invention relates to a power saving circuit, and more particularly to a power saving circuit and an electronic device thereof for reducing power consumption through a pressure sensing function.

隨著物連網時代的來臨,各公司紛紛推出許多種類的穿戴式裝置或是手持式裝置,藉當中的各種功能來提升使用者的日常體驗,使得這些終端電子裝置的數量正快速的在全球增長。 With the advent of the Internet of Things era, companies have introduced many types of wearable devices or handheld devices, which use various functions to enhance the user's daily experience, making the number of these terminal electronic devices fast and global. increase.

這些物連網終端電子裝置因可攜性的緣故大多皆是採用電池作為電力,因此,隨著使用者的隨身設備數量增多,每樣終端電子裝置充電的需求會造成使用者的困擾,因此如何延長終端電子裝置的待機時間,藉以提供使用者更好的使用者體驗,成了各公司在產品開發時的重要考量,尤其使用者也已開始注意到這個問題,使得待機時間更長的終端電子裝置在市場上更受歡迎。 Most of these networked terminal electronic devices use batteries as power for the sake of portability. Therefore, as the number of portable devices of users increases, the demand for charging each terminal electronic device may cause user confusion, so how to Extending the standby time of the terminal electronic device to provide a better user experience for the user has become an important consideration for the company during product development. In particular, the user has begun to notice this problem, making the terminal electronic device with longer standby time. Devices are more popular on the market.

一般的終端電子裝置在關機的狀態下,因開關單元未被開啟,因此開關為斷路時,電子裝置電路判讀為進入休眠模式,使電子裝置電路在消耗最小的電源狀態下待命,待開關導通電流後電子裝置電路在控制進入工作狀態。 In the state where the general terminal electronic device is turned off, since the switch unit is not turned on, when the switch is open, the electronic device circuit is judged to enter the sleep mode, so that the electronic device circuit is standby in the power state with the least consumption, and the on-current is to be switched. The rear electronic device circuit enters the working state after the control.

然,一般的終端電子裝置的電子裝置電路在休眠狀態仍會消耗少量的電力,因此為了使終端電子裝置具有更長的待機時間,有必 要提出一種使電子裝置電路在關機時不會消耗電源的省電電路。 However, the electronic device circuit of a general terminal electronic device still consumes a small amount of power in a sleep state, so in order to make the terminal electronic device have a longer standby time, it is necessary A power saving circuit that does not consume power when the electronic device circuit is turned off is proposed.

如一種已知的藍芽觸控筆,該藍芽觸控筆上具有一電源按鈕,當使用者開啟電源按鈕後,藍芽觸控筆的電子裝置電路由休眠模式進入工作狀態。由於藍芽觸控筆屬於低耗電量產品,若能節省下休眠模式消耗的電量,將能夠大幅提高使用時間以及待機時間。 For example, in a known Bluetooth stylus, the Bluetooth stylus has a power button. When the user turns on the power button, the electronic device circuit of the Bluetooth stylus enters the working state from the sleep mode. Since the Bluetooth stylus is a low-power product, if you can save the power consumed by the sleep mode, you will be able to greatly increase the usage time and standby time.

本發明之目的係針對上述習知的不足而提供一種省電電路,為了使電子裝置電路在關機的狀態下不會消耗電源。 SUMMARY OF THE INVENTION The object of the present invention is to provide a power saving circuit for the above-mentioned deficiencies, in order to prevent the electronic device circuit from consuming power in a shutdown state.

為達成所述目的,本發明公開一種省電電路,連接一電源,其包括一可變電阻、一開關及一處理模組,電源分別連接於開關及可變電阻,處理模組分別連接於開關及可變電阻,開關連接可變電阻。開關被設置成當可變電阻受到壓力後導通電源及處理模組之間的線路。處理模組被設置成在接收到電源後提供開關一工作訊號使開關在可變電阻未受到壓力時持續導通電源至處理模組之間的線路。或是,處理模組被設置成偵測可變電阻的電壓,以關閉工作訊號時,開關使電源至處理模組的線路斷路。 To achieve the above object, the present invention discloses a power saving circuit, which is connected to a power supply, and includes a variable resistor, a switch and a processing module. The power source is respectively connected to the switch and the variable resistor, and the processing module is respectively connected to the switch. And a variable resistor, the switch is connected to the variable resistor. The switch is arranged to turn on the line between the power supply and the processing module when the variable resistor is subjected to pressure. The processing module is configured to provide a switch-operating signal upon receipt of the power source to cause the switch to continuously conduct power to the circuit between the processing modules when the variable resistor is not under pressure. Alternatively, the processing module is configured to detect the voltage of the variable resistor to turn off the working signal, and the switch disconnects the line from the power supply to the processing module.

所述可變電阻可為壓力感測器。 The variable resistor can be a pressure sensor.

所述可變電阻包括一第一端及一第二端,開關包括一PMOS電晶體及一NMOS電晶體,處理模組包括一電源腳、發送工作訊號的一訊號腳及一偵測可變電阻電壓的電壓腳,電源的正極分別連接PMOS電晶體的源極及可變電阻的第一端,第二端連接NMOS電晶體的閘極,第二端與NMOS電晶體的閘極之間的線路經過一電阻接地,第二端與NMOS電晶體的閘極之間的線路 連接至電壓腳,NMOS電晶體的源極接地,NMOS電晶體的汲極連接PMOS電晶體的閘極,PMOS電晶體的汲極連接電源腳,電源的正極與PMOS電晶體的源極之間的線路經過一電阻與PMOS電晶體的閘極及NMOS電晶體的汲極之間的線路形成節點接著連接至訊號腳。 The variable resistor includes a first end and a second end. The switch includes a PMOS transistor and an NMOS transistor. The processing module includes a power pin, a signal pin for transmitting a working signal, and a detecting variable resistor. The voltage of the voltage, the positive pole of the power supply is respectively connected to the source of the PMOS transistor and the first end of the variable resistor, the second end is connected to the gate of the NMOS transistor, and the line between the second end and the gate of the NMOS transistor After a resistor is grounded, the line between the second end and the gate of the NMOS transistor Connected to the voltage pin, the source of the NMOS transistor is grounded, the drain of the NMOS transistor is connected to the gate of the PMOS transistor, the drain of the PMOS transistor is connected to the power supply pin, and the anode of the power supply is connected to the source of the PMOS transistor. The line is connected to the signal pin via a resistor forming a node between the gate of the PMOS transistor and the drain of the NMOS transistor.

所述第二端與NMOS電晶體的閘極之間的線路串聯一反向迴路放大器後連接電壓腳。 The circuit between the second end and the gate of the NMOS transistor is connected in series with a reverse loop amplifier and connected to the voltage pin.

一種電子設備,其包括一殼體,具有一預設觸碰區。一本發明的省電電路,位於殼體內。及一由省電電路供電的電子裝置電路,設置於殼體內。其中,可變電阻被設置成使用者碰觸預設觸碰區時受感應,且電子裝置電路根據省電電路所偵測之可變電阻電壓進而控制電子設備。 An electronic device includes a housing having a predetermined touch area. A power saving circuit of the invention is located within the housing. And an electronic device circuit powered by the power saving circuit is disposed in the housing. The variable resistor is configured to be sensed when the user touches the preset touch area, and the electronic device circuit controls the electronic device according to the variable resistance voltage detected by the power saving circuit.

所述電子設備還包括一連接電子裝置電路的無線模組。 The electronic device further includes a wireless module that connects the electronic device circuits.

所述電子設備為一觸控筆,所述殼體為一筆桿,可變電阻連接於筆桿之一端的觸控筆尖。 The electronic device is a stylus, the housing is a pen, and the variable resistor is connected to the stylus tip of one end of the pen.

所述電子設備還包括一連接電子裝置電路的無線模組。 The electronic device further includes a wireless module that connects the electronic device circuits.

本發明的省電電路具備下列優點: The power saving circuit of the present invention has the following advantages:

一、本發明的省電電路提高電子設備的待機時間。 1. The power saving circuit of the present invention increases the standby time of the electronic device.

二、本發明的省電電路使可變電阻除了可以用來感測壓力,還能做為電子設備的開關,使開關在電子設備上解放開來,並且藉此節省製造時間與經費。 2. The power-saving circuit of the present invention allows the variable resistor to be used as a switch for an electronic device in addition to sensing pressure, thereby freeing the switch from the electronic device and thereby saving manufacturing time and expense.

三、本發明的省電電路應用於觸控筆時,觸控筆使用方式與 一般書寫筆一樣直覺,隨取隨用,不需要有另外的動作打開電源,藉以提升使用者的日常體驗。 3. When the power saving circuit of the present invention is applied to a stylus, the stylus is used and Generally, the writing pen is as intuitive as it is, and it does not need to have another action to turn on the power, so as to enhance the user's daily experience.

四、由於本發明的電子設備及觸控筆外表面上不需要設置開關,因此可以使得外觀設計更不受限制。 Fourth, since the electronic device of the present invention and the outer surface of the stylus do not need to be provided with switches, the design can be made more unrestricted.

1‧‧‧省電電路 1‧‧‧Power saving circuit

10‧‧‧可變電阻 10‧‧‧Variable resistor

100‧‧‧第一端 100‧‧‧ first end

101‧‧‧第二端 101‧‧‧ second end

102‧‧‧反向迴路放大器 102‧‧‧Reverse loop amplifier

11‧‧‧電子裝置電路 11‧‧‧Electronic device circuit

12‧‧‧電源 12‧‧‧Power supply

13‧‧‧開關 13‧‧‧ switch

130‧‧‧PMOS電晶體 130‧‧‧PMOS transistor

131‧‧‧NMOS電晶體 131‧‧‧NMOS transistor

14‧‧‧處理模組 14‧‧‧Processing module

140‧‧‧電源腳 140‧‧‧Power foot

141‧‧‧訊號腳 141‧‧‧ signal foot

142‧‧‧電壓腳 142‧‧‧ voltage foot

2‧‧‧電子設備 2‧‧‧Electronic equipment

20‧‧‧殼體 20‧‧‧shell

21‧‧‧預設觸碰區 21‧‧‧Preset touch zone

3‧‧‧觸控筆 3‧‧‧ stylus

30‧‧‧筆桿 30‧‧‧ pen

31‧‧‧觸控筆尖 31‧‧‧Touch tip

32‧‧‧無線模組 32‧‧‧Wireless Module

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

R‧‧‧電阻 R‧‧‧resistance

第一圖是本發明省電電路的方塊圖。 The first figure is a block diagram of the power saving circuit of the present invention.

第二圖是本發明省電電路的電路圖。 The second figure is a circuit diagram of the power saving circuit of the present invention.

第三圖是本發明一種具省電電路的電子設備的方塊圖。 The third figure is a block diagram of an electronic device with a power saving circuit of the present invention.

第四圖是本發明一種觸控筆的示意圖。 The fourth figure is a schematic view of a stylus according to the present invention.

第五圖是第四圖中觸控筆與電子裝置的使用示意圖。 The fifth figure is a schematic diagram of the use of the stylus and the electronic device in the fourth figure.

為詳細說明本發明之技術內容、構造特徵、所達成目的及功效,以下茲舉例並配合圖式詳予說明。 In order to explain the technical content, structural features, objectives and effects of the present invention in detail, the following detailed description is given by way of example.

請參閱第一圖,本發明公開一種省電電路1,用以節省終端電子裝置待機時所消耗的電源。省電電路1用以連接於一電源12以及一電子裝置電路11之間。 Referring to the first figure, the present invention discloses a power saving circuit 1 for saving power consumed by a terminal electronic device during standby. The power saving circuit 1 is connected between a power source 12 and an electronic device circuit 11.

所述省電電路1包括一可變電阻10、一開關13及一處理模組14。電源12分別連接於開關13及可變電阻10,處理模組14分別連接於開關13、可變電阻10及電子裝置電路11,開關13連接可變電阻10。 The power saving circuit 1 includes a variable resistor 10, a switch 13, and a processing module 14. The power source 12 is connected to the switch 13 and the variable resistor 10, respectively. The processing module 14 is connected to the switch 13, the variable resistor 10 and the electronic device circuit 11, respectively, and the switch 13 is connected to the variable resistor 10.

實施例中所述開關13被設置成當可變電阻10受到壓力後導通電源12及處理模組14之間的線路。 The switch 13 in the embodiment is arranged to turn on the line between the power source 12 and the processing module 14 when the variable resistor 10 is subjected to pressure.

處理模組14被設置成用以傳送電源12至電子裝置電路11、 偵測可變電阻10的訊號以及保持開關13供電,且被設置成在接收到電源12後提供開關13一工作訊號使開關13在可變電阻10未受到壓力時持續導通電源12至處理模組14的線路,處理模組14還被設置成偵測可變電阻10的電壓,並且當處理模組14關閉工作訊號時,開關13使電源12至處理模組14的線路斷路。 The processing module 14 is configured to transmit the power source 12 to the electronic device circuit 11, Detecting the signal of the variable resistor 10 and maintaining the power supply of the switch 13, and is configured to provide a switch 13 after the power source 12 is received, so that the switch 13 continuously turns on the power source 12 to the processing module when the variable resistor 10 is not under pressure. The line 14 of the processing module 14 is also arranged to detect the voltage of the variable resistor 10, and when the processing module 14 turns off the working signal, the switch 13 opens the line of the power source 12 to the processing module 14.

在一實施例當中,可變電阻10可為一壓力感測器。 In an embodiment, the variable resistor 10 can be a pressure sensor.

請參閱第二圖,係一省電電路1的實施例。可變電阻10在未受到壓力時,其阻值非常大(一般視為無限大),可變電阻10包括一第一端100及一第二端101。開關13包括一PMOS電晶體130(P-type Metal-Oxide-Semiconductor Field-Effect Transistor,PMOS FET)及一NMOS電晶體131(N-type)。處理模組14包括一接收電流的電源腳140、一發送工作訊號的訊號腳141及一偵測可變電阻10電壓的電壓腳142。 Please refer to the second figure, which is an embodiment of a power saving circuit 1. The variable resistor 10 has a very large resistance (generally regarded as infinite) when it is not subjected to pressure, and the variable resistor 10 includes a first end 100 and a second end 101. The switch 13 includes a PMOS transistor 130 (P-type Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS FET) and an NMOS transistor 131 (N-type). The processing module 14 includes a power supply pin 140 for receiving current, a signal pin 141 for transmitting a working signal, and a voltage pin 142 for detecting the voltage of the variable resistor 10.

電源12的正極分別連接PMOS電晶體130的源極S及可變電阻10的第一端100,可變電阻10的第二端101連接NMOS電晶體131的閘極G,第二端101與NMOS電晶體131的閘極G之間的線路經過一電阻R接地,且第二端101與NMOS電晶體131的閘極G之間的線路還連接至電壓腳142,NMOS電晶體131的源極S接地,NMOS電晶體131的汲極D連接PMOS電晶體130的閘極G,PMOS電晶體130的汲極D連接電源腳140,電源12的正極與PM OS電晶體130的源極S之間的線路經過一電阻R與PMOS電晶體130的閘極G及NMOS電晶體131的汲極D之間的線路形成節點接著連接至訊號腳141。 The positive poles of the power source 12 are respectively connected to the source S of the PMOS transistor 130 and the first end 100 of the variable resistor 10. The second end 101 of the variable resistor 10 is connected to the gate G of the NMOS transistor 131, and the second terminal 101 and the NMOS are connected. The line between the gates G of the transistor 131 is grounded via a resistor R, and the line between the second terminal 101 and the gate G of the NMOS transistor 131 is also connected to the voltage pin 142, the source S of the NMOS transistor 131. Grounding, the drain D of the NMOS transistor 131 is connected to the gate G of the PMOS transistor 130, the drain D of the PMOS transistor 130 is connected to the power supply pin 140, and the positive terminal of the power supply 12 is connected to the PM. The line between the source S of the OS transistor 130 is connected to the signal pin 141 via a resistor R and a line forming node between the gate G of the PMOS transistor 130 and the drain D of the NMOS transistor 131.

其中,可變電阻10的第二端101與NMOS電晶體131的閘極G之間的線路串聯一反向迴路放大器102後連接電壓腳142。當電壓進入反向迴路放大器102後電壓值經過處理,使電壓的變化形成更易於判讀的線性起伏。 The circuit between the second end 101 of the variable resistor 10 and the gate G of the NMOS transistor 131 is connected in series with a reverse loop amplifier 102 and then connected to the voltage pin 142. When the voltage enters the reverse loop amplifier 102, the voltage value is processed, causing the voltage change to form a linear undulation that is easier to interpret.

本實施例的省電電路1的電流流通方式為,在可變電阻10受到壓力後,因壓力變化使得可變電阻10內部的阻值開始變小,接著因電路分壓定理,使得NMOS電晶體131的閘極G受到電壓而使NMOS電晶體131的汲極D與源極S導通,由於NMOS電晶體131的源極S接地,使PMOS電晶體130的閘極G準位降低進而導通PMOS電晶體130的汲極D與源極S,使電源腳140接收電源。 The current circulation mode of the power saving circuit 1 of the present embodiment is such that after the variable resistor 10 is subjected to pressure, the resistance inside the variable resistor 10 starts to decrease due to the pressure change, and then the NMOS transistor is caused by the circuit partial pressure theorem. The gate G of the 131 is subjected to a voltage, and the drain D of the NMOS transistor 131 is turned on and the source S is turned on. Since the source S of the NMOS transistor 131 is grounded, the gate G of the PMOS transistor 130 is lowered and the PMOS is turned on. The drain D and the source S of the crystal 130 cause the power supply pin 140 to receive power.

可變電阻10的第二端101的電壓能夠被處理模組14的電壓腳142接收。處理模組14控制訊號腳141發出低準位電壓使PMOS電晶體130的閘極G為低準位,進而使PMOS電晶體130的汲極D與源極S保持導通(此時第一可變電阻10無論有無受到壓力,處理模組14仍可接收到電源)。 The voltage at the second terminal 101 of the variable resistor 10 can be received by the voltage pin 142 of the processing module 14. The processing module 14 controls the signal pin 141 to emit a low level voltage so that the gate G of the PMOS transistor 130 is at a low level, thereby keeping the drain D and the source S of the PMOS transistor 130 conductive (the first variable at this time) The resistor 10 can receive power even if the resistor 10 is under pressure.

雖然可變電阻10未受到壓力時,可變電阻10的電阻變回無限大,且可變電阻10至處理模組14的電壓腳142的線路為斷路以及NMOS電晶體131的汲極D與源極S不導通,然而PMOS電晶體130的閘極G受到訊號腳141提供低準位的影 響,根據PMOS電晶體130的特性,PMOS電晶體130的汲極D與源極S持續導通,使電源腳140為導通狀態,因此當導通電流後,電源12的關閉由處理模組14控制。 Although the variable resistor 10 is not subjected to pressure, the resistance of the variable resistor 10 changes back to infinity, and the line of the variable resistor 10 to the voltage pin 142 of the processing module 14 is an open circuit and the drain D and the source of the NMOS transistor 131. The pole S is not conducting, but the gate G of the PMOS transistor 130 is provided by the signal pin 141 to provide a low level of shadow. According to the characteristics of the PMOS transistor 130, the drain D and the source S of the PMOS transistor 130 are continuously turned on, so that the power pin 140 is turned on. Therefore, when the current is turned on, the power source 12 is turned off by the processing module 14.

當電子裝置電路11需要關閉電源,處理模組14只要控制訊號腳141發出高準位電壓,根據PMOS電晶體130的特性,PMOS電晶體130的閘極G受到訊號腳141高準位電壓的影響PMOS電晶體130的汲極D與源極S形成不導通,進而使處理模組14與電源12斷路,根據第二圖所示,在關閉狀態PMOS電晶體130的閘極G與源極S同時是高準位。 When the electronic device circuit 11 needs to turn off the power, the processing module 14 only needs to control the signal pin 141 to emit a high level voltage. According to the characteristics of the PMOS transistor 130, the gate G of the PMOS transistor 130 is affected by the high level voltage of the signal pin 141. The drain D and the source S of the PMOS transistor 130 are non-conducting, and the processing module 14 is disconnected from the power source 12. According to the second figure, the gate G and the source S of the PMOS transistor 130 are turned off in the off state. It is a high standard.

電子裝置電路11關閉方式可以選擇為,若一段時間後電壓腳142所偵測之電壓值持續為零,則透過設定訊號腳141為高準位電壓,以關閉電流來源。 The electronic device circuit 11 can be turned off. If the voltage value detected by the voltage pin 142 continues to be zero after a period of time, the set signal pin 141 is set to a high level voltage to turn off the current source.

請參閱第三圖,省電電路1可應用於一電子設備2中,電子設備2由一殼體20將省電電路1及電子裝置電路11收容於內部。電子設備2的殼體20上具有一預設觸碰區21,可變電阻10被設置成使用者碰觸預設觸碰區21時受感應,電子裝置電路11可以根據省電電路1所偵測的可變電阻10電壓值之改變進而控制電子設備2。 Referring to the third figure, the power saving circuit 1 can be applied to an electronic device 2, and the electronic device 2 is housed inside the power saving circuit 1 and the electronic device circuit 11 by a casing 20. The housing 20 of the electronic device 2 has a predetermined touch area 21, and the variable resistor 10 is arranged to be sensed when the user touches the preset touch area 21, and the electronic device circuit 11 can be detected according to the power saving circuit 1. The measured change in the voltage value of the variable resistor 10 in turn controls the electronic device 2.

進一步說明,預設觸碰區21為使用者在使用電子產品時,電子產品與身體接觸或是與物體接觸的位置。 Further, the preset touch area 21 is a position where the electronic product contacts the body or contacts the object when the electronic product is used.

請參閱第四圖,所述電子設備2可以是一種觸控筆3,其包括一筆桿30、一位於筆桿30之一端的觸控筆尖31,可變電阻10連接於觸控筆尖31,所述省電電路1與電子裝置電路11均 位於筆桿30內。 Referring to the fourth figure, the electronic device 2 can be a stylus 3 including a pen 30, a stylus tip 31 at one end of the pen 30, and a variable resistor 10 connected to the stylus tip 31. The power saving circuit 1 and the electronic device circuit 11 are both Located in the pen holder 30.

如第五圖顯示,觸控筆尖31與可變電阻10被設置成當使用者將觸控筆3的觸控筆尖31接觸物體時可變電阻10被擠壓,藉此可變電阻10除了能夠感應觸控筆3的筆觸還能夠做為觸控筆3的開關。 As shown in the fifth figure, the stylus tip 31 and the variable resistor 10 are disposed such that when the user touches the stylus tip 31 of the stylus pen 3 to the object, the variable resistor 10 is squeezed, whereby the variable resistor 10 can be The stroke of the inductive stylus 3 can also be used as a switch of the stylus 3.

為使觸控筆3能夠與電子裝置連結以感測使用者的筆觸,觸控筆包括一連接電子裝置電路11的無線模組34,用以提供電子裝置電路11與電子裝置溝通。 In order to enable the stylus 3 to be coupled to the electronic device to sense the user's stroke, the stylus includes a wireless module 34 connected to the electronic device circuit 11 for providing the electronic device circuit 11 to communicate with the electronic device.

本發明的省電電路1具備下列優點: The power saving circuit 1 of the present invention has the following advantages:

一、本發明的省電電路1提高電子設備2的待機時間。 1. The power saving circuit 1 of the present invention increases the standby time of the electronic device 2.

二、本發明的省電電路1使可變電阻10除了可以用來感測壓力,還能做為電子設備2的開關,使電子設備2省去一構件,並且藉此節省製造時間與經費。 2. The power saving circuit 1 of the present invention allows the variable resistor 10 to be used as a switch for the electronic device 2 in addition to sensing the pressure, thereby eliminating the need for the electronic device 2 to save a manufacturing time and expense.

三、本發明的省電電路1應用於觸控筆3時,觸控筆3使用方式與一般書寫筆一樣直覺,隨取隨用,不需要有另外的動作打開電源,藉以提升使用者的日常體驗。 3. When the power saving circuit 1 of the present invention is applied to the stylus pen 3, the stylus pen 3 is used in the same sense as the general writing pen, and it can be used as needed, and no additional action is required to turn on the power source, thereby improving the daily life of the user. Experience.

四、由於本發明的電子設備2及觸控筆3外表面上不需要設置開關,因此可以使得外觀設計更不受限制。 Fourth, since the electronic device 2 and the stylus 3 of the present invention do not need to be provided with switches on the outer surface, the design can be made more unrestricted.

有鑑於所述優點,透過結合本發明的省電電路1的電子設備2在市場上受消費者歡迎是可期的,為使公眾能享受此技藝所帶來的利益,盼貴承審委員能早日准予本案之專利申請,實感德便。 In view of the above advantages, it is expected that the electronic device 2 incorporating the power saving circuit 1 of the present invention is popular among consumers in the market, and in order to enable the public to enjoy the benefits brought by this skill, it is hoped that the auditing committee can As soon as possible, the patent application for this case was granted.

1‧‧‧省電電路 1‧‧‧Power saving circuit

10‧‧‧第一可變電阻 10‧‧‧First variable resistor

100‧‧‧第一端 100‧‧‧ first end

101‧‧‧第二端 101‧‧‧ second end

102‧‧‧反向迴路放大器 102‧‧‧Reverse loop amplifier

12‧‧‧電源 12‧‧‧Power supply

13‧‧‧開關 13‧‧‧ switch

130‧‧‧PMOS電晶體 130‧‧‧PMOS transistor

131‧‧‧NMOS電晶體 131‧‧‧NMOS transistor

14‧‧‧處理模組 14‧‧‧Processing module

140‧‧‧電源腳 140‧‧‧Power foot

141‧‧‧訊號腳 141‧‧‧ signal foot

142‧‧‧電壓腳 142‧‧‧ voltage foot

G‧‧‧閘極 G‧‧‧ gate

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

R‧‧‧電阻 R‧‧‧resistance

Claims (3)

一種省電電路,連接一電源,其包括:一可變電阻、一開關及一處理模組,電源分別連接於開關及可變電阻,處理模組分別連接於開關及可變電阻,開關連接可變電阻;開關被設置成當可變電阻受到壓力後導通電源及處理模組之間的線路;處理模組被設置成在接收到電源後提供開關一工作訊號使開關在可變電阻未受到壓力時持續導通電源至處理模組之間的線路;或是,處理模組被設置成偵測可變電阻的電壓值持續一段時間不變動為零,以關閉工作訊號時,提供開關一工作訊號使電源至處理模組的線路斷路;其特徵在於:所述可變電阻包括一第一端及一第二端,開關包括一PMOS電晶體及一NMOS電晶體,處理模組包括一電源腳、發送工作訊號的一訊號腳及一偵測可變電阻電壓的電壓腳,電源的正極分別連接PMOS電晶體的源極及可變電阻的第一端,第二端連接NMOS電晶體的閘極,第二端與NMOS電晶體的閘極之間的線路經過一電阻接地,第二端與NMOS電晶體的閘極之間的線路連接至電壓腳,NMOS電晶體的源極接地,NMOS電晶體的汲極連接PMOS電晶體的閘極,PMOS電晶體的汲極連接電源腳,電源的正極與PMOS電晶體的源極之間的線路經過一電阻與PMOS電晶體的閘極及NMOS電晶體的汲極之間的線路形成節點接著連接至訊號腳。 A power-saving circuit is connected to a power supply, comprising: a variable resistor, a switch and a processing module, wherein the power source is respectively connected to the switch and the variable resistor, and the processing module is respectively connected to the switch and the variable resistor, and the switch connection is The variable resistor; the switch is configured to turn on the line between the power supply and the processing module when the variable resistor is under pressure; the processing module is configured to provide a switch-operating signal after receiving the power source so that the switch is not under pressure in the variable resistor Continuously turning on the power to the circuit between the processing modules; or, the processing module is configured to detect the voltage value of the variable resistor for a period of time that does not change to zero, to provide a switch-operation signal when the working signal is turned off The circuit is disconnected from the power supply to the processing module; the variable resistor includes a first end and a second end, the switch includes a PMOS transistor and an NMOS transistor, and the processing module includes a power pin and transmits a signal pin of the working signal and a voltage pin for detecting the variable resistance voltage, the positive pole of the power source is respectively connected to the source of the PMOS transistor and the first end of the variable resistor, and the second end is connected The gate of the NMOS transistor, the line between the second end and the gate of the NMOS transistor is grounded through a resistor, and the line between the second end and the gate of the NMOS transistor is connected to the voltage pin, the source of the NMOS transistor The pole is grounded, the drain of the NMOS transistor is connected to the gate of the PMOS transistor, the drain of the PMOS transistor is connected to the power supply pin, and the line between the anode of the power supply and the source of the PMOS transistor passes through a resistor and a gate of the PMOS transistor. The line forming node between the poles of the pole and the NMOS transistor is then connected to the signal pin. 如申請專利範圍第1項所述之省電電路,其中所述可變電阻可為 壓力感測器。 The power saving circuit of claim 1, wherein the variable resistor is Pressure sensor. 如申請專利範圍第1項所述之省電電路,其中所述第二端與NMOS電晶體的閘極之間的線路串聯一反向迴路放大器後連接電壓腳。 The power saving circuit of claim 1, wherein the circuit between the second end and the gate of the NMOS transistor is connected in series with a reverse loop amplifier and connected to the voltage pin.
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