CN201917867U - Hibernating and waking-up circuit of microprocessor - Google Patents
Hibernating and waking-up circuit of microprocessor Download PDFInfo
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- CN201917867U CN201917867U CN2010206825077U CN201020682507U CN201917867U CN 201917867 U CN201917867 U CN 201917867U CN 2010206825077 U CN2010206825077 U CN 2010206825077U CN 201020682507 U CN201020682507 U CN 201020682507U CN 201917867 U CN201917867 U CN 201917867U
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Abstract
The utility model discloses a hibernating and waking-up circuit of a microprocessor, which comprises an energy-saving control signal acquisition circuit and a resetting control circuit. The energy-saving control signal acquisition circuit is provided with a resistor R5 and a switch key K1 which are electrically connected mutually, an interrupt pin of the microprocessor U2 is connected between the resistor R5 and the switch key K1, one end of the resistor R5 is connected with high level, one end of the switch key K1 is grounded, the resetting control circuit is provided with a starting key K2, one end of the starting key K2 is electrically connected with the high level while the other end of the starting key K2 is electrically connected to a resetting pin of the microprocessor U2, the resetting pin is electrically connected with a resistor R1, a capacitor EC1 and a switch element Q1, one end of the resistor R1 and one end of the switch element Q1 are grounded, and the switch element Q1 is electrically connected to the microprocessor U2. The hibernating and waking-up circuit is simple in structure, low in cost and high in reliability.
Description
Technical field
The utility model relates to a kind of dormancy and wake-up circuit, especially relates to a kind of microprocessor dormancy and wake-up circuit.
Background technology
Along with development of electronic technology, the performance of electronic product from strength to strength, its power consumption is also increasing.In the electronic product formerly, the user is usually by the powered-down device or manually other of battery and electronic product inside used module by switch and disconnected, so as when not use device consumed power not.
Developed the electronic product that much turns round in the prior art, made and through user operable switch battery to be isolated fully with low-power.For example, each functional circuit module that existing electronic product is provided with microprocessor usually and is electrically connected with described microprocessor, be provided with dormancy program and wake up procedure in the described microprocessor, in dormant state, described dormancy program is by cutting off the power supply to the functional circuit module of inoperative, thereby eliminate the leakage current of the functional circuit module of described inoperative, thereby can realize purpose of energy saving.Produce the wake-up trigger incident by program when waking up and wake up, thereby reliability is low.
Summary of the invention
The utility model is to provide at the defective that the above-mentioned background technology exists that a kind of circuit structure is simple, cost low and high microprocessor dormancy and the wake-up circuit of reliability.
For achieving the above object, the utility model discloses a kind of microprocessor dormancy and wake-up circuit, it comprises Energy Saving Control signal acquisition circuit and reset control circuit, described Energy Saving Control signal acquisition circuit is provided with the resistance R 5 and the on ﹠ off switch K1 of mutual electrical connection, the interrupt pin of microprocessor U2 is connected between described resistance R 5 and the on ﹠ off switch K1, one end of described resistance R 5 is connected with high level, the end ground connection of described on ﹠ off switch K1; Described reset control circuit is provided with start key K2, described start key K2 one end is electrically connected with high level, the other end is electrically connected to the reset pin of microprocessor U2, described reset pin is electrically connected with resistance R 1, electric capacity EC1 and on-off element Q1, the end ground connection of described resistance R 1 and on-off element Q1, on-off element Q1 is electrically connected to described microprocessor U2.
Further, described on-off element Q1 is a triode, and the collector of described triode is electrically connected with described reset pin, the grounded emitter of described triode, and the base stage of described triode is electrically connected to described microprocessor U2.
Further, be provided with resistance R 2 between the base stage of described triode and the described microprocessor.
Further, be provided with resistance R 4 between described start key K2 and the described reset pin.
Further, described electric capacity EC1 is an electrochemical capacitor, and an end of this electrochemical capacitor is electrically connected with high level.
In sum, dormancy of the utility model microprocessor and wake-up circuit are by being provided with described Energy Saving Control signal acquisition circuit and reset control circuit, the start key by controlling described Energy Saving Control signal acquisition circuit or the closing key of reset control circuit, just realize starting shooting accordingly and enter dormancy energy-conservation/awakening mode, thereby circuit structure is simple, cost low and the reliability height.
Description of drawings
Fig. 1 is the circuit diagram of a kind of embodiment of the utility model when cooperating with microprocessor.
Embodiment
For further understanding feature of the present utility model, technological means and the specific purposes that reached, function, the utility model is described in further detail below in conjunction with accompanying drawing and embodiment.
See also Fig. 1, dormancy of the utility model microprocessor and wake-up circuit comprise Energy Saving Control signal acquisition circuit 1 and reset control circuit 2, described Energy Saving Control signal acquisition circuit 1 is provided with the resistance R 5 and the on ﹠ off switch K1 of mutual electrical connection, the interrupt pin of microprocessor U2 is connected between described resistance R 5 and the on ﹠ off switch K1, one end of described resistance R 5 is connected with high level, the end ground connection of described on ﹠ off switch K1.
Described reset control circuit 2 is provided with start key K2, and described start key K2 one end is electrically connected with high level, and the other end is electrically connected with resistance R 4, and described resistance R 4 is electrically connected with the reset pin of described microprocessor U2.Be electrically connected with resistance R 1, electric capacity EC1 and on-off element Q1 between described reset pin and the described resistance R 4, an end ground connection of described resistance R 1.
In the present embodiment, described electric capacity EC1 is an electrochemical capacitor, and an end of this electrochemical capacitor is electrically connected with high level.Described on-off element Q1 is a triode, the collector of described triode is electrically connected with described reset pin, the grounded emitter of described triode, the base stage of described triode is electrically connected with resistance R 2, and the other end of described resistance R 2 is electrically connected with the interrupt pin P3.2 of described microprocessor U2.
Principle of work of the present utility model is as follows: after circuit powered on, described electric capacity EC1 and resistance R 1 were formed a RC delay circuit, finish the electrification reset function of microprocessor U2.At this moment, triode is not in cut-off state because of there being base voltage, does not influence electrification reset RC delay circuit.After the microprocessor U2 work, its pin P3.0 puts high level, the triode conducting, and make pin RST keep low level, at this moment, K2 is invalid for the start key.
After the user presses closing key K1; the level of the interrupt pin P3.2 of microprocessor U2 becomes low level by high level; at this moment; microprocessor U2 pin P3.0 puts low level; promptly allow start; the functional module of power consumption also out of service simultaneously and possibility power consumption just enters shutdown mode, i.e. energy saver mode then.When wanting to withdraw from energy saver mode, then by start key K2 start, after start key K2 was pressed, high level was given microprocessor U2 through resistance R 4 current limlitings, and microprocessor U2 is resetted, and microprocessor U2 withdraws from energy saver mode, reenters mode of operation.
In sum, dormancy of the utility model microprocessor and wake-up circuit are by being provided with described Energy Saving Control signal acquisition circuit 1 and reset control circuit 2, the start key K2 by controlling described Energy Saving Control signal acquisition circuit 1 or the closing key K1 of reset control circuit 2, just realize starting shooting accordingly and enter dormancy energy-conservation/awakening mode, thereby circuit structure is simple, cost low and the reliability height.
The above embodiment has only expressed a kind of embodiment of the present utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model scope.Should be pointed out that for the person of ordinary skill of the art, under the prerequisite that does not break away from the utility model design; can also make some distortion and improvement; for example, described on-off element Q1 is set to field effect transistor etc., and these all belong to protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with claims.
Claims (5)
1. microprocessor dormancy and wake-up circuit, it is characterized in that: comprise Energy Saving Control signal acquisition circuit (1) and reset control circuit (2), described Energy Saving Control signal acquisition circuit (1) is provided with the resistance R 5 and the on ﹠ off switch K1 of mutual electrical connection, the interrupt pin of microprocessor U2 is connected between described resistance R 5 and the on ﹠ off switch K1, one end of described resistance R 5 is connected with high level, the end ground connection of described on ﹠ off switch K1; Described reset control circuit (2) is provided with start key K2, described start key K2 one end is electrically connected with high level, the other end is electrically connected to the reset pin of microprocessor U2, described reset pin is electrically connected with resistance R 1, electric capacity EC1 and on-off element Q1, the end ground connection of described resistance R 1 and on-off element Q1, on-off element Q1 is electrically connected to described microprocessor U2.
2. microprocessor dormancy according to claim 1 and wake-up circuit, it is characterized in that: described on-off element Q1 is a triode, the collector of described triode is electrically connected with described reset pin, the grounded emitter of described triode, the base stage of described triode are electrically connected to described microprocessor U2.
3. microprocessor dormancy according to claim 2 and wake-up circuit is characterized in that: be provided with resistance R 2 between the base stage of described triode and the described microprocessor.
4. according to claim 1 or 2 or 3 described microprocessor dormancy and wake-up circuits, it is characterized in that: be provided with resistance R 4 between described start key K2 and the described reset pin.
5. according to claim 1 or 2 or 3 described microprocessor dormancy and wake-up circuits, it is characterized in that: described electric capacity EC1 is an electrochemical capacitor, and an end of this electrochemical capacitor is electrically connected with high level.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010206825077U CN201917867U (en) | 2010-12-28 | 2010-12-28 | Hibernating and waking-up circuit of microprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010206825077U CN201917867U (en) | 2010-12-28 | 2010-12-28 | Hibernating and waking-up circuit of microprocessor |
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CN201917867U true CN201917867U (en) | 2011-08-03 |
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CN2010206825077U Expired - Lifetime CN201917867U (en) | 2010-12-28 | 2010-12-28 | Hibernating and waking-up circuit of microprocessor |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102053701A (en) * | 2010-12-28 | 2011-05-11 | 东莞常禾电子有限公司 | Microprocessor sleeping and awakening circuit |
CN104914969A (en) * | 2014-03-13 | 2015-09-16 | 鸿富锦精密工业(武汉)有限公司 | Connector port power supply circuit |
CN104978005A (en) * | 2014-04-02 | 2015-10-14 | 新巨企业股份有限公司 | Power supply device and method for reducing energy consumption of same |
-
2010
- 2010-12-28 CN CN2010206825077U patent/CN201917867U/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102053701A (en) * | 2010-12-28 | 2011-05-11 | 东莞常禾电子有限公司 | Microprocessor sleeping and awakening circuit |
CN104914969A (en) * | 2014-03-13 | 2015-09-16 | 鸿富锦精密工业(武汉)有限公司 | Connector port power supply circuit |
CN104978005A (en) * | 2014-04-02 | 2015-10-14 | 新巨企业股份有限公司 | Power supply device and method for reducing energy consumption of same |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
AV01 | Patent right actively abandoned |
Granted publication date: 20110803 Effective date of abandoning: 20120926 |