TWI532326B - Charge pump circuit with low clock feed through - Google Patents

Description

Low-clock feed-in charge pump circuit

The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit that reduces the clock feed effect.

Phase lock loops (PLLs) have been widely used in various electronic devices and systems. Phase-locked loops are commonly used to generate clock signals, clock samples, signal synchronization, and frequency synthesis for generating clocks and signals, and charge pump circuits are often used to change the potential in a phase-locked loop.

Please refer to FIG. 1 , which is a schematic diagram of a conventional charge pump circuit 100 . The charge pump circuit 100 includes a charge current mirror 10, a discharge current mirror 20, a P-channel gold oxide semiconductor (PMOS) switch K5, and an N-channel gold oxide semiconductor (NMOS) switch K6. The charging current mirror 10 includes PMOS transistors K1 and K2, and is coupled to the voltage source VDD to provide a charging current I _up . The discharge current mirror 20 includes NMOS transistors K3 and K4, all coupled to ground to provide a discharge current I _dn .

The PMOS switch K5 and the NMOS switch K6 are coupled to a charge pump output OUT and controlled by control signals UN and DP generated by a phase frequency detector (PFD) 30. However, when the control signals UN and DP change from a high level to a low level, or from a low level to a high level, the parasitic capacitances C _gsp , C _gdp , C _{gsn ,} and C _{gdn of the} PMOS switch K5 and the NMOS switch K6 cause a charge. Pump output OUT has a non-ideal voltage swing phenomenon, which is also known as clock feed-through.

In addition, when the PMOS switch K5 and the NMOS switch K6 are turned off, the charge in the depletion region of the channel is injected into the parasitic capacitances C _gsp , C _gdp , C _{gsn ,} and C _gdn , which also causes the charge pump output OUT to be non-ideal. The phenomenon of voltage turbulence, which is also known as charge injection.

Furthermore, the voltage turbulence phenomenon causes an up/down current mismatch of the charge pump circuit 100, for example, when the potential of the charge pump output OUT becomes high, the drain of the NMOS transistor K4 to the source The voltage difference will become higher, and the current flowing from the charge pump output OUT through the NMOS switch K6 becomes larger; in addition, when the potential of the charge pump output OUT becomes high, the source-to-drain voltage difference of the PMOS transistor K2 will It becomes smaller, and the current flowing from the voltage source V _DD through the PMOS transistor K2 becomes smaller.

The above-mentioned clock feed, charge injection and up/down current mismatch effects due to the voltage turbulence phenomenon of the charge pump output OUT cause parasitic noise generated by the output signal generated from the charge pump output OUT to deteriorate the output signal. Quality.

An embodiment of the present invention provides a charge pump circuit including a first comparator, a PMOS tuner, a first current mirror, a first NMOS transistor, a first PMOS switch, an NMOS tuner, a second current mirror and a first NMOS switch. The first comparator has a first input terminal, a second input terminal and an output terminal. The output terminal is coupled to the second input end of the first comparator. The PMOS tuner has a source coupled to a voltage source and a drain for receiving a first bias voltage. The first current mirror includes a starting PMOS transistor and a first output PMOS transistor. The starting PMOS transistor has a source coupled to the voltage source and a gate coupled to the drain of the starting PMOS transistor. The first output PMOS transistor has a gate coupled to the gate of the starting PMOS transistor and a drain coupled to the first input of the first comparator. The first NMOS transistor has a drain coupled to the gate of the first output PMOS transistor, a gate coupled to the output of the first comparator, and a source coupled to the ground . The first PMOS switch has a drain, a source coupled to the source of the first output PMOS transistor, a source coupled to the drain of the PMOS tuner, and a gate for receiving a first control signal. The NMOS tuner has a source coupled to ground and a gate for receiving a second bias. The second current mirror includes a starting NMOS transistor and a first output NMOS transistor. The starting NMOS transistor has a source coupled to the ground and a gate coupled to the drain of the starting NMOS transistor. The first output NMOS transistor has a gate coupled to the gate of the starting NMOS transistor and a drain coupled to the first input of the first comparator. The first PMOS transistor has a drain coupled to the gate of the first output NMOS transistor, a gate coupled to the output of the first comparator, and a source coupled to the gate power source. The first NMOS switch has a drain, a source coupled to the source of the first output NMOS transistor, a source coupled to the drain of the NMOS tuner, and a gate for receiving a second control signal.

Please refer to FIG. 2, which is a block diagram of the phase locked loop 250 of the present invention. As shown in FIG. 2, the phase locked loop 250 includes a phase frequency detector (PFD) 212, a charge pump circuit 200, a loop filter 216, a voltage controlled oscillator 218, and a divider 220. . The phase locked loop 250 receives an input reference signal F _ref and generates an output signal F _out . Divider 220 divides the output signal _Fout to produce a feedback signal. The phase frequency detector 212 is based on a phase or frequency difference between the input reference signal F _ref and the feedback signal to produce an output signal F _out . After comparing the phase or frequency difference between the input reference signal F _ref and the feedback signal, the phase frequency detector 212 generates a control signal and transmits a control signal to the charge pump circuit 200. The charge pump circuit 200 generates a charging current to charge the load capacitance in the loop filter 216 or to generate a discharge current to discharge the load capacitance in the loop filter 216.

The above described operation of charging or discharging the load capacitance in the loop filter 216 affects the output voltage from the loop filter 216 output to the voltage controlled oscillator 218. VCO 218 based on the output from the line voltage of the loop filter 216 to change the phase or frequency of the output signal F _out. With the above arrangement, the phase locked loop 250 can continuously adjust the output signal F _out according to the input reference signal F _ref .

Please refer to FIG. 3, which is a schematic diagram of a charge pump circuit 300 according to a first embodiment of the present invention. As shown in FIG. 3, the charge pump circuit 300 includes a first comparator 38, a PMOS tuner M1, a first current mirror 310, a first NMOS transistor M5, a first PMOS switch 312, and an NMOS tuning. The device M7, a second current mirror 320, a first NMOS switch 314 and a first PMOS transistor M10. The first comparator 38 has a first input terminal 301 , a second input terminal 302 , and an output terminal 303 . The output terminal 303 is coupled to the second input terminal 302 of the first comparator 38 . The PMOS tuner M1 has a source coupled to a voltage source V _DD and a gate for receiving a first bias voltage V _B1 . The first current mirror 310 includes a starting PMOS transistor M4 and a first output PMOS transistor M2. The starting PMOS transistor M4 has a source coupled to the voltage source V _DD and a gate coupled to the drain of the starting PMOS transistor M4. The first output PMOS transistor M2 has a gate coupled to the gate of the starting PMOS transistor M4 and a drain coupled to the first input terminal 301 of the first comparator 38. The first NMOS transistor M5 has a drain, is coupled to the gate of the first output PMOS transistor M2, a gate is coupled to the output terminal 303 of the first comparator 38, and a source is coupled to Ground. The first PMOS switch 312 has a drain, a source coupled to the source of the first output PMOS transistor M2, a source coupled to the drain of the PMOS tuner M1, and a gate for receiving a first Control signal UP1.

The NMOS tuner M7 has a source coupled to the ground and a gate for receiving a second bias voltage V _B2 . The second current mirror 320 includes a starting NMOS transistor M9 and a first output NMOS transistor M6. The starting NMOS transistor M9 has a source coupled to the ground and a gate coupled to the drain of the starting NMOS transistor M9. The first output NMOS transistor M6 has a gate coupled to the gate of the starting NMOS transistor M9 and a drain coupled to the first input terminal 301 of the first comparator 38. The first PMOS transistor M10 has a drain, is coupled to the gate of the first output NMOS transistor M6, a gate is coupled to the output terminal 303 of the first comparator 38, and a source is coupled to the first NMOS transistor M6. Voltage source V _DD . The first NMOS switch 314 has a drain, a source coupled to the source of the first output NMOS transistor M6, a source coupled to the drain of the NMOS tuner M7, and a gate for receiving a second Control signal DN2.

In general, the logic potentials of the first control signal UP1 and the second control signal DN2 are opposite. However, by changing the component types of the first PMOS switch 312 and the first NMOS switch 314, the first control signal UP1 and the second control signal DN2 may also have the same logic potential.

In the first embodiment, when the charge pump output V _cont has a voltage turbulence phenomenon, the clock feed, charge injection, and up/down current mismatch effects can be alleviated, so the signal quality generated by the charge pump output V _cont Will not be worsened. For example, when the output potential of the charge pump output V _cont becomes high, the drain-to-source voltage difference of the first output NMOS transistor M6 becomes higher. Due to the channel length modulation effect, an increase in the drain-to-source voltage difference of the first output NMOS transistor M6 results in an increase in current flowing from the charge pump output V _cont through the first output NMOS transistor M6. On the other hand, when the potential of the charge pump output V _cont rises, the source-to-gate voltage difference of the first PMOS transistor M10 becomes lower due to the setting of the first comparator 38, and flows through the start. The current of the NMOS transistor M9 also becomes lower, thereby lowering the gate-to-source voltage difference of the starting NMOS transistor M9, and the gate-to-source voltage difference of the first output NMOS transistor M6 is also due to the second current. The setting of the mirror 320 becomes lower. Therefore, the channel length modulation effect is slowed down based on the gate-to-source voltage difference of the first output NMOS transistor M6, and the self-charge pump output V _cont flows through the first output NMOS transistor M6. The current level will not be affected by the actual amount.

That is, although the drain-to-source voltage difference of the first output NMOS transistor M6 rises due to the potential rise of the charge pump output V _cont , the gate-to-source voltage difference of the NMOS transistor M6 decreases and eases. The channel length modulation effect. Therefore, the magnitude of the current flowing from the charge pump output V _cont through the first output NMOS transistor M6 will not increase as the potential of the charge pump output V _cont rises. Similarly, the current flowing from the voltage source V _DD through the first output PMOS transistor M2 will not decrease as the potential of the charge pump output V _cont rises. Therefore, the voltage turbulence phenomenon of the charge pump output V _cont will not substantially affect the current flowing from the voltage source V _DD through the first output PMOS transistor M2 and from the charge pump output V _cont through the first output NMOS transistor M6. The magnitude of the current.

Therefore, in the first embodiment, when the charge pump output V _{cont is} subjected to voltage turbulence, the effect of the up/down current mismatch can be alleviated, so that the quality of the signal generated by the charge pump output V _cont can be maintained.

Please refer to FIG. 4, which is an explanatory diagram of the charge pump circuit 300. Since the first PMOS switch 312 is coupled between the PMOS tuner M1 and the first output PMOS transistor M2, the parasitic capacitance C1 formed between the gate and the drain of the first PMOS switch 312 is formed in the first The parasitic capacitance C2 between the gate and the source of the output PMOS transistor M2 and the parasitic capacitance C3 formed between the gate and the drain of the first output PMOS transistor M2 are equivalent to the series connection, and the PMOS tuner is lowered. The value of the capacitance between M1 and the charge pump output V _cont . Therefore, the clock feed and charge injection effects in the charge pump circuit 300 can be alleviated.

Please refer to FIG. 5, which is a schematic diagram of a charge pump circuit 500 according to a second embodiment of the present invention. The difference between the charge pump circuit 500 and the charge pump circuit 300 is that the charge pump circuit 500 further includes a second PMOS switch M3 and a second NMOS switch M8. The second PMOS switch M3 has a drain coupled to the source of the starting PMOS transistor M4, a source coupled to the voltage source V _DD , and a gate coupled to the first NMOS transistor M5 Gate. The second NMOS switch M8 has a drain coupled to the source of the first NMOS transistor M9, a source coupled to the ground, and a gate coupled to the gate of the first PMOS transistor M10.

In the second embodiment, the potential of the output terminal 303 of the first comparator 38 is limited to enable the second PMOS switch M3, the first NMOS transistor M5, the second NMOS switch M8, and the first PMOS transistor M10 to be simultaneously turned on. The scope. To simultaneously turn on the second PMOS switch M3, the first NMOS transistor M5, the first PMOS transistor M10, and the second NMOS switch M8, if the threshold voltages of the first PMOS transistor M10 and the second PMOS switch M3 are _Vtp , and The threshold voltage of the first NMOS transistor M5 and the second NMOS switch M8 is V _tn , and the gate voltage required to turn on the first PMOS transistor M10 and the second PMOS switch M3 must be lower than (V _DD -V _tp ), The gate voltage required to turn on the first NMOS transistor M5 and the second NMOS switch M8 must be higher than V _tn . Therefore, the potential of the output terminal 303 of the first comparator 38 capable of simultaneously turning on the second PMOS switch M3, the first NMOS transistor M5, the first PMOS transistor M10, and the second NMOS switch M8 is limited to (V _DD - Between V _tp ) and V _tn . When the second PMOS switch M3, the first NMOS transistor M5, the second NMOS switch M8, and the first PMOS transistor M10 are turned on, the PMOS tuner M1, the first PMOS switch 312, and the first NMOS switch 314 are turned on. The NMOS tuner M7, therefore, the charge pump circuit 500 is formed from the V _DD via the PMOS tuner M1, the first PMOS switch 312, the first output PMOS transistor M2, the first output NMOS transistor M6, and the first NMOS switch 314. And the current path of the NMOS tuner M7 to ground saves power consumption of the charge pump circuit 500.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a charge pump circuit 600 according to a third embodiment of the present invention. The difference between the charge pump circuit 600 and the charge pump circuit 300 is that the charge pump circuit 600 further includes a second comparator 68, a third PMOS switch 612, and a third NMOS switch 614, and the first current mirror 610 further includes a first The second output PMOS transistor M12, the second current mirror 620 further includes a second output NMOS transistor M16. The second comparator 68 has a first input end 601 coupled to the first input end 301 of the first comparator 38, a second input end 602, and an output end 603 coupled to the second comparator 68. Second input 602. The third PMOS switch 612 has a source coupled to the drain of the PMOS tuner M1 and a gate for receiving a third control signal UP3. The third NMOS switch 614 has a source coupled to the drain of the NMOS tuner M7 and a gate for receiving a fourth control signal DN4. The second output PMOS transistor M12 has a source coupled to the drain of the third PMOS switch 612, a drain, coupled to the output 603 of the second comparator 68, and a gate coupled to the first A gate of the output PMOS transistor M2. The second output NMOS transistor M16 has a source coupled to the drain of the third NMOS switch 614, a drain coupled to the drain of the second output PMOS transistor M12, and a gate coupled to the gate. The gate of the first output NMOS transistor M6. The logic potentials of the first control signal UP1 and the second control signal DN2 are opposite, the logic potentials of the first control signal UP1 and the third control signal UP3 are opposite, and the logic potentials of the second control signal DN2 and the fourth control signal DN4 are also opposite. .

The charge pump circuit 600 provides another charge/discharge path to prevent the drain of the PMOS tuner M1 from having a charge sharing effect, for example, when the first PMOS switch 312 is turned on, the third PMOS switch 612 is turned off, and vice versa. . By alternately charging/discharging the first PMOS switch 312 and the third PMOS switch 612, the potential of the drain of the PMOS tuner M1 can be limited to be lower than a predetermined value, thereby alleviating the aforementioned channel length modulation effect.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a charge pump circuit 700 according to a fourth embodiment of the present invention. The difference between the charge pump circuit 700 and the charge pump circuit 600 is that the charge pump circuit 700 further includes a second PMOS switch M3 and a second NMOS switch M8. The second PMOS switch M3 has a drain coupled to the source of the starting PMOS transistor M4, a source coupled to the voltage source V _DD , and a gate coupled to the first NMOS transistor M5 Gate. The second NMOS switch M8 has a drain coupled to the source of the first NMOS transistor M9, a source coupled to the ground, and a gate coupled to the gate of the first PMOS transistor M10.

In the fourth embodiment, the potential of the output terminal 303 of the first comparator 38 is limited to enable the second PMOS switch M3, the first NMOS transistor M5, the second NMOS switch M8, and the first PMOS transistor M10 to be simultaneously turned on. The scope. To simultaneously turn on the second PMOS switch M3, the first NMOS transistor M5, the first PMOS transistor M10, and the second NMOS switch M8, if the threshold voltages of the first PMOS transistor M10 and the second PMOS switch M3 are _Vtp , and The threshold voltage of the first NMOS transistor M5 and the second NMOS switch M8 is V _tn , and the gate voltage required to turn on the first PMOS transistor M10 and the second PMOS switch M3 must be lower than (V _DD -V _tp ), The gate voltage required to turn on the first NMOS transistor M5 and the second NMOS switch M8 must be higher than V _tn . Therefore, the potential of the output terminal 303 of the first comparator 38 capable of simultaneously turning on the second PMOS switch M3, the first NMOS transistor M5, the first PMOS transistor M10, and the second NMOS switch M8 is limited to (V _DD - Between V _tp ) and V _tn . When the second PMOS switch M3, the first NMOS transistor M5, the second NMOS switch M8, and the first PMOS transistor M10 are turned on, the PMOS tuner M1, the first PMOS switch 312, and the first NMOS switch 314 are turned on. The NMOS tuner M7, therefore, the charge pump circuit 700 is formed from V _DD via the PMOS tuner M1, the first PMOS switch 312, the first output PMOS transistor M2, the first output NMOS transistor M6, and the first NMOS switch 314. And the current path of the NMOS tuner M7 to ground saves the power consumption of the charge pump circuit 700.

In the charge pump circuits 300, 500, 600, 700, when the charge pump output V _cont has a voltage turbulence phenomenon, the clock feed, charge injection, and up/down current mismatch effects can be alleviated, so the charge is not deteriorated. The signal quality produced by the pump output V _cont . In the charge pump circuits 500 and 700, the output terminal 303 of the first comparator 38 is limited to a range such that the charge pump circuits 500 and 700 are formed from V _DD via the PMOS tuner M1, the first PMOS switch 312, and the first The current paths of the PMOS transistor M2, the first output NMOS transistor M6, the first NMOS switch 314, and the NMOS tuner M7 to ground are output, and the power consumption of the charge pump circuits 500 and 700 is reduced. The charge pump circuits 600 and 700 provide another charge/discharge path to prevent the drain of the PMOS tuner M1 from having a charge sharing effect, while mitigating the channel length modulation effect.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300, 500, 600, 700. . . Charge pump circuit

10. . . Charging current mirror

20. . . Discharge current mirror

30, 212. . . Phase frequency detector

216. . . Loop filter

218. . . Voltage controlled oscillator

220. . . Divider

250. . . Phase-locked loop

38. . . First comparator

301. . . First input

302. . . Second input

303. . . Output

310, 610. . . First current mirror

312. . . First PMOS switch

320, 620. . . Second current mirror

314. . . First NMOS switch

68. . . Second comparator

601. . . First input

602. . . Second input

603. . . Output

612. . . Third PMOS switch

614. . . Third NMOS switch

K1, K2. . . PMOS transistor

K3, K4. . . NMOS transistor

K5. . . PMOS switch

K6. . . NMOS switch

V _DD . . . power source

I _up . . . recharging current

I _dn . . . Discharge current

UP, DN. . . control signal

C _gsp , C _gdp , C _gsn , C _gdn , C1 , C2 , C3. . . Parasitic capacitance

OUT, V _cont . . . Charge pump output

F _ref . . . Reference signal

F _out . . . output signal

V _tp , V _tn . . . Threshold voltage

M1. . . PMOS tuner

M2. . . First output PMOS transistor

M3. . . Second PMOS switch

M4. . . First output PMOS transistor

M5. . . First NMOS transistor

M6. . . First output NMOS transistor

M7. . . NMOS tuner

M8. . . Second NMOS switch

M9. . . Starting NMOS transistor

M10. . . First PMOS transistor

M12. . . Second output PMOS transistor

M16. . . Second output NMOS transistor

V _B1 . . . First bias

V _B2 . . . Second bias

UP1. . . First control signal

DN2. . . Second control signal

UP3. . . Third control signal

DN4. . . Fourth control signal

Figure 1 is a schematic diagram of a conventional charge pump circuit.

Figure 2 is a block diagram of the phase locked loop of the present invention.

Fig. 3 is a schematic view showing a charge pump circuit of the first embodiment of the present invention.

Fig. 4 is an explanatory view of the charge pump circuit of Fig. 3.

Fig. 5 is a schematic view showing a charge pump circuit of a second embodiment of the present invention.

Figure 6 is a schematic view showing a charge pump circuit of a third embodiment of the present invention.

Figure 7 is a schematic view showing a charge pump circuit of a fourth embodiment of the present invention.

300. . . Charge pump circuit

38. . . First comparator

301. . . First input

302. . . Second input

303. . . Output

310. . . First current mirror

312. . . First PMOS switch

314. . . First NMOS switch

320. . . Second current mirror

V _DD . . . power source

V _cont . . . Charge pump output

M1. . . PMOS tuner

M2. . . First output PMOS transistor

M4. . . First output PMOS transistor

M5. . . First NMOS transistor

M6. . . First output NMOS transistor

M7. . . NMOS tuner

M9. . . Starting NMOS transistor

M10. . . First PMOS transistor

V _B1 . . . First bias

V _B2 . . . Second bias

UP1. . . First control signal

DN2. . . Second control signal

Claims (6)

A charge pump circuit comprising: a first comparator having a first input terminal, a second input terminal and an output terminal coupled to the second input terminal of the first comparator; a MOS tuner having a source coupled to a voltage source and a gate for receiving a first bias voltage; a first current mirror comprising: a starting PMOS transistor having a source coupled to the voltage source and a gate coupled to the drain of the starting PMOS transistor; and a first output PMOS transistor having a gate coupled to the starting PMOS a gate of the transistor, and a drain coupled to the first input of the first comparator; a first N-type metal oxide semiconductor (NMOS) transistor having a drain coupled to the first a gate of the output PMOS transistor, a gate coupled to the output end of the first comparator, and a source coupled to the ground; a first PMOS switch having a drain coupled to the first a source of the output PMOS transistor, a source coupled to the drain of the PMOS tuner, and a gate for receiving a first control signal An NMOS tuner having a source coupled to ground and a gate for receiving a second bias voltage; a second current mirror comprising: a starting NMOS transistor having a source coupled Connected to the ground, and a gate coupled to the drain of the starting NMOS transistor; and a first output NMOS transistor having a gate coupled to the gate of the starting NMOS transistor, and a first PMOS transistor having a drain coupled to the gate of the first output NMOS transistor, a gate coupled to the first input terminal of the first comparator An output of the first comparator, and a source coupled to the voltage source, and a first NMOS switch having a drain coupled to the source of the first output NMOS transistor, a source The pole is coupled to the drain of the NMOS tuner and a gate for receiving a second control signal. The charge pump circuit of claim 1, wherein the first control signal is opposite to a logic potential of the second control signal. The charge pump circuit of claim 1, further comprising: a second PMOS switch having a drain coupled to the source of the starting PMOS transistor, a source coupled to the voltage source, and a gate coupled to the gate of the first NMOS transistor; and a second NMOS switch having a drain coupled to the source of the starting NMOS transistor, a source coupled to the ground And a gate coupled to the gate of the first PMOS transistor. The charge pump circuit of claim 1, further comprising: a second comparator having a first input coupled to the first input of the first comparator, a second input, and an output The second PMOS switch has a source coupled to the drain of the PMOS tuner and a gate for receiving a third control. And a third NMOS switch having a source coupled to the drain of the NMOS tuner and a gate for receiving a fourth control signal; wherein the first current mirror further includes a second An output PMOS transistor having a source coupled to the drain of the third PMOS switch, a drain coupled to the output of the second comparator, and a gate coupled to the first output a gate of the PMOS transistor; and the second current mirror further includes a second output NMOS transistor having a source coupled to the drain of the third NMOS switch, and a drain coupled to the first The drain of the second output PMOS transistor and a gate are coupled to the gate of the first output NMOS transistor. The charge pump circuit of claim 4, further comprising: a second PMOS switch having a drain coupled to the source of the starting PMOS transistor, a source coupled to the voltage source, and a gate coupled to the gate of the first NMOS transistor; and a second NMOS switch having a drain coupled to the source of the starting NMOS transistor, a source coupled to the ground And a gate coupled to the gate of the first PMOS transistor. The charge pump circuit of claim 4, wherein the first control signal is opposite to a logic potential of the second control signal, the first control signal is opposite to a logic potential of the third control signal, and the second control signal is It is opposite to the logic potential of the fourth control signal.