TWI530955B - Operation Method of Small Area Electron Removal Type Rewritable Read Only Memory Array - Google Patents

Description

Operation method of small area electronic erasing rewritable read-only memory array

The present invention relates to a memory array, and more particularly to a method of operating a small area electronic erase rewritable read-only memory array.

According to Complementary Metal Oxide Semiconductor (CMOS) process technology, it has become a common manufacturing method for application specific integrated circuits (ASICs). In today's computer information products, Flash and Electronically Erasable Programmable Read Only Memory (EEPROM) are non-volatile with electrical writing and erasing data. The memory function, and the data does not disappear after the power is turned off, so it is widely used in electronic products.

The non-volatile memory system is programmable to store charge to change the gate voltage of the transistor of the memory or to store the charge to leave the gate voltage of the transistor of the original memory. The erase operation removes the charge stored in the non-volatile memory, causing the non-volatile memory to return to the gate voltage of the transistor of the original memory. For the current non-volatile memory, the circuit diagram and circuit layout are shown in Figures 1 and 2, respectively. The non-volatile memory is a memory composed of many memory cells, each memory crystal in the figure. The cell comprises a transistor 10 and a capacitor structure 12, and a binary line is arranged between the memory cells of each two adjacent bytes. This will increase the area cost. FIG. 3 is a cross-sectional view showing the structure of each memory cell. As can be seen from the figure, the capacitor structure 12 is disposed on one side of the transistor 10. Due to such a structure, a large area is also generated, thereby increasing the cost.

Therefore, the applicant of the present invention has developed a small-area electronic erasing rewritable read-only memory array in response to the above-mentioned prior art, and further proposed a low current and low voltage operation method based on the architecture, which can simultaneously rewrite a large number of memories. Unit cell.

The main object of the present invention is to provide a small area electronic erasing rewritable read-only memory array operation method, which has a small area and low cost electronic erasing rewritable read-only memory architecture, utilizing special The bias mode achieves a large number of memory cell writing and erasing functions.

To achieve the above object, the present invention provides a small area electronic erasing rewritable read-only memory array operation method, which is applied to a small area electronic erasing rewritable read-only memory array, and the small area electronic erasing type can be The copy-reading memory array includes a plurality of parallel bit lines, word lines and common source lines, and the bit lines are divided into complex array bit lines, which comprise a first group of bit lines and a second The bit line is grouped, and the word line and the bit line are perpendicular to each other, and include a first word line. The common source line and the word line are parallel to each other and include a first common source line. There is a plurality of sub-memory arrays, each sub-memory array is connected to two sets of bit lines, a word line and a common source line, and each sub-memory array comprises a first, second, third, fourth memory crystal Cell. The first memory cell is connected to the first group of bit lines, the first common source line and the first word line, and the second memory cell is connected to the second group of bit lines, the first common source line and the first word line, first The second memory cells are symmetrically arranged with each other and are located on the same side of the first common source line. The third memory cell is connected to the first group of bit lines, the first common source line and the first word line, And symmetrically arranged with the first memory cell by using the first common source line as an axis. The fourth memory cell is connected to the second group of bit lines, the first common source line and the first word line, and is symmetrically arranged with the second memory cell by using the first common source line as an axis, and the third and fourth memory crystals are further The cells are symmetrically arranged with each other and are located on opposite sides of the first common source line from the first and second memory cells.

Wherein, the first, second, third, and fourth memory cells each comprise an N-type field effect transistor, and the first, second, third, and fourth memory cells are all used as operational memory cells, All operating memory cells are operated by applying a substrate voltage V _sub to all P-type substrates or P-type well regions connected to the memory cell, and all the bit lines, word lines, and totals connected to the memory cells are connected. The source line applies a bit voltage V _b , a word voltage V _w , and a common source voltage V _s to perform writing or erasing. Wherein, when writing, the condition that V _sub = ground, V _S = V _b =0, and V _w = high voltage (HV) is satisfied; when erasing, it is satisfied that V _sub = ground, V _s = V _b = high voltage, and V _w = the condition of floating.

In addition, when the field effect transistors of the first, second, third, and fourth memory cells are P-type, the present invention also provides an operation method of another small area electronic erasing rewritable read-only memory array. when all operations selected memory cell is operated, it is operated by all the memory cell connected to the N-type substrate or N-type well region Shijia Ji substrate voltage V _sub, and the cell bit line connected to all of the working memory, the word line The common source line applies a bit voltage V _b , a word voltage V _w , and a common source voltage V _s to perform writing or erasing. Wherein, when writing, the condition that V _sub = high voltage (HV), V _w =0, and V _s = V _b = high voltage is satisfied; when erasing, it is satisfied that V _sub = high voltage, V _w = floating And the condition of V _s =V _b =0.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

10‧‧‧Optoelectronics

12‧‧‧Capacitor structure

14‧‧‧ bit line

16‧‧‧ bit line

18‧‧‧The first group of bit lines

19‧‧‧Second group of bit lines

20‧‧‧ word line

22‧‧‧First word line

24‧‧‧Common source line

26‧‧‧The first common source line

28‧‧‧Sub Memory Array

30‧‧‧First memory cell

32‧‧‧Second memory cell

34‧‧‧ Third memory cell

36‧‧‧The fourth memory cell

38‧‧‧ Field Effect Crystal

40‧‧‧ Capacitance

42‧‧‧ Field Effect Crystal

44‧‧‧ Capacitance

46‧‧‧ Field Effect Crystal

48‧‧‧ Capacitance

50‧‧‧ field effect transistor

52‧‧‧ Capacitance

54‧‧‧gate contacts

56‧‧‧汲pole contacts

58‧‧‧N type field effect transistor

60‧‧‧P type semiconductor substrate

62‧‧‧Electrical gate

64‧‧‧ Capacitance

66‧‧‧P type field effect transistor

68‧‧‧N type semiconductor substrate

70‧‧‧ Conductive gate

72‧‧‧ Capacitance

Figure 1 is a schematic diagram of a prior art non-volatile memory circuit.

Figure 2 is a schematic diagram of the circuit layout of Figure 1.

Figure 3 is a cross-sectional view of the memory cell structure of the prior art non-volatile memory.

Figure 4 is a circuit diagram showing a first embodiment of the present invention.

Figure 5 is a schematic diagram showing the circuit layout of the first embodiment of the present invention.

Figure 6 is a circuit diagram of a sub-memory array of the first embodiment of the present invention.

Figure 7 is a cross-sectional view showing the structure of an N-type field effect transistor and a capacitor of the present invention.

Figure 8 is a cross-sectional view showing the structure of a P-type field effect transistor and a capacitor of the present invention.

Figure 9 is a circuit diagram showing a second embodiment of the present invention.

Figure 10 is a schematic diagram showing the circuit layout of the second embodiment of the present invention.

Figure 11 is a circuit diagram of a sub-memory array of a second embodiment of the present invention.

Please refer to FIG. 4 and FIG. 5 at the same time to introduce the first embodiment. The present invention includes a plurality of parallel bit lines 14 that are divided into complex array bit lines 16, which include a first set of bit lines 18 and a second set of bit lines 19, Both the first set of bit lines 18 and the second set of bit lines 19 comprise a single bit line 14. There is also a plurality of parallel word lines 20 that are perpendicular to the bit line 14 and that comprise a first word line 22. Parallel to the word line 20 are a plurality of parallel common source lines 24 comprising a first common source line 26. The bit line 14, the word line 20 and the common source line 24 are connected to a plurality of sub-memory arrays 28, that is, 2x2 bit memory cells. Each sub-memory array 28 is connected to two sets of bit lines 16, two word lines 20 and a common source line 24, and each sub-memory array 28 is located between two adjacent sets of bit lines 16. Since each sub-memory array 28 is connected to bit line 16, two word line 20, The connection relationship of the common source line 24 is very similar, and the following is stated in the same place.

Referring to FIGS. 5 and 6, each sub-memory array 28 includes a first, second, third, and fourth memory cells 30, 32, 34, 36 and is located in the first set of bit lines 18. Between the second set of bit lines 19. The first memory cell 30 is connected to the bit line 14 of the first group of bit lines 18, the first common source line 26 and the first word line 22, and the second memory cell 32 is connected to the bit of the second group of bit lines 19. The line 14, the first common source line 26 and the first word line 22, the first and second memory cells 32, 34 are symmetrically arranged on each other and on the same side of the first common source line 26. The third memory cell 34 connects the bit line 14 of the first group of bit lines 18, the first common source line 26 and the first word line 22, and the first common source line 26 is the axis, and the first memory cell 30 symmetric configuration. The fourth memory cell 36 is connected to the bit line 14 of the second group of bit lines 19, the first common source line 26 and the first word line 22, and the first common source line 26 is the axis, and the second memory cell 32 symmetrically arranged, the fourth memory cell 36 is symmetrically arranged with the third memory cell 34, and the first and second memory cells 30, 32 and the third and fourth memory cells 34, 36 are respectively located in the first The two sides of the source line 26 are different.

Since the first, second, third, and fourth memory cells 30, 32, 34, 36 are arranged in a symmetrical manner and are both connected to the first word line 22, the same contact can be shared by the first word line 22. In addition, in the adjacent two-child memory array 28, the two third memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same contact; and the second memory cells 36 are adjacent to each other. And the same bit line 14 is connected to share the same contact point, and the common contact arrangement mode can be used to reduce the overall layout area.

The first memory cell 30 further includes a field transistor 38 and a capacitor 40. The field effect transistor 38 has a conductive gate, and the drain of the field effect transistor 38 is connected to the bit line of the first group of bit lines 18. 14. The source is coupled to the first common source line 26. The bias voltage V _w of the first word line 22 is coupled to the field effect transistor 38 via a capacitor 40 formed of the same polysilicon as the conductive gate of the field effect transistor 38. The transistor 38 receives the bias voltages V _b , V _s of the bit line 14 of the first set of bit lines 18 and the first common source line 26 to write data or field the conductive gate of the field effect transistor 38. The data of the conductive gate of the effect transistor 38 is erased.

The second memory cell 32 further includes a field transistor 42 and a capacitor 44. The field effect transistor 42 has a conductive gate, and the drain of the field effect transistor 42 is connected to the bit line of the second group of bit lines 19. 14. The source is coupled to the first common source line 26. The bias voltage V _w of the first word line 22 is coupled to the field effect transistor 42 via a capacitor 44 formed of the same polysilicon as the conductive gate of the field effect transistor 42. The capacitor 40 is directly connected to be placed between the field effect transistor 38 and the field effect transistor 42. The field effect transistor 42 receives the bias voltages V _b , V _s of the bit line 14 of the second group of bit lines 19 and the first common source line 26 to write data to the conductive gate of the field effect transistor 42 or The data of the conductive gate of the field effect transistor 42 is erased.

The third memory cell 34 further includes a field transistor 46 and a capacitor 48. The field effect transistor 46 has a conductive gate, and the drain of the field effect transistor 46 is connected to the bit line of the first group of bit lines 18. 14. The source is coupled to the first common source line 26 to share the same contact with the first memory cell 30. The bias voltage V _w of the first word line 22 is formed by the same polysilicon as the conductive gate of the field effect transistor 46. The capacitor 48 is coupled to the field effect transistor 46. The capacitor 48 and the field effect transistor 46 are symmetrical with the capacitor 40 and the field effect transistor 38, respectively, with the first common source line 26 as the axis. The field effect transistor 46 receives the bias voltages V _b , V _s of the bit line 14 of the first group of bit lines 18 and the first common source line 26 to write data to the conductive gate of the field effect transistor 46 or The data of the conductive gate of the field effect transistor 46 is erased.

The fourth memory cell 36 further includes a field transistor 50 and a capacitor 52. The field effect transistor 50 has a conductive gate, and the drain of the field effect transistor 50 is connected to the bit line of the second group of bit lines 19. 14. The source is coupled to the first common source line 26 to share the same contact with the second memory cell 32. The bias voltage V _w of the first word line 22 is formed by the same polysilicon as the conductive gate of the field effect transistor 50. The capacitor 52 is coupled to the field effect transistor 50. The capacitor 52 and the field effect transistor 50 are symmetrical with the capacitor 44 and the field effect transistor 42 respectively, and the capacitor 52 and the capacitor 48 are directly connected. Connected to be located between field effect transistor 50 and field effect transistor 46. The field effect transistor 50 receives the bias voltages V _b , V _s of the bit line 14 of the second group of bit lines 19 and the first common source line 26 to write data to the conductive gate of the field effect transistor 50 or The data of the conductive gate of the field effect transistor 50 is erased.

Since the capacitors 40, 44, 48, 52 are all connected to the first word line 22, the same gate contact 54 can be shared by the first word line 22. In addition, in the adjacent two sub-memory arrays 28, the two field effect transistors 46 are adjacent to each other and connected to the same bit line 14 to share the same drain contact 56; the two field effect transistors 50 are adjacent to each other. Also, the same bit line 14 is connected to share the same drain contact 56. With this common contact arrangement, the overall layout area can be reduced, thereby greatly reducing the manufacturing cost.

Referring to FIG. 4, the field effect transistors 38, 42, 46, 50 may all be N-type field effect transistors located in a P-type substrate or a P-type well region, or may be located in an N-type substrate or an N-type well. The P-type field effect transistor in the region, and the operation mode of the present invention is different according to the N-type or P-type field effect transistor. The following description shows that the field effect transistor 38, 42, 46, 50 is the N-type field effect electric power. The way the crystal operates.

The first, second, third, and fourth memory cells 30, 32, 34, and 36 are all used as an operational memory cell, and the present invention selects all of the operational memory cells for writing or erasing operations. The operation mode of the first embodiment is as follows. With the following operation mode, a large number of memory cells can be simultaneously written under conditions of low voltage and low current.

The substrate voltage V _{sub is} applied to all P-type substrates or P-type well regions in which the memory cell is connected, and the bit voltage V is applied to the bit lines 14 , the word lines 20 , and the common source lines 24 connected to all the memory cells. _b , word voltage V _w , common source voltage V _s , and satisfy the following conditions: when writing, V _sub is grounded, V _s = V _b =0, and V _w = high voltage (HV); V _sub ground, V _s = V _b = high voltage, and V _w = floating.

38,42,46,50 spot effect transistor is a P-type field effect transistor, the memory cell in accordance with the above definition of the voltage, but the N-well or N-type substrate Shijia Ji substrate voltage V _sub, and a write When V _sub = high voltage (HV), V _w =0, and V _s = V _b = high voltage; when erasing, V _sub = high voltage, V _w = floating, and V _s = V _b =0.

Since the same bit line 14 is connected to the two memory cells for the same sub-memory array 28, when writing or erasing, the memory cell of one tuple is operated once instead of a single memory crystal. Cell. By using the above bias method, the function of byte writing and byte erase can be achieved in the non-volatile memory without adding an isolation transistor.

The structural cross-sectional views of the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44, 48, 52 are described below, and an N-type field effect transistor is taken as an example. Referring to FIG. 7, the N-type field effect transistor 58 is disposed in a P-type semiconductor substrate 60 as a semiconductor substrate, and has a conductive gate 62. The capacitor 64 is simultaneously horizontally disposed with the N-type field effect transistor 58. In the P-type semiconductor substrate 60, the capacitor 64 is a capacitor of the same polysilicon as the conductive gate. When the semiconductor substrate is N-type, a P-type well region may be disposed in the substrate, and the N-type field effect transistor 58 may be disposed in the P-type well region.

Similarly, when the cross-sectional views of the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44, 48, 52 are exemplified by a P-type field effect transistor, as shown in Fig. 8, the P-type field effect transistor 66 is disposed in an N-type semiconductor substrate 68 as a semiconductor substrate, and has a conductive gate 70, and a capacitor 72 is simultaneously disposed horizontally with the P-type field effect transistor 66 in the N-type semiconductor substrate 68, and the capacitor 72 is The same polysilicon capacitor as the conductive gate. When the semiconductor substrate is P-type, an N-type well region may be disposed in the substrate, and the P-type field effect transistor 66 may be disposed in the N-type well region.

A second embodiment is provided below. Please refer to FIG. 9 , FIG. 10 and FIG. 11 simultaneously. This second embodiment differs from the first embodiment only in that each group of bit lines 16 includes two bit lines 14 , so the first group of bit lines 18 . Also included are two bit lines 14, which are respectively connected to the first and third memory cells 30, 34 of the same sub-memory array 28; the second set of bit lines 19 comprise two bit lines 14, which are respectively connected to the same The second and fourth memory cells 32, 36 of the sub-memory array 28. Further, in the adjacent two-child memory array 28, the two third memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same contact, and the second and fourth memory cells 36 are adjacent to each other and connected to each other. Bit line 14 to share the same contact. In other words, the field effect transistors 46 of the second memory cell 34 are adjacent to each other and connected to the same bit line 14 to share the same gate contact 56, and the field effect transistors 50 of the second memory cell 36 are mutually Adjacent and connected to the same bit line 14 to share the same bungee contact 56, the overall layout area can be reduced.

Referring to FIG. 9, the field effect transistors 38, 42, 46, 50 may all be N-type field effect transistors located in the P-type substrate or the P-type well region, or in the N-type substrate or the N-type well region. In the case of the P-type field effect transistor, the operation mode of the second embodiment differs depending on the N-type or P-type field effect transistor. The following describes the field effect transistor 38, 42, 46, 50 as the N-type field effect. The mode of operation of the transistor.

The first, second, third, and fourth memory cells 30, 32, 34, and 36 are all used as an operational memory cell, and the present invention selects all of the operational memory cells for writing or erasing operations. The operation mode of the second embodiment is as follows. With the following operation mode, a large number of memory cells can be simultaneously written under conditions of low voltage and low current.

_Sub Shijia Ji bottom voltage V P-type substrate or on a P-type well region of the memory cell connected to all _operations, and the memory cell connected to the bit line 14 all operations, the word lines 20, 24 are respectively applied to common source line voltage V bit _b , word voltage V _w , common source voltage V _s , and satisfy the following conditions: when writing, satisfy V _sub = ground, V _s = V _b =0, and V _w = high voltage (HV); V _sub = ground, V _s = V _b = high voltage, and V _w = floating.

38,42,46,50 spot effect transistor is a P-type field effect transistor, the memory cell in accordance with the above definition of the voltage, but the N-well or N-type substrate Shijia Ji substrate voltage V _sub, and a write When V _sub = high voltage (HV), V _w =0, and V _s = V _b = high voltage; when erasing, V _sub = high voltage, V _w = floating, and V _s = V _b =0.

By using the above bias method, the function of writing and erasing the non-volatile memory using the upper byte can be achieved without the addition of the isolation transistor.

When the memory cell is in the write operation, its voltage is applied to a stable high voltage by a charge pump of about 2.5 volts or 3.3 volts, but the voltage difference between the drain and the source causes 汲The current between the pole and the source is generated, and the high voltage is changed. When the current is larger, the higher the fluctuation of the high voltage is, the stronger the required charge pump is, the larger the layout area is, and the structure of the flash memory is usually When programmed, the bias voltage is: the gate capacitance and the drain are applied with high voltage, the source is grounded, and the current between the drain and the source is about 500u amps/bit. In the present invention, when all the memory cells are selected for writing operation, the gate capacitance is increased by a high voltage; when the erasing operation is performed, a high voltage is applied to both the source and the drain, and the voltages at the two ends are respectively about 5 Volts and 3.3 volts are added to about 9 volts and 7 volts, which is much lower than the withstand voltage of the transistor. The operating method of the present invention can erase all the memory cells at one time under the bias condition, and can also perform the stylization of all the memory cells together without load, thereby reducing the charge pump and improving the efficiency.

As for the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44 of the second embodiment, The structural cross-sectional views of 48 and 52 are the same as those of the first embodiment, and therefore will not be described again.

In summary, the present invention is capable of erasing or writing all memory cells together with a bias voltage in an electronic erasing rewritable read-only memory architecture having a small area and a low cost. Achieve a lot of replication features.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

14‧‧‧ bit line

16‧‧‧ bit line

18‧‧‧The first group of bit lines

19‧‧‧Second group of bit lines

20‧‧‧ word line

24‧‧‧Common source line

26‧‧‧The first common source line

28‧‧‧Sub Memory Array

30‧‧‧First memory cell

32‧‧‧Second memory cell

34‧‧‧ Third memory cell

36‧‧‧The fourth memory cell

38‧‧‧ Field Effect Crystal

40‧‧‧ Capacitance

42‧‧‧ Field Effect Crystal

44‧‧‧ Capacitance

46‧‧‧ Field Effect Crystal

48‧‧‧ Capacitance

50‧‧‧ field effect transistor

52‧‧‧ Capacitance

Claims (22)

A small area electronic erasing rewritable read-only memory array operation method, the small area electronic erasing rewritable read-only memory array comprises: a plurality of parallel bit lines, which are divided into complex array bit lines The set of bit lines includes a first set of bit lines and a second set of bit lines; a plurality of parallel word lines are perpendicular to the bit lines and include a first word line; a parallel common source line parallel to the word lines and including a first common source line; and a plurality of sub-memory arrays, each of the sub-memory arrays connecting two sets of the bit lines, one word a line and a common source line, each of the sub-memory arrays comprising: a first memory cell connecting the first set of bit lines, the first common source line and the first word line; and a first a second memory cell connected to the second group of bit lines, the first common source line and the first word line, the first and second memory cells being symmetrically arranged with each other and located at the first common source line a third memory cell connected to the first group of bit lines, the first common source line and the first word line And aligning with the first memory cell with the first common source line as an axis; and a fourth memory cell connecting the second group of bit lines, the first common source line and the first word line And symmetrically arranging the second common memory cell with the first common source line as an axis, and the third and fourth memory cells are symmetrically arranged with each other, and the first and second memory cells are located at the first The first, second, third, and fourth memory cells each include an N-type field effect transistor located in the P-type substrate or the P-type well region, and the first The second, third, and fourth memory cells are all operated as a memory cell, and when all of the operational memory cells are selected for operation, the method of operation is characterized in that all of the operational memory cells are connected Applying a substrate voltage V _{sub to} the P-type substrate or the P-type well region, and applying a bit voltage V _{b to} the bit line, the word line, and the common source line respectively connected to the operation memory cell Voltage V _w , a common source voltage V _s , and satisfying the following conditions: when writing, satisfy V _sub = ground; V _s = V _b =0; and V _w = high voltage (HV); and when erasing, satisfy V _sub = ground; V _s = V _b = high voltage; and V _w = floating. The method of operating a small area electronic erasable rewritable read-only memory array according to claim 1, wherein each of the sub-memory arrays is located between two adjacent sets of the bit lines. The method for operating a small-area electronic erasable rewritable read-only memory array according to claim 1, wherein the first, second, third, and fourth memory cells are connected to the first word line for sharing The same contact. The method for operating a small-area electronic erasable rewritable read-only memory array according to claim 1, wherein the first set of bit lines includes a bit line connecting the first and third memory crystals And the second set of bit lines also includes a bit line connecting the second and fourth memory cells. The method for operating a small-area electronic erasable rewritable read-only memory array according to claim 1, wherein the first set of bit lines includes two bit lines, which are respectively connected to the first and third memories. The unit cell, and the second group of bit lines also includes two bit lines, which are respectively connected to the second and fourth memory cells. The method of operating a small area electronic erasable rewritable read-only memory array according to claim 4, wherein the two third memory cells are adjacent to each other and connected to each other in the adjacent sub-memory array. The same bit line is connected to share the same contact, and the two fourth memory cells are adjacent to each other and connected to the same bit line to share the same contact. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the N-type field effect transistor of the first memory cell has a drain, a source, and a a conductive gate, and the drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive with the N-type field effect transistor One of the gates having the same polysilicon formation is capacitively coupled to the N-type field effect transistor, and the N-type field effect transistor receives a bias voltage between the first set of bit lines and the first common source line, and the conductive gate is performed Write data or erase the data of the conductive gate. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the N-type field effect transistor of the second memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the N-type field effect transistor One of the extremely identical polysilicon formations is capacitively coupled to the N-type field effect transistor, the N-type field effect transistor receiving a bias voltage of the second set of bit lines and the first common source line, writing the conductive gate Enter the data or erase the data of the conductive gate. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the N-type field effect transistor of the third memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the N-type field effect transistor One of the most identical polysilicon formations is capacitively coupled to the N-type field effect transistor, the N-type field effect transistor receiving a bias voltage of the first set of bit lines and the first common source line, writing the conductive gate Entry information or the guide The data of the electric gate is erased. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the N-type field effect transistor of the fourth memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the N-type field effect transistor One of the extremely identical polysilicon formations is capacitively coupled to the N-type field effect transistor, the N-type field effect transistor receiving a bias voltage of the second set of bit lines and the first common source line, writing the conductive gate Enter the data or erase the data of the conductive gate. The method of operating a small-area electronic erasing rewritable read-only memory array according to claim 7, wherein the N-type field effect transistor and the capacitor are horizontally disposed in a semiconductor substrate. A small area electronic erasing rewritable read-only memory array operation method, the small area electronic erasing rewritable read-only memory array comprises: a plurality of parallel bit lines, which are divided into complex array bit lines The set of bit lines includes a first set of bit lines and a second set of bit lines; a plurality of parallel word lines are perpendicular to the bit lines and include a first word line; a parallel common source line parallel to the word lines and including a first common source line; and a plurality of sub-memory arrays, each of the sub-memory arrays connecting two sets of the bit lines, one word a line and a common source line, each of the sub-memory arrays comprising: a first memory cell connecting the first set of bit lines, the first common source line and the first word line; and a first a second memory cell connected to the second group of bit lines, the first common source line and the first word line, the first and second memory cells being symmetrically arranged with each other and located at the first common source line a third memory cell connected to the first group of bit lines, the first common source line and the first word line And aligning with the first memory cell with the first common source line as an axis; and a fourth memory cell connecting the second group of bit lines, the first common source line and the first word line And symmetrically arranging the second common memory cell with the first common source line as an axis, and the third and fourth memory cells are symmetrically arranged with each other, and the first and second memory cells are located at the first The first, second, third, and fourth memory cells each include a P-type field effect transistor located in the N-type substrate or the N-type well region, and the first The second, third, and fourth memory cells are all operated as a memory cell, and when all of the operational memory cells are selected for operation, the method of operation is characterized in that all of the operational memory cells are connected N-type substrate is applied to the N-type well region or a substrate voltage V _sub, and all the operation of the bit line connected to the memory cell, the word line, are respectively applied to the common source line one yuan voltage V _b, the word The voltage V _w , a common source voltage V _s , and satisfying the following conditions: when writing, satisfying V _sub high voltage (HV); V _s = V _b = high voltage (H) V); and V _w =0; and when erasing, satisfy V _sub = high voltage (HV); V _s = V _b =0; and V _w = floating. The method of operating a small area electronic erasable rewritable read-only memory array according to claim 12, wherein each of the sub-memory arrays is located between two adjacent sets of the bit lines. The method for operating a small area electronic erasable rewritable read-only memory array according to claim 12, wherein the first, second, third, and fourth memory cells are connected to the first word line for sharing The same contact. The operator of the small area electronic erasing rewritable read-only memory array as claimed in claim 12 The first group of bit lines includes a bit line connecting the first and third memory cells, and the second group of bit lines also includes a bit line, which is connected to the bit line The second and fourth memory cells. The method for operating a small area electronic erasable rewritable read-only memory array according to claim 12, wherein the first set of bit lines includes two bit lines, which are respectively connected to the first and third memories. The unit cell, and the second group of bit lines also includes two bit lines, which are respectively connected to the second and fourth memory cells. The method of operating a small-area electronic erasable rewritable read-only memory array according to claim 15 or 16, wherein in the adjacent two sub-memory arrays, the two third memory cells are adjacent to each other and connected The same bit line is shared to share the same contact, and the two fourth memory cells are adjacent to each other and connected to the same bit line to share the same contact. The method of operating a small-area electronic erasing rewritable read-only memory array according to claim 12, wherein the P-type field effect transistor of the first memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the P-type field effect transistor One of the extremely identical polysilicon formations is capacitively coupled to the P-type field effect transistor, the P-type field effect transistor receiving a bias voltage of the first set of bit lines and the first common source line, writing the conductive gate Enter the data or erase the data of the conductive gate. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 12, wherein the P-type field effect transistor of the second memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the P-type field effect transistor Very identical polysilicon Forming a capacitive coupling to the P-type field effect transistor, the P-type field effect transistor receiving a bias voltage of the second group of bit lines and the first common source line, writing the data to the conductive gate or The information of the conductive gate is erased. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 12, wherein the P-type field effect transistor of the third memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the P-type field effect transistor One of the extremely identical polysilicon formations is capacitively coupled to the P-type field effect transistor, the P-type field effect transistor receiving a bias voltage of the first set of bit lines and the first common source line, writing the conductive gate Enter the data or erase the data of the conductive gate. The method for operating a small-area electronic erasing rewritable read-only memory array according to claim 12, wherein the P-type field effect transistor of the fourth memory cell has a drain, a source, and a conductive a gate, and the drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is via the conductive gate of the P-type field effect transistor One of the extremely identical polysilicon formations is capacitively coupled to the P-type field effect transistor, the P-type field effect transistor receiving a bias voltage of the second set of bit lines and the first common source line, writing the conductive gate Enter the data or erase the data of the conductive gate. The method of operating a small area electronic erasable rewritable read-only memory array according to claim 18, 19, 20 or 21, wherein the P-type field effect transistor and the capacitor are horizontally disposed in a semiconductor substrate.