TWI415251B - Small area of ​​electronic erasure can be rewritten read only memory array - Google Patents

Abstract

The present invention discloses a small size electrically erasable programmable read only memory array, which comprises a plurality of parallel byte lines, word lines and common source lines. These byte lines are divided as a plurality of byte line sets, which includes a first set and a second set of byte lines. The word lines include a first word line. The common source line includes a fist common source line. Furthermore, there are a plurality of sub-memory arrays, and each sub-memory array includes a first, a second, a third, and a fourth memory cells which are respectively connected with two sets of byte lines, one word line and a common source line; wherein, the first and the second memory cells are symmetrically arranged, and the third and the fourth memory cells are symmetrically arranged, and the first and second memory cells, and the third and the fourth memory cells are respectively arranged and symmetrical to the first common line. The present invention can greatly reduce the area cost, and realize the byte write function.

Description

Small area electronic erasing rewritable read-only memory array

The present invention relates to a memory array, and more particularly to a small area electronic erase rewritable read-only memory array.

According to Complementary Metal Oxide Semiconductor (CMOS) process technology, it has become a common manufacturing method for application specific integrated circuits (ASICs). In today's computer information products, Flash and Electronically Erasable Programmable Read Only Memory (EEPROM) are non-volatile with electrical writing and erasing data. The memory function, and the data does not disappear after the power is turned off, so it is widely used in electronic products.

The non-volatile memory system is programmable to store charge to change the gate voltage of the transistor of the memory or to store the charge to leave the gate voltage of the transistor of the original memory. The erase operation removes the charge stored in the non-volatile memory, causing the non-volatile memory to return to the gate voltage of the transistor of the original memory. For the current non-volatile memory, the circuit diagram and circuit layout are shown in Figures 1 and 2, respectively. The non-volatile memory is a memory composed of many memory cells, each memory crystal in the figure. The cell comprises a transistor 10 and a capacitor structure 12, and a memory line between two adjacent ones of the memory cells is provided with a two-bit line, which increases the area cost. FIG. 3 is a cross-sectional view showing the structure of each memory cell. As can be seen from the figure, the capacitor structure 12 is disposed on one side of the transistor 10. Due to such a structure, a large area is also generated, thereby increasing the cost.

Accordingly, the present invention has been directed to a small area electronic erasable rewritable read-only memory array in order to solve the above problems.

The main object of the present invention is to provide a small-area electronic erasing rewritable read-only memory array, which uses a method in which a gate contact and a drain contact are shared to reduce the cell area and thereby reduce the cost.

To achieve the above objective, the present invention provides a small area electronic erasing rewritable read-only memory array comprising a plurality of parallel bit lines, word lines and common source lines, and the bit lines are divided into complex array bits. a line comprising a first set of bit lines and a second set of bit lines, wherein the word lines and the bit lines are perpendicular to each other and comprising a first word line, the common source line and the word line being parallel to each other, and Contains a first common source line. There is a plurality of sub-memory arrays, each sub-memory array is connected to two sets of bit lines, a word line and a common source line, and each sub-memory array comprises a first, second, third, fourth memory crystal Cell. The first memory cell is connected to the first group of bit lines, the first common source line and the first word line, and the second memory cell is connected to the second group of bit lines, the first common source line and the first word line, first The second memory cells are symmetrically arranged with each other and are located on the same side of the first common source line. The third memory cell is connected to the first group of bit lines, the first common source line and the first word line, and is symmetrically arranged with the first memory cell with the first common source line as an axis. The fourth memory cell is connected to the second group of bit lines, the first common source line and the first word line, and is symmetrically arranged with the second memory cell by using the first common source line as an axis, and the third and fourth memory crystals are further The cells are symmetrically arranged with each other and are located on opposite sides of the first common source line from the first and second memory cells.

For a better understanding and understanding of the structural features and the achievable effects of the present invention, please refer to the preferred embodiment and the detailed description.

Please refer to FIG. 4 and FIG. 5 at the same time to introduce the first embodiment. The present invention includes a plurality of parallel bit lines 14 that are divided into complex array bit lines 16, which include a first set of bit lines 18 and a second set of bit lines 19, Both the first set of bit lines 18 and the second set of bit lines 19 comprise a single bit line 14. There is also a plurality of parallel word lines 20 that are perpendicular to the bit line 14 and that comprise a first word line 22. Parallel to the word line 20 are a plurality of parallel common source lines 24 comprising a first common source line 26. The bit line 14, the word line 20 and the common source line 24 are connected to a plurality of sub-memory arrays 28, that is, 2x2 bit memory cells. Each sub-memory array 28 is connected to two sets of bit lines 16, two word lines 20 and a common source line 24, and each sub-memory array 28 is located between two adjacent sets of bit lines 16. Since the connection relationship between each sub-memory array 28 and the bit line 16, the second word line 20, and the common source line 24 is very similar, the following is stated in the same place.

Referring to FIGS. 5 and 6, each sub-memory array 28 includes a first, second, third, and fourth memory cells 30, 32, 34, 36 and is located in the first set of bit lines 18. Between the second set of bit lines 19. The first memory cell 30 is connected to the bit line 14 of the first group of bit lines 18, the first common source line 26 and the first word line 22, and the second memory cell 32 is connected to the bit of the second group of bit lines 19. The line 14, the first common source line 26 and the first word line 22, the first and second memory cells 32, 34 are symmetrically arranged on each other and on the same side of the first common source line 26. The third memory cell 34 connects the bit line 14 of the first group of bit lines 18, the first common source line 26 and the first word line 22, and the first common source line 26 is the axis, and the first memory cell 30 symmetric configuration. The fourth memory cell 36 is connected to the bit line 14 of the second group of bit lines 19, the first common source line 26 and the first word line 22, and the first common source line 26 is the axis, and the second memory cell 32 symmetrically arranged, the fourth memory cell 36 is symmetrically arranged with the third memory cell 34, and the first and second memory cells 30, 32 and the third and fourth memory cells 34, 36 are respectively located in the first The two sides of the source line 26 are different.

Since the first, second, third, and fourth memory cells 30, 32, 34, 36 are arranged in a symmetrical manner and are both connected to the first word line 22, the same contact can be shared by the first word line 22. In addition, in the adjacent two-child memory array 28, the two third memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same contact; and the second memory cells 36 are adjacent to each other. And the same bit line 14 is connected to share the same contact point, and the common contact arrangement mode can be used to reduce the overall layout area.

The first memory cell 30 further includes a field transistor 38 and a capacitor 40. The field effect transistor 38 has a conductive gate, and the drain of the field effect transistor 38 is connected to the bit line of the first group of bit lines 18. 14. The source is coupled to the first common source line 26. The bias of the first word line 22 is coupled to the field effect transistor 38 via a capacitor 40 formed of the same polysilicon as the conductive gate of the field effect transistor 38. 38 receiving the bias of the bit line 14 of the first set of bit lines 18 and the first common source line 26 to write data to the conductive gate of the field effect transistor 38 or to electrically switch the field effect transistor 38. Extreme data is erased.

The second memory cell 32 further includes a field transistor 42 and a capacitor 44. The field effect transistor 42 has a conductive gate, and the drain of the field effect transistor 42 is connected to the bit line of the second group of bit lines 19. 14. The source is coupled to the first common source line 26. The bias of the first word line 22 is coupled to the field effect transistor 42 via a capacitor 44 formed of the same polysilicon as the conductive gate of the field effect transistor 42. The capacitor 44 and the capacitor 40 is directly connected to be located between the field effect transistor 38 and the field effect transistor 42. The field effect transistor 42 receives the bias voltage of the bit line 14 of the second group of bit lines 19 and the first common source line 26 to write data to the conductive gate of the field effect transistor 42 or to apply a field effect transistor. The data of the conductive gate of 42 is erased.

The third memory cell 34 further includes a field transistor 46 and a capacitor 48. The field effect transistor 46 has a conductive gate, and the drain of the field effect transistor 46 is connected to the bit line of the first group of bit lines 18. 14. The source is coupled to the first common source line 26 to share the same contact with the first memory cell 30. The bias of the first word line 22 is formed by a capacitor formed by the same polysilicon as the conductive gate of the field effect transistor 46. 48 is coupled to the field effect transistor 46. The capacitor 48 and the field effect transistor 46 are axially aligned with the capacitor 40 and the field effect transistor 38, respectively, with the first common source line 26 as the axis. The field effect transistor 46 receives the bias voltage of the bit line 14 of the first set of bit lines 18 and the first common source line 26 to write data to the conductive gate of the field effect transistor 46 or to apply a field effect transistor. The data of the conductive gate of 46 is erased.

The fourth memory cell 36 further includes a field transistor 50 and a capacitor 52. The field effect transistor 50 has a conductive gate, and the drain of the field effect transistor 50 is connected to the bit line of the second group of bit lines 19. 14. The source is coupled to the first common source line 26 to share the same contact with the second memory cell 32. The bias of the first word line 22 is formed by a capacitor formed by the same polysilicon as the conductive gate of the field effect transistor 50. The capacitor 52 is coupled to the field effect transistor 50. The capacitor 52 and the field effect transistor 50 are symmetrical with the capacitor 44 and the field effect transistor 42 respectively, and the capacitor 52 is directly connected to the capacitor 48. It is located between the field effect transistor 50 and the field effect transistor 46. The field effect transistor 46 receives the bias voltage of the bit line 14 of the first set of bit lines 18 and the first common source line 26 to write data to the conductive gate of the field effect transistor 46 or to apply a field effect transistor. The data of the conductive gate of 46 is erased.

Since the capacitors 40, 44, 48, 52 are all connected to the first word line 22, the same gate contact 54 can be shared by the first word line 22. In addition, in the adjacent two sub-memory arrays 28, the two field effect transistors 46 are adjacent to each other and connected to the same bit line 14 to share the same drain contact 56; the two field effect transistors 50 are adjacent to each other. Also, the same bit line 14 is connected to share the same drain contact 56. With this common contact arrangement, the overall layout area can be reduced, thereby greatly reducing the manufacturing cost.

Referring to FIG. 4, the field effect transistors 38, 42, 46, 50 may all be N-type field effect transistors located in a P-type substrate or a P-type well region, or may be located in an N-type substrate or an N-type well. The P-type field effect transistor in the region, and the operation mode of the present invention is different according to the N-type or P-type field effect transistor. The following description shows that the field effect transistor 38, 42, 46, 50 is the N-type field effect electric power. The way the crystal operates. In order to clearly illustrate this mode of operation, the name of each memory cell should be clearly defined: the first, second, third, and fourth memory cells 30, 32, 34, and 36 are all used as an operational memory crystal. The cell, and one of the operational memory cells can be selected as the selected memory cell for operation. An operational memory cell connected to the same bit line 14 as the selected memory cell and not connected to the same common source line 24 as the selected memory cell, as a complex allomorphic memory cell; connected to the same word line 20 as the selected memory cell The memory cell is operated as a complex word cell, and the rest of the memory cell is used as a complex memory cell.

The operation mode of the first embodiment is as follows. According to the following operation mode, other operational memory cells are not subjected to the selection bias except for the operation memory cell which is connected to the same bit line and the same common source line as the selected memory cell. influences.

_Applying a substrate voltage _{Vsubp to a} P-type substrate or a P-type well region in which the memory cell is connected, and applying a first bit voltage V to the bit line 14, the word line 20, and the common source line 24 of the selected memory cell connection, respectively. _B1 , the first word voltage V _w1 , the first common source voltage V _S1 , the second word voltage V _w2 and the second common source voltage V are respectively applied to the word line 20 and the common source line 24 connected to each of the same memory cells. _S2 , applying a second bit voltage V _b2 and a first common source voltage V _S1 to each of the bit line 24 and the common source line 24 connected to the same word memory cell, respectively, for each bit connected to the memory cell The line 14, the word line 20, and the common source line 24 respectively apply the second bit voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 , and satisfy the following conditions: when writing, V _subp is grounded. V _b2 is floating, and V _b1 >V _S1 , V _w1 >V _S1 , V _b1 >V _S1 >0, V _b1 >V _w2 >0, V _b1 >V _S2 >0; when erasing, V _{subp is satisfied} For grounding, V _S1 is grounded, V _b2 is floating, and V _b1 >V _w2 >V _w1 ≧0, V _b1 >V _S2 >V _w1 ≧0.

When the field effect transistors 38, 42, 46, 50 are P-type field effect transistors, the substrate voltage _{Vsubn is} applied to the N-type well region or the N-type substrate according to the definition of the memory cell and the voltage, and is written. When V _b2 is satisfied as floating, and V _subn >V _S1 >V _b1 , V _subn1 >V _S1 >V _w1 , V _subn >V _S2 >V _b1 , V _subn >V _w2 >V _b1 ; V _b2 is satisfied as floating, and V _subn =V _S1 ≧V _w1 >V _b1 , V _subn >V _S2 >V _b1 , V _subn >V _w2 >V _b1 .

Since the same bit line 14 is connected to the two memory cells for the same sub-memory array 28, when writing or erasing, the memory cell of one tuple is operated once instead of a single memory crystal. Cell. By using the above bias method, the function of using byte writes in non-volatile memory can be achieved without adding an isolation transistor.

The structural cross-sectional views of the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44, 48, 52 are described below, and an N-type field effect transistor is taken as an example. Referring to FIG. 7, the N-type field effect transistor 58 is disposed in a P-type semiconductor substrate 60 as a semiconductor substrate, and has a conductive gate 62. The capacitor 64 is simultaneously horizontally disposed with the N-type field effect transistor 58. In the P-type semiconductor substrate 60, the capacitor 64 is a capacitor of the same polysilicon as the conductive gate. When the semiconductor substrate is N-type, a P-type well region may be disposed in the substrate, and the N-type field effect transistor 58 may be disposed in the P-type well region.

Similarly, when the cross-sectional views of the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44, 48, 52 are exemplified by a P-type field effect transistor, as shown in Fig. 8, the P-type field effect transistor 66 is disposed in an N-type semiconductor substrate 68 as a semiconductor substrate, and has a conductive gate 70, and a capacitor 72 is simultaneously disposed horizontally with the P-type field effect transistor 66 in the N-type semiconductor substrate 68, and the capacitor 72 is The conductive gate is the same as the capacitor of the polysilicon. When the semiconductor substrate is P-type, an N-type well region may be disposed in the substrate, and the P-type field effect transistor 66 may be disposed in the N-type well region.

In order to operate a particular single memory cell, a second embodiment is provided below. Please refer to FIG. 9 , FIG. 10 and FIG. 11 simultaneously. This second embodiment differs from the first embodiment only in that each group of bit lines 16 includes two bit lines 14 , so the first group of bit lines 18 . Also included are two bit lines 14, which are respectively connected to the first and third memory cells 30, 34 of the same sub-memory array 28; the second set of bit lines 19 comprise two bit lines 14, which are respectively connected to the same The second and fourth memory cells 32, 36 of the sub-memory array 28. Further, in the adjacent two-child memory array 28, the two third memory cells 34 are adjacent to each other and connected to the same bit line 14 to share the same contact, and the second and fourth memory cells 36 are adjacent to each other and connected to each other. Bit line 14 to share the same contact. In other words, the field effect transistors 46 of the second memory cell 34 are adjacent to each other and connected to the same bit line 14 to share the same gate contact 56, and the field effect transistors 50 of the second memory cell 36 are mutually Adjacent and connected to the same bit line 14 to share the same bungee contact 56, the overall layout area can be reduced.

Referring to FIG. 9, the field effect transistors 38, 42, 46, 50 may all be N-type field effect transistors located in the P-type substrate or the P-type well region, or in the N-type substrate or the N-type well region. In the case of the P-type field effect transistor, the operation mode of the second embodiment differs depending on the N-type or P-type field effect transistor. The following describes the field effect transistor 38, 42, 46, 50 as the N-type field effect. The mode of operation of the transistor. In order to clearly illustrate this mode of operation, the name of each memory cell should be clearly defined: the first, second, third, and fourth memory cells 30, 32, 34, and 36 are all used as an operational memory crystal. The cell, and one of the operational memory cells can be selected as the selected memory cell for operation. An operational memory cell connected to the same bit line 14 as the memory cell is selected as a complex allo memory cell; an operational memory cell connected to the same word line 20 as the selected memory cell, as a complex word memory cell, the rest The memory cell is operated as a complex number of memory cells.

The second embodiment operates in the following manner, and the other unselected memory cells can be left unaffected to operate a particular single memory cell by the following operation.

_Applying a substrate voltage _{Vsubp to a} P-type substrate or a P-type well region in which the memory cell is connected, and applying a first bit voltage V to the bit line 14, the word line 20, and the common source line 24 of the selected memory cell connection, respectively. _B1 , the first word voltage V _w1 , the first common source voltage V _S1 , the second word voltage V _w2 and the second common source voltage V are respectively applied to the word line 20 and the common source line 24 connected to each of the same memory cells. _S2 , a second bit voltage V _b2 and a first common source voltage V _S1 are respectively applied to the bit line 14 and the common source line 24 connected to each of the same word memory cells, respectively, and the bit connected to each memory cell is not selected. The line 14, the word line 20, and the common source line 24 respectively apply the second bit voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 , and satisfy the following conditions: when writing, V _subp is grounded. V _b2 is floating, and V _b1 >V _S1 , V _w1 >V _S1 , V _b1 >V _S1 >0, V _b1 >V _w2 >0, V _b1 >V _S2 >0; when erasing, V _{subp is satisfied} For grounding, V _S1 is grounded, V _b2 is floating, and V _b1 >V _w2 >V _w1 ≧0, V _b1 >V _S2 >V _w1 ≧0.

When the field effect transistors 38, 42, 46, 50 are P-type field effect transistors, the substrate voltage _{Vsubn is} applied to the N-type well region or the N-type substrate according to the definition of the memory cell and the voltage, and is written. When V _b2 is satisfied as floating, and V _subn >V _S1 >V _b1 , V _subn >V _S1 >V _w1 , V _subn >V _S2 >V _b1 , V _subn >V _w2 >V _b1 ; V _b2 is satisfied as floating, and V _subn =V _S1 ≧V _w1 >V _b1 , V _subn >V _S2 >V _b1 , V _subn >V _w2 >V _b1 .

By using the above bias method, the function of byte write can be achieved in the non-volatile memory without adding an isolation transistor.

The structural cross-sectional views of the field effect transistors 38, 42, 46, 50 and the capacitors 40, 44, 48, 52 of the second embodiment are the same as those of the first embodiment, and therefore will not be described again.

In summary, the present invention utilizes a common contact method to have a small area structure, and can also utilize a bias mode to achieve a byte write function.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

10. . . Transistor

12. . . Capacitor structure

14. . . Bit line

16. . . Bit line

18. . . First set of bit lines

19. . . Second set of bit lines

20. . . Word line

twenty two. . . First word line

twenty four. . . Common source line

26. . . First common source line

28. . . Sub-memory array

30. . . First memory cell

32. . . Second memory cell

34. . . Third memory cell

36. . . Fourth memory unit cell

38. . . Field effect transistor

40. . . capacitance

42. . . Field effect transistor

44. . . capacitance

46. . . Field effect transistor

48. . . capacitance

50. . . Field effect transistor

52. . . capacitance

54. . . Gate contact

56. . . Bungee contact

58. . . N-type field effect transistor

60. . . P-type semiconductor substrate

62. . . Conductive gate

64. . . capacitance

66. . . P-type field effect transistor

68. . . N-type semiconductor substrate

70. . . Conductive gate

72. . . capacitance

Figure 1 is a schematic diagram of a prior art non-volatile memory circuit.

Figure 2 is a schematic diagram of the circuit layout of Figure 1.

Figure 3 is a cross-sectional view of the memory cell structure of the prior art non-volatile memory.

Figure 4 is a circuit diagram showing a first embodiment of the present invention.

Figure 5 is a schematic diagram showing the circuit layout of the first embodiment of the present invention.

Figure 6 is a circuit diagram of a sub-memory array of the first embodiment of the present invention.

Figure 7 is a cross-sectional view showing the structure of an N-type field effect transistor and a capacitor of the present invention.

Figure 8 is a cross-sectional view showing the structure of a P-type field effect transistor and a capacitor of the present invention.

Figure 9 is a circuit diagram showing a second embodiment of the present invention.

Figure 10 is a schematic diagram showing the circuit layout of the second embodiment of the present invention.

Figure 11 is a circuit diagram of a sub-memory array of a second embodiment of the present invention.

14. . . Bit line

16. . . Bit line

18. . . First set of bit lines

19. . . Second set of bit lines

20. . . Word line

twenty two. . . First word line

twenty four. . . Common source line

26. . . First common source line

28. . . Sub-memory array

30. . . First memory cell

32. . . Second memory cell

34. . . Third memory cell

36. . . Fourth memory unit cell

38. . . Field effect transistor

40. . . capacitance

42. . . Field effect transistor

44. . . capacitance

46. . . Field effect transistor

48. . . capacitance

50. . . Field effect transistor

52. . . capacitance

Claims (16)

A small area electronic erasing rewritable read-only memory array, comprising: a plurality of parallel bit lines, which are divided into complex array bit lines, wherein the group bit lines comprise a first group of bit lines and a second set of bit lines; a plurality of parallel word lines, which are perpendicular to the bit lines, and include a first word line; a plurality of parallel common source lines are parallel to the word lines And comprising a first common source line; and a plurality of sub-memory arrays, each of the sub-memory arrays connecting two sets of the bit line, a word line and a common source line, each of the sub-memory arrays The method includes: a first memory cell connected to the first group of bit lines, the first common source line and the first word line; and a second memory cell connected to the second group of bit lines The first common source line and the first word line, the first and second memory cells are symmetrically arranged on each other and located on the same side of the first common source line; and a third memory cell is connected to the first common source line a first set of bit lines, the first common source line and the first word line, and the first common source line as an axis and the first memory cell pair And a fourth memory cell connected to the second group of bit lines, the first common source line and the first word line, and the first common source line as an axis and the second memory crystal The cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged with each other, and the first and second memory cells are located on opposite sides of the first common source line. The small-area electronic erasable rewritable read-only memory array according to claim 1, wherein each of the sub-memory arrays is located between two adjacent sets of the bit lines. The small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the first, second, third, and fourth memory cells are connected to the first word line for sharing The same contact. The small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the first group of bit lines includes a bit line connecting the first and third memory crystals And the second set of bit lines also includes a bit line connecting the second and fourth memory cells. The small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the first group of bit lines includes two bit lines, and the first and third memories are respectively connected. The unit cell, and the second group of bit lines also includes two bit lines, which are respectively connected to the second and fourth memory cells. The small area electronic erasing rewritable read-only memory array according to claim 4 or 5, wherein the two third memory cells are adjacent to each other in the adjacent two sub-memory arrays And connecting the same bit line to share the same contact, the two fourth memory cells are adjacent to each other and connected to the same bit line to share the same contact. The small area electronic erasing rewritable read-only memory array according to claim 4, wherein the first, second, third, and fourth memory cells are located on a P-type substrate or a P-type well. In the N-type field effect transistor in the region, the first, second, third, and fourth memory cells are used as an operational memory cell, and one of the operational memory cells is selected as the selected memory cell. When the operation is performed, the bit line is connected to the selected memory cell, and the operational memory cells of the common source line are not connected to the selected memory cell as the complex allo memory cell, and The selected memory cell is connected to the operational memory cell of the same word line as a complex word memory cell, and the remaining operational memory cells are operated as a complex unselected memory cell, and the selected memory cell is operated. The method includes: applying a substrate voltage V _{subp to} the P-type substrate or the P-type well region connected to the memory cell, and selecting the bit line, the word line, and the common source line connected to the memory cell bits are applied to a first voltage V _b1, the first Voltage V _w1, the first common voltage source V _S1, the same bit in each of the memory cell connected to the word line, are respectively applied to the common source line of the second word voltage V _w2, a second common voltage source V _S2, in each of a bit line connected to the same word memory cell, the common source line respectively applying a second bit voltage V _b2 , the first common source voltage V _S1 , and the bit of each of the unselected memory cell connections The second line voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 are respectively applied to the source line, the word line, and the common source line, and satisfy the following conditions: when writing, V _subp is Grounding, V _b2 is floating; V _b1 >V _S1 ; V _w1 >V _S1 ; V _b1 >V _S1 >0; V _b1 >V _w2 >0; and V _b1 >V _S2 >0; V _subp is grounded, V _S1 is grounded, V _b2 is floating; V _b1 >V _w2 >V _w1 ≧0; and V _b1 >V _S2 >V _w1 ≧0. The small-area electronic erasing rewritable read-only memory array according to claim 4, wherein the first, second, third, and fourth memory cells are located on an N-type substrate or an N-type well. In the P-type field effect transistor in the region, the first, second, third, and fourth memory cells are used as an operational memory cell, and one of the operational memory cells is selected as the selected memory cell. When the operation is performed, the bit line is connected to the selected memory cell, and the operational memory cells of the common source line are not connected to the selected memory cell as the complex allo memory cell, and The selected memory cell is connected to the operational memory cell of the same word line as a complex word memory cell, and the remaining operational memory cells are operated as a complex unselected memory cell, and the selected memory cell is operated. The method includes: applying a substrate voltage _{Vsubn to} the N-type substrate or the N-type well region to which the memory cell is connected, and selecting the bit line, the word line, and the common source line connected to the memory cell bits are applied to a first voltage V _b1, the first Voltage V _w1, the first common voltage source V _S1, the same bit in each of the memory cell connected to the word line, are respectively applied to the common source line of the second word voltage V _w2, a second common voltage source V _S2, in each of a bit line connected to the same word memory cell, the common source line respectively applying a second bit voltage V _b2 , the first common source voltage V _S1 , and the bit of each of the unselected memory cell connections The second line voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 are respectively applied to the source line, the word line, and the common source line, and satisfy the following conditions: when writing, satisfying V _b2 Floating; V _subn >V _S1 >V _b1 ;V _subn1 >V _S1 >V _w1 ;V _subn >V _S2 >V _b1 ; and V _subn >V _w2 >V _b1 ; and when erasing, satisfying V _b2 Floating; V _subn = V _S1 ≧ V _w1 > V _b1 ; V _subn > V _S2 > V _b1 ; and V _subn > V _w2 > V _b1 . The small area electronic erasing rewritable read-only memory array according to claim 5, wherein the first, second, third, and fourth memory cells are located on a P-type substrate or a P-type well. In the N-type field effect transistor in the region, the first, second, third, and fourth memory cells are used as an operational memory cell, and one of the operational memory cells is selected as the selected memory cell. When the operation is performed, the operational memory cells of the same bit line are connected to the selected memory cell as the complex allo memory cell, and the operational memories of the same word line are connected to the selected memory cell. The unit cell, as a plurality of memory cells of the same word, the remaining operating memory cells are used as a plurality of memory cells, and the method for operating the selected memory cell comprises: selecting the P-type connected to the memory cell a substrate voltage V _{subp is} applied to the substrate or the P-type well region, and the first bit voltage V _b1 and the first word voltage V are respectively applied to the bit line connecting the selected memory cell, the word line, and the common source line respectively _W1 , the first common source voltage V _S1 , in each of the same a word line connected to the bit memory cell, the common source line respectively applying a second word voltage V _w2 and a second common source voltage V _S2 , the bit line connected to each of the same word memory cells, the total The source line respectively applies a second bit voltage V _b2 , the first common source voltage V _S1 , and applies the second to each of the bit lines, the word line, and the common source line of the unselected memory cell connection. The bit voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 satisfy the following conditions: when writing, V _subp is grounded, V _b2 is floating; V _b1 >V _S1 ; V _w1 >V _S1 ;V _b1 >V _S1 >0; V _b1 >V _w2 >0; and V _b1 >V _S2 >0; and when erasing, V _subp is grounded, V _S1 is grounded, V _b2 is floating ; V _b1 >V _w2 >V _w1 ≧0; and V _b1 >V _S2 >V _w1 ≧0. The small area electronic erasing rewritable read-only memory array according to claim 5, wherein the first, second, third, and fourth memory cells are located on an N-type substrate or an N-type well. In the P-type field effect transistor in the region, the first, second, third, and fourth memory cells are used as an operational memory cell, and one of the operational memory cells is selected as the selected memory cell. When the operation is performed, the operational memory cells of the same bit line are connected to the selected memory cell as the complex allo memory cell, and the operational memories of the same word line are connected to the selected memory cell. The unit cell, as a plurality of memory cells of the same word, the remaining operating memory cells are used as a plurality of memory cells, and the method for operating the selected memory cell comprises: selecting the N-type of the memory cell connection Applying a substrate voltage _{Vsubn to the} substrate or the N-type well region, and applying a first bit voltage _Vb1 and a first word voltage V to the bit line, the word line, and the common source line respectively connected to the selected memory cell _W1 , the first common source voltage V _S1 , in each of the same a word line connected to the bit memory cell, the common source line respectively applying a second word voltage V _w2 and a second common source voltage V _S2 , the bit line connected to each of the same word memory cells, the total The source line respectively applies a second bit voltage V _b2 , the first common source voltage V _S1 , and applies the second to each of the bit lines, the word line, and the common source line of the unselected memory cell connection. The bit voltage V _b2 , the second word voltage V _w2 , and the second common source voltage V _S2 satisfy the following conditions: when writing, V _b2 is satisfied as floating; V _subn >V _S1 >V _b1 ; V _subn1 > V _S1 >V _w1 ; V _subn >V _S2 >V _b1 ; and V _subn >V _w2 >V _b1 ; and when erasing, V _b2 is satisfied as floating; V _subn =V _S1 ≧V _w1 >V _b1 ;V _Subn >V _S2 >V _b1 ; and V _subn >V _w2 >V _b1 . The small area electronic erasing rewritable read-only memory array according to claim 1, wherein the first memory cell further comprises a field effect transistor having a conductive gate, and the field effect transistor The drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is formed by one of the same polysilicon as the conductive gate of the field effect transistor. Capacitively coupled to the field effect transistor, the field effect transistor receiving a bias voltage of the first set of bit lines and the first common source line, writing data to the conductive gate or data of the conductive gate Erase. The small area electronic erasing rewritable read-only memory array according to claim 1, wherein the second memory cell further comprises a field effect transistor having a conductive gate, and the field effect transistor The drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is formed by one of the same polysilicon as the conductive gate of the field effect transistor. Capacitively coupled to the field effect transistor, the field effect transistor receiving a bias voltage of the second group of bit lines and the first common source line, writing data to the conductive gate or data of the conductive gate Erase. The small area electronic erasing rewritable read-only memory array according to claim 1, wherein the third memory cell further comprises a field effect transistor having a conductive gate, and the field effect transistor The drain is connected to the first group of bit lines, the source is connected to the first common source line, and the bias of the first word line is formed by one of the same polysilicon as the conductive gate of the field effect transistor. Capacitively coupled to the field effect transistor, the field effect transistor receiving a bias voltage of the first set of bit lines and the first common source line, writing data to the conductive gate or data of the conductive gate Erase. The small-area electronic erasing rewritable read-only memory array according to claim 1, wherein the fourth memory cell further comprises a field effect transistor having a conductive gate, and the field effect transistor The drain is connected to the second group of bit lines, the source is connected to the first common source line, and the bias of the first word line is formed by one of the same polysilicon as the conductive gate of the field effect transistor. Capacitively coupled to the field effect transistor, the field effect transistor receiving a bias voltage of the second group of bit lines and the first common source line, writing data to the conductive gate or data of the conductive gate Erase. A small-area electronic erasing rewritable read-only memory array as described in claim 11, claim 12, item 13 or item 14, wherein the field effect transistor is an N-type field effect transistor or P-type field effect transistor. The small-area electronic erasing rewritable read-only memory array according to claim 11, wherein the field effect transistor and the capacitor system are horizontally disposed. In a semiconductor substrate.