TWI530701B - Three dimension integrated circuit testing system and method thereof - Google Patents

Description

Three-dimensional integrated circuit test system and method thereof

The invention relates to a three-dimensional integrated circuit testing system and a method thereof, in particular to an electrical testing system and a method for automatically generating various control signals required for testing inside a three-dimensional integrated circuit, thereby reducing external automatic testing. The dependence of the machine effectively completes the pre-stack mode of the three-dimensional integrated circuit, the boring mode, and the electrical tester of the post-stack mode.

According to the theory stated by Moore's Law, the number of transistors that can be accommodated on an integrated circuit (IC) is about every 18 months due to the advancement of semiconductor process technology. Doubled, and performance will more than double; however, with the rapid development of semiconductor process technology, it is increasingly difficult to accommodate a larger number of transistors on a single wafer, and because of the size of the transistor The smaller the lead time, the greater the relative delay time of the connecting line. In today's advanced semiconductor manufacturing process, the delay time ratio of the connecting line has been greatly increased, so that the evolution speed of the integrated circuit is gradually slowing; in order to solve the above problems, The innovation and invention of three-dimensional integrated circuit (3D IC) provides an effective semiconductor process solution. The three-dimensional integrated circuit has the advantages of increasing the component density per unit area and the transmission speed of the signal. Using the Through Silicon Via (TSV) technology, the vias (TSV) are layered in a vertical manner. Inter-wafer signal The connection makes the signal not only transmit in the two-dimensional direction, but also in the vertical direction of the three-dimensional, which is in line with the requirements of the overall performance of the wafer due to the continuous development of the process technology. In addition to the three-dimensional integrated circuit, the three-dimensional integrated circuit can be used to accelerate the signal. Transmission, another feature is to provide heterogeneous integration, so that wafers with different processes and different functions can be connected by vertical connecting lines.

Just like the traditional two-dimensional integrated circuit, the three-dimensional integrated circuit using the 矽-perforated (TSV) as the connecting line must also be electrically tested on the defects of the process to ensure that the manufactured product can meet the customer's needs; Three-dimensional integrated circuits require the use of today's most advanced testing techniques and testability methods, coupled with the great challenges of 矽perforation and three-dimensional process testing, so new fault models and corresponding test methods need to be developed to meet high efficiency. And low-cost requirements; in addition, the traditional three-dimensional integrated circuit test method relies entirely on the external automatic test equipment (ATM), the test method is the automatic test instrument through the test pin (test pad) transmits the control signal and test vector for testing to the three-dimensional integrated circuit for electrical testing of the three-dimensional integrated circuit, and after using the electrical response of the circuit, the control signal provided by the automatic test instrument is also used. The test results are transmitted back to the automated test equipment to complete the electrical test procedure for the 3D integrated circuit; however, to achieve high quality Circuit testing, automated test equipment supported by the price of hundreds of billion yuan, the cost of this test has become the semiconductor or severe burden of packaging and testing plant.

In addition, the test signals of the traditional electrical measurement are transmitted from the external automatic test equipment (ATE) to the test circuit. This transmission method is often accompanied by the problem of signal interference, and the signal pulse transmitted to the test circuit with the automatic test instrument. The higher the signal interference problem, the more serious the impact on the quality of the test and the lower the yield of the circuit. Moreover, the way of transmitting the test signal is limited by the test pin, resulting in a lower test clock. Causing automatic test equipment It is impossible to detect whether the circuit has a signal delay problem; therefore, how to effectively test the system and method of the three-dimensional integrated circuit with low cost and low signal interference to ensure the test quality of the chip and improve the yield of the chip, thereby reducing the test requirements. The cost is still an important issue for the current 3D integrated circuit electrical test development industry or researchers to continuously overcome and solve.

Nowadays, the inventors have in view of the above-mentioned tradition that the electrical test machine used in the semiconductor factory is too expensive and the signal is easily distorted or deformed, so it is a tireless spirit, and with its rich professional knowledge and many years. The practical experience is supplemented and improved, and the present invention has been developed based on this.

The main object of the present invention is to provide a three-dimensional integrated circuit test system and method thereof, and more particularly to an electrical test system and a method for automatically generating various control signals required for testing inside a three-dimensional integrated circuit, and the present invention can be applied to a three-dimensional product. The internal wisdom circuit of the internal circuit and the perforated structure connecting the layers are compared with the electrical test and the result, thereby, the three-dimensional integrated circuit can reduce the dependence on the external automatic test instrument, and effectively complete the pre-stack mode, Punch mode, as well as electrical testing of the post-stack mode.

In order to achieve the above-mentioned implementation, the inventors propose a three-dimensional integrated circuit test system, which includes a test interface and decoding unit, a control signal generating unit, and a test flow execution unit; the test interface and the decoding unit receive the three-dimensional integrated body. The test vector required by the circuit test system; the control signal generating unit is electrically connected to the test interface and the decoding unit, and the control signal generating unit is configured to generate a control signal required for the three-dimensional integrated circuit test in a specific test mode, wherein the specific test mode It can be a combination of one or more of the pre-stack test mode, the 矽 puncturing test mode, or the post-stack test mode; the test process execution unit is electrically connected The test interface and the decoding unit, and the control signal generating unit, the test flow execution unit transmits the test vector to the three-dimensional integrated circuit, and receives the test result of the three-dimensional integrated circuit back-transfer to compare with the expected test result.

The three-dimensional integrated circuit test system as described above, wherein the three-dimensional integrated circuit test system can further be provided with a graphical interface software module electrically connected to the test interface and the decoding unit, when the specific test mode is the pre-stack test mode or stack In one of the post-test modes, the graphical interface software module transmits the test vector required for the specific test mode, and is transmitted to the 3D integrated circuit via the test interface and the decoding unit and the test flow execution unit, and the test flow execution unit receives The test result of the three-dimensional integrated circuit back-transfer is compared with the expected result, and then the error information of the comparison is output by the graphical interface software module.

The three-dimensional integrated circuit test system as described above, wherein when the specific test mode is the 矽 puncturing test mode, the test flow execution unit generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit, and receives the three-dimensional integrated circuit return The results of the perforation test are then compared to the expected results.

The three-dimensional integrated circuit test system as described above, wherein the test interface and the decoding unit comprise a transmission conversion interface, and a data decoding transmitter electrically connected to the transmission conversion interface, wherein the transmission conversion interface receives the graphical interface software module The input test vector, the data decoding transmitter is a format used by the three-dimensional integrated circuit test system, and transmitted to the control signal generating unit and the test flow execution unit.

The three-dimensional integrated circuit test system as described above, wherein the control signal generating unit comprises a setting register, and a control signal generator electrically connected to the setting register, wherein the setting register receives the data decoding transmitter Test vector transmitted, control signal generator A control signal is input to the three-dimensional integrated circuit for electrical testing.

The three-dimensional integrated circuit test system as described above, wherein the test flow execution unit comprises at least one shift buffer, a comparator, a memory, a puncturing test vector generator, and a test flow controller; When the test mode is one of a pre-stack test mode or a post-stack test mode, at least one shift buffer transmits the test vector transmitted by the graphical interface software module to the three-dimensional integrated circuit for electrical test, and the comparator system Receiving the test result of the 3D integrated circuit backhaul and comparing with the expected test result stored in the memory; when the specific test mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator is based on the test in the test flow controller The process generates a test vector corresponding to the number of the number of puncturing puncturings, and transmits the puncturing through the at least one shifting buffer to the three-dimensional integrated circuit for electrical testing, and the comparator receives the puncturing test result of the three-dimensional integrated circuit backhaul. And align with the expected test results generated by the 矽 puncturing test vector generator.

In addition, in order to achieve the above-mentioned three-dimensional integrated circuit test system implementation purposes, the inventors have developed the following implementation techniques, first, select a specific test mode required for a three-dimensional integrated circuit test, the specific test mode is pre-stack test a mode, a puncturing test mode, and a post-stack test mode; and then, using a control signal generating unit to generate a control signal required for the three-dimensional integrated circuit test in a specific test mode; finally, using a control signal to generate The test flow execution unit of the unit electrical connection transmits a test vector to the three-dimensional integrated circuit, and receives the test result returned by the three-dimensional integrated circuit to compare with the expected test result.

The method for testing a three-dimensional integrated circuit as described above, wherein the test interface and the decoding unit are further electrically connected to a graphical interface software module, when the specific test mode is one of a pre-stack test mode or a post-stack test mode. , graphical interface software module is carried out The overall test process is to select a test vector required for a specific test mode, and is transmitted through the test interface and the decoding unit and the test flow execution unit, and the test flow execution unit receives the test result of the three-dimensional integrated circuit return to perform with the expected result. After the comparison, the graphical interface software module outputs the error information after the comparison, and the user can know whether the tested three-dimensional integrated circuit has an error.

The three-dimensional integrated circuit test method as described above, wherein when the specific test mode is the 矽 puncturing test mode, the test flow execution unit generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit, and receives the three-dimensional integrated circuit return The results of the perforation test are then compared to the expected results.

The three-dimensional integrated circuit testing method as described above, wherein the test interface and the decoding unit comprise a transmission conversion interface, and a data decoding transmitter electrically connected to the transmission conversion interface, wherein the transmission conversion interface receives the graphical interface software module The input test vector, the data decoding transmitter is a format used by the three-dimensional integrated circuit test system, and is transmitted to the control signal generating unit and the test flow execution unit; the control signal generating unit includes a setting register. And a control signal generator electrically connected to the setting register, wherein the setting register receives the test vector transmitted by the data decoding transmitter, and the control signal generator generates a control signal input to the three-dimensional integrated circuit for electrical testing. The test flow execution unit includes at least one shift buffer, a comparator, a memory, a puncturing test vector generator, and a test flow controller; when the specific test mode is a pre-stack test mode or a post-stack test At least one shift buffer when the mode is one of the modes Passing the test vector transmitted by the graphical interface software module to the three-dimensional integrated circuit for electrical testing, and the comparator receives the test result returned by the three-dimensional integrated circuit and compares it with the expected test result stored in the memory; Specific test When the mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator generates a test vector corresponding to the number of puncturing perforations according to the testing process in the test flow controller, and transmits the test vector to the three-dimensional integrated circuit via at least one shift buffer. After the perforation is electrically tested, the comparator receives the perforation test result of the back-transfer of the three-dimensional integrated circuit and compares it with the expected test result generated by the perforation test vector generator.

Therefore, the three-dimensional integrated circuit test system and method of the present invention automatically generate a test control signal by means of the circuit, thereby performing electrical test of the three-dimensional integrated circuit, and supporting an international standard test interface of the three-dimensional integrated circuit, so that After the test circuit is manufactured in the three-dimensional integrated circuit, the electric circuit of the three-dimensional integrated circuit and the 矽 perforated structure connecting the layers can be electrically tested, and the pre-stack test and the boring test of the three-dimensional integrated circuit are effectively completed. And the post-stack test; in addition, the three-dimensional integrated circuit test system and method of the present invention effectively solve the high cost and high external test machine (ATE) by high-efficiency three-dimensional integrated circuit electrical test mode. The shortcomings of signal interference and the inability to test the delay of high-cycle circuit signal, etc., effectively improve the cycle of semiconductor wafer manufacturing; finally, the three-dimensional integrated circuit test system and method of the present invention can effectively be used for the perforated structure electrical test system. Improving the traditional test method must rely on the external test machine to control the shortcomings of the test signal, effectively achieving low Electrical testing of the present three-dimensional integrated circuits, the electrical circuits to obtain three-dimensional integrated test result of a high degree of accuracy.

(1)‧‧‧Test interface and decoding unit

(11) ‧‧‧Transfer conversion interface

(12)‧‧‧ Data Decoding Transmitter

(2) ‧‧‧Control signal generation unit

(21)‧‧‧Setting the register

(22)‧‧‧Control signal generator

(221)‧‧‧Limited state machine

(222)‧‧‧3D test mode selector

(223)‧‧‧Shift counter

(224)‧‧‧Vector Counter

(3) ‧‧‧3D integrated circuit

(4) ‧‧‧Test Process Execution Unit

(41)‧‧‧Shift buffer

(411)‧‧‧Scan data buffer

(412)‧‧‧Loading data buffer

(413)‧‧‧ data counter

(42)‧‧‧ comparator

(421)‧‧‧ Results buffer

(422) ‧‧‧ Expected result buffer

(423)‧‧‧ aligners

(424)‧‧‧Error result register

(43) ‧‧‧ memory

(44)‧‧‧矽Perforation test vector generator

(441)‧‧‧ record buffer

(442)‧‧‧ algorithm vector generator

(443)‧‧‧Vector buffer

(45) ‧‧‧Test flow controller

(5)‧‧‧Graphic interface software module

(6) ‧ ‧ scan chain

(S1)‧‧‧Step one

(S2)‧‧‧Step 2

(S3) ‧ ‧ Step 3

First: a test system configuration block diagram of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention

The second figure: the overall configuration block diagram of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention

The third figure: a control signal generator configuration block diagram of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention

Fourth figure: block diagram of a shift buffer configuration of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention

Figure 5 is a block diagram showing a comparator configuration of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention.

Figure 6 is a block diagram of a configuration of a 矽 puncturing test vector generator of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention

Figure 7: Flow chart of the steps of the three-dimensional integrated circuit test method of the present invention

The object of the present invention and its structural design and advantages will be explained in the light of the preferred embodiments shown in the following drawings, so that the reviewing committee can have a more in-depth and specific understanding of the present invention.

First, please refer to the first and second figures. The test system configuration block diagram and the overall configuration block diagram of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention, wherein the three-dimensional integrated circuit test system includes: A test interface and decoding unit (1) is a test vector required for receiving a three-dimensional integrated circuit test system; a control signal generating unit (2), an electrical connection test interface and a decoding unit (1), and a control signal generating unit (2) A control signal required to generate a three-dimensional integrated circuit (3) test in a specific test mode, wherein the specific test mode is one of a pre-stack test mode, a puncture test mode, and a post-stack test mode. Or a combination of the two; and A test flow execution unit (4) is respectively electrically connected to the test interface and the decoding unit (1), and the control signal generating unit (2), and the test flow execution unit (4) transmits the test vector to the three-dimensional integrated circuit (3) And receiving the test result of the three-dimensional integrated circuit (3) back to compare with the expected test result.

In addition, the three-dimensional integrated circuit test system is further provided with a graphical interface software module (5) electrically connected to the test interface and the decoding unit (1), when the specific test mode is a pre-stack test mode or a post-stack test mode. In one case, the graphical interface software module (5) performs an overall test process to select a test vector required for a specific test mode, and transmits it through the test interface and the decoding unit (1) and the test flow execution unit (4). The test flow execution unit (4) receives the test result of the back-transfer of the three-dimensional integrated circuit (3), and compares it with the expected result, and then outputs the error information after the comparison by the graphical interface software module (5). It can be known whether the tested three-dimensional integrated circuit (3) has an error.

Furthermore, when the specific test mode is the 矽 puncturing test mode, the test flow execution unit (4) generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit (3), and receives the three-dimensional integrated circuit (3) backhaul. The results of the perforation test are then compared to the expected results.

In addition, the test interface and decoding unit (1) includes a transmission conversion interface (11), and a data decoding transmitter (12) electrically connected to the transmission conversion interface (11), wherein the transmission conversion interface (11) receives graphics The interface software module (5) inputs the test vector, and the data decoding transmitter (12) converts the test vector into the format used by the three-dimensional integrated circuit test system, and transmits it to the control signal generating unit (2) and the test flow execution. Unit (4).

Furthermore, the control signal generating unit (2) includes a setting register (21), and a control signal generator (22) electrically connected to the setting register (21), wherein the register (21) is set. The test signal transmitted by the data decoding transmitter (12) is received, and the control signal generator (22) generates a control signal input to the three-dimensional integrated circuit (3) for electrical testing.

In addition, the test flow execution unit (4) includes at least one shift buffer (41), a comparator (42), a memory (43), a puncturing test vector generator (44), and a test flow. The controller (45); when the specific test mode is one of a pre-stack test mode or a post-stack test mode, at least one shift buffer (41) is a test vector transmitted by the graphical interface software module (5) Passed to the three-dimensional integrated circuit (3) for electrical testing, the comparator (42) receives the test result returned by the three-dimensional integrated circuit (3), and compared with the expected test results stored in the memory (43); When the specific test mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator (44) generates a test vector corresponding to the number of puncturing perforations according to the test flow in the test flow controller (45), after at least one shift The bit buffer (41) is transmitted to the three-dimensional integrated circuit (3) for electrical testing, and the comparator (42) receives the back-punched test result of the three-dimensional integrated circuit (3), and is tested with the boring test. The vector generator (44) produces an expected comparison of the test results.

Furthermore, the three-dimensional integrated circuit test system of the present invention transfers test vectors to at least one scan chain via at least one shift buffer (41), built in a three-dimensional integrated circuit test system. The plurality of test standard circuits are coated with one of IEEE P1838, IEEE P1687, IEEE 1149.1, and IEEE 1500. In a preferred embodiment of the present invention, a package circuit conforming to the IEEE P1838 standard is used to The internal signal is swept out for electrical testing of the three-dimensional integrated circuit (3), wherein the wrapped circuit includes a boundary scan, a wrapper instructuin register, and a wrapper (wrapper). Controller), and a wrapper clock controller, the edge scan chain records the test standard circuit input and output signals of the three-dimensional integrated circuit test system, the package instruction The register is a command to be executed by the parcel circuit. The parcel controller analyzes the control signal in the instruction register and the input parcel circuit and generates a corresponding control signal, and the package clock controller controls the three-dimensional product. The body circuit test system tests the clock of the standard circuit, thereby controlling the scan chain (6) of the three-dimensional integrated circuit (3); however, it must be noted that the principles and architecture of the above-described package circuit are well known in the art. The knowledge is not the focus of the present invention, so that the internal signal of the test standard circuit of the three-dimensional integrated circuit (3) can be swept out, and the present invention is not limited to whether or not to cover IEEE P1838, IEEE P1687, IEEE 1149.1. And a test standard circuit of a three-dimensional integrated circuit test system of one of IEEE 1500 and the like.

In addition, the transport conversion interface (11) is a Joint Test Action Group (JTAG), Peripheral Component Interconnect (PCI), and a universal serial bus interface (Universal Serial Bus). In one of the above, the test vector is input to the three-dimensional integrated circuit test system. In a preferred embodiment of the present invention, the transmission conversion interface (11) receives the graphical interface software module (5). The test signal line of IEEE 1149.1 transmits the test vector and tests the expected result and stores it in the memory (43), thereby reducing the number of transmission signal lines originally required by hundreds to thousands.

Furthermore, please refer to the third figure, which is a block diagram of a control signal generator configuration of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention, wherein the control signal generator (22) includes a finite state machine ( 221) (Finite State Machine, FSM for short), and a three-dimensional test mode selector (222), a shift counter (223) and a vector counter (224) electrically connected to the finite state machine (221); When the specific test mode is the 矽 puncturing test mode, the three-dimensional test mode selector (222) is adjusted to the 矽 puncturing mode, and the shift counter (223) records the 矽 perforation test vector to the three-dimensional integrated circuit (3). Number of displacements of the structure (not shown), and vector The counter (224) records the number of data of the test vector, generates a corresponding control signal through the finite state machine (221), and transmits the 矽 perforation test vector to the 矽 perforation structure of the three-dimensional integrated circuit (3), and then passes the test. The test flow controller (45) generates a control signal to transmit the test result back to the three-dimensional integrated circuit test system; when the specific test mode is one of a pre-stack test mode or a post-stack test mode, the three-dimensional test mode selector (222) will be adjusted to the pre-stack test mode or the post-stack test mode, the shift counter (223) will record the number of shifts of the transfer test vector to the three-dimensional integrated circuit (3), and the vector counter (224) also records the test vector. The number of data, the control signal generator (22) generates a corresponding control signal according to the content of the record, transfers the test vector stored in the memory (43) to the three-dimensional integrated circuit (3), and then according to the test flow controller ( 45) The information generation control signal transmits the test result back to the three-dimensional integrated circuit test system.

In addition, please refer to the fourth figure, which is a block diagram of a shift buffer configuration of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention, wherein the shift buffer (41) includes at least one scan data buffer. (411), and one of the electrical connection scan data buffers (411) is respectively loaded into the data buffer (412) and a data counter (413); in the specific test mode, the scan data buffer (411) can receive the test. The result of the vector and the three-dimensional integrated circuit (3), and the data on the scan data buffer (411) is copied in parallel by the load data buffer (412), and the data counter (413) is used for counting. Scan the data on the data buffer (411).

In addition, please refer to the fifth figure, which is a block diagram of a comparator configuration of a preferred embodiment of the three-dimensional integrated circuit test system of the present invention, wherein the comparator (42) includes a result buffer (421), a The expected result buffer (422), a comparator (423) of the electrical connection result buffer (421) and the expected result buffer (422), and an incorrect result of the electrical connection comparator (423) are temporarily suspended. The memory (424), the result buffer (421) is a temporary storage of the test result of the three-dimensional integrated circuit (3), and the expected junction The buffer (422) stores the expected test result of the three-dimensional integrated circuit (3), and the foregoing result buffer (421) is compared with the expected result buffer (422) in the comparator (423), if If the results of the comparison are inconsistent, the comparison information is transferred to the error result register (424) for temporary storage.

In addition, please refer to the sixth figure, which is a block diagram of a configuration of a 矽 puncturing test vector generator according to a preferred embodiment of the three-dimensional integrated circuit testing system of the present invention, wherein the 矽 puncturing test vector generator (44) includes a a record buffer (441), an algorithm vector generator (442) electrically coupled to the record buffer (441), and a vector buffer (443) electrically coupled to the algorithm vector generator (442) when specified When the test mode is the 矽 puncturing test mode, the record buffer (441) records the relevant information of the three-dimensional integrated circuit (3) and the three-dimensional integrated circuit test system, and the recorded information includes the layers of the test circuit of the three-dimensional integrated circuit. The number of circuits and the number of layers of the test circuit of the three-dimensional integrated circuit, the algorithm vector generator (442) transmits the information of the record buffer (441) to generate a perforation test corresponding to the number of punctures to the vector buffer (443). ) Temporary storage.

Furthermore, in order to enable the reviewing committee to have a more in-depth and specific understanding of the present invention, please refer to the seventh figure, which is a flow chart of the method for testing the three-dimensional integrated circuit of the present invention, which includes the following steps: Step 1 ( S1): Select a three-dimensional integrated circuit (3) to test the specific test mode, the specific test mode is one of the pre-stack test mode, the boring test mode, and the post-stack test mode; step two (S2): Using a control signal generating unit (2) to generate a control signal required for testing the three-dimensional integrated circuit (3) in a specific test mode; and step three (S3): electrically connecting to the control signal generating unit (2) The test flow execution unit (4) transmits a test vector to the three-dimensional integrated circuit (3) and receives the three-dimensional integrated circuit (3) The test results of the return are compared to the expected test results.

In addition, the test flow execution unit (4) can be further electrically connected to a graphical interface software module (5), and a test interface and decoding unit (1), when the specific test mode is a pre-stack test mode or a post-stack test In one of the modes, the graphical interface software module (5) transmits the test vector required for the specific test mode, via the test interface and the decoding unit (1) and the test flow execution unit (4) to the three-dimensional integrated circuit ( 3) The test flow execution unit (4) receives the test result of the 3D integrated circuit (3) back to compare with the expected result, and then outputs the comparison error by the graphical interface software module (5). News.

Furthermore, when the specific test mode is the 矽 puncturing test mode, the test flow execution unit (4) generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit (3), and receives the three-dimensional integrated circuit (3) backhaul. The results of the perforation test are then compared to the expected results.

In addition, the test interface and decoding unit (1) includes a transmission conversion interface (11), and a data decoding transmitter (12) electrically connected to the transmission conversion interface (11), wherein the transmission conversion interface (11) receives graphics The interface software module (5) inputs the test vector, and the data decoding transmitter (12) converts the test vector into the format used by the three-dimensional integrated circuit test system, and transmits it to the control signal generating unit (2) and the test flow execution. The unit (4); the control signal generating unit (2) includes a setting register (21), and a control signal generator (22) electrically connected to the setting register (21), wherein the register is set ( 21) receiving the test vector transmitted by the data decoding transmitter (12), and the control signal generator (22) generates a control signal input to the three-dimensional integrated circuit (3) for electrical testing; the test flow execution unit (4) is Include at least one shift buffer (41), a comparator (42), a memory (43), a puncturing test vector generator (44), and a test flow controller (45); when a specific test mode It is a pre-stack test mode or a post-stack test mode. One type, at least one shift is slow The punch (41) transmits the test vector transmitted by the graphical interface software module (5) to the three-dimensional integrated circuit (3) for electrical testing, and the comparator (42) receives the three-dimensional integrated circuit (3) backhaul. The test result is compared with the expected test result stored in the memory (43); when the specific test mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator (44) is based on the test flow controller (45) The test process generates a test vector corresponding to the number of punctured puncturings, which is transmitted to the three-dimensional integrated circuit (3) through at least one shift buffer (41) for electrical testing, and the comparator (42) receives The three-dimensional integrated circuit (3) returns the punctured test result and compares it with the expected test result generated by the 矽 puncturing test vector generator (44).

It can be seen from the above description that the three-dimensional integrated circuit test system and method of the present invention have the following advantages compared with the prior art: 1. The three-dimensional integrated circuit test system and method thereof of the present invention are provided by a circuit The test control signal is automatically generated internally to perform the electrical test of the three-dimensional integrated circuit, and supports the international standard test interface of the three-dimensional integrated circuit, so that the test circuit can be built into the three-dimensional integrated circuit after the three-dimensional integrated circuit is completed. The Wisdom circuit and the perforated structure connecting the layers are electrically tested to effectively complete the pre-stack test, the boring test, and the post-stack test of the three-dimensional integrated circuit.

2. The three-dimensional integrated circuit test system and method thereof of the present invention effectively solve the shortcomings of high cost and high signal interference of an external automatic test machine (ATE) by means of a high-efficiency three-dimensional integrated circuit electrical test mode. And the inability to test the delay of high-clock circuit signal, etc., effectively improve the cycle of semiconductor wafer manufacturing.

3. The three-dimensional integrated circuit test system and method of the present invention, the perforated structure electrical test system can effectively improve the traditional test method must rely on the external test machine control test The shortcomings of the test signal effectively achieve the electrical test of the low-cost three-dimensional integrated circuit to obtain the high-accuracy three-dimensional integrated circuit electrical test results.

In summary, the three-dimensional integrated circuit test system and method of the present invention can achieve the intended use efficiency by the above-disclosed embodiments, and the present invention has not been disclosed before the application, and has completely complied with the patent. The rules and requirements of the law.爰Issuing an application for a patent for invention in accordance with the law, and asking for a review, and granting a patent, is truly sensible.

The illustrations and descriptions of the present invention are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; those skilled in the art, which are characterized by the scope of the present invention, Equivalent variations or modifications are considered to be within the scope of the design of the invention.

(1)‧‧‧Test interface and decoding unit

(11) ‧‧‧Transfer conversion interface

(12)‧‧‧ Data Decoding Transmitter

(2) ‧‧‧Control signal generation unit

(21)‧‧‧Setting the register

(22)‧‧‧Control signal generator

(3) ‧‧‧3D integrated circuit

(4) ‧‧‧Test Process Execution Unit

(41)‧‧‧Shift buffer

(42)‧‧‧ comparator

(43) ‧‧‧ memory

(44)‧‧‧矽Perforation test vector generator

(45) ‧‧‧Test flow controller

(5)‧‧‧Graphic interface software module

Claims (10)

A three-dimensional integrated circuit test system includes: a test interface and a decoding unit, which is a test vector required to receive the three-dimensional integrated circuit test system; a control signal generating unit electrically connected to the test interface and the decoding unit The control signal generating unit generates a control signal required for the three-dimensional integrated circuit test in a specific test mode, wherein the specific test mode is a pre-stack test mode, a puncture test mode, and a post-stack test mode. a combination of one or more; and a test flow execution unit electrically connected to the test interface and the decoding unit, and the control signal generating unit, wherein the test flow execution unit transmits the test vector to the three-dimensional integrated circuit And receiving the test result returned by the three-dimensional integrated circuit to compare with the expected test result. The three-dimensional integrated circuit test system of claim 1, wherein the three-dimensional integrated circuit test system is further provided with a graphical interface software module electrically connected to the test interface and the decoding unit, when the specific test When the mode is one of the pre-stack test mode or the post-stack test mode, the graphical interface software module performs an overall test process to select a test vector required for a specific test mode, and passes the test interface and the decoding unit and the test. The process execution unit transmits, and the test flow execution unit receives the test result of the three-dimensional integrated circuit return If the result is compared with the expected result, the graphical interface software module outputs the error information after the comparison. The three-dimensional integrated circuit test system of claim 1, wherein when the specific test mode is a 矽 puncturing test mode, the test flow execution unit generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit. And receiving the punctured test result of the three-dimensional integrated circuit back to compare with the expected result. The three-dimensional integrated circuit test system of claim 2, wherein the test interface and the decoding unit comprise a transmission conversion interface, and a data decoding transmitter electrically connected to the transmission conversion interface, wherein the transmission conversion The interface receives the test vector input by the graphical interface software module, and the data decoding transmitter converts the test vector into a format used by the three-dimensional integrated circuit test system, and transmits the format to the control signal generating unit and the test flow. Execution unit. The three-dimensional integrated circuit test system of claim 4, wherein the control signal generating unit comprises a setting register, and a control signal generator electrically connected to the setting register, wherein the setting The register receives the test vector transmitted by the data decoding transmitter, and the control signal generator generates a control signal input to the three-dimensional integrated circuit for electrical testing. The three-dimensional integrated circuit test system of claim 5, wherein the test flow execution unit comprises at least one shift buffer, a comparator, a memory, a puncturing test vector generator, and a Test process controller When the specific test mode is one of a pre-stack test mode or a post-stack test mode, the at least one shift buffer transmits the test vector transmitted by the graphical interface software module to the three-dimensional integrated circuit for electrical testing. The comparator receives the test result returned by the three-dimensional integrated circuit and compares it with the expected test result stored in the memory; when the specific test mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator And generating, according to the testing process in the test flow controller, a test vector corresponding to the number of puncturing puncturings, and transmitting, by the at least one shifting buffer, to the puncturing hole of the three-dimensional integrated circuit for electrical testing, the comparator Receiving the back-punch test result of the three-dimensional integrated circuit back-transmission and comparing it with the expected test result generated by the 矽-punch test vector generator. A three-dimensional integrated circuit test method includes the following steps: Step 1: Select a specific test mode required for a three-dimensional integrated circuit test, which is a pre-stack test mode, a perforation test mode, and a post-stack test. One of the modes; step 2: using a control signal generating unit to generate the control signal required for the three-dimensional integrated circuit test in the specific test mode; and step three: using a test electrically connected to the control signal generating unit The process execution unit transmits a test vector to the three-dimensional integrated circuit, and receives the test result returned by the three-dimensional integrated circuit to compare with the expected test result. The method for testing a three-dimensional integrated circuit according to claim 7, wherein the test flow execution unit is further electrically connected to a graphical interface software module, and a test interface and a decoding unit, when the specific test mode is In one of the pre-stack test mode or the post-stack test mode, the graphical interface software module transmits a test vector required for the specific test mode, through the test interface and the decoding unit and the test flow execution unit to the three-dimensional integrated body. The circuit, the test flow execution unit receives the test result of the three-dimensional integrated circuit back-transfer, and compares the expected result, and then outputs the compared error information by the graphical interface software module. The method of testing a three-dimensional integrated circuit according to claim 7, wherein when the specific test mode is a 矽 puncturing test mode, the test flow execution unit generates a 矽 puncturing test vector for transmission to the three-dimensional integrated circuit. And receiving the punctured test result of the three-dimensional integrated circuit back to compare with the expected result. The method for testing a three-dimensional integrated circuit according to claim 8, wherein the test interface and the decoding unit comprise a transmission conversion interface, and a data decoding transmitter electrically connected to the transmission conversion interface, wherein the transmission conversion The interface receives the test vector input by the graphical interface software module, and the data decoding transmitter converts the test vector into a format used by the three-dimensional integrated circuit test system, and transmits the format to the control signal generating unit and the test flow. An execution unit; the control signal generating unit includes a setting register, and a control signal generator electrically connected to the setting register, wherein the setting register receives the capital The test signal is transmitted by the test transmitter, and the control signal generator generates a control signal input to the three-dimensional integrated circuit for electrical testing; the test flow execution unit includes at least one shift buffer, a comparator, and a a memory, a perforation test vector generator, and a test flow controller; when the specific test mode is one of a pre-stack test mode or a post-stack test mode, the at least one shift buffer is the graphical interface The test vector transmitted by the software module is transmitted to the three-dimensional integrated circuit for electrical testing, and the comparator receives the test result returned by the three-dimensional integrated circuit, and compares with the expected test result stored in the memory; When the specific test mode is the 矽 puncturing test mode, the 矽 puncturing test vector generator generates a test vector corresponding to the number of punctured puncturing according to the test flow in the test flow controller, through the at least one shift buffer Transmitting to the three-dimensional integrated circuit for electrical testing, the comparator receives the three-dimensional integrated circuit backhaul Through-silicon via test result, and generating an expected test result of alignment with the through-silicon via test vectors.