TWI720832B - Structure and method for testing semiconductor devices - Google Patents

Abstract

A method of testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer; transmitting a testing signal to a first device under test (DUT) through the first register at a first edge of the clock signal; transmitting a first measurement signal through a first pad of the first wafer; transmitting the testing signal to a second DUT through the second register at a second edge of the clock signal; and transmitting a second measurement signal through a second pad of the second wafer, wherein the first pad and the second pad are aligned in a vertical direction.

Description

Test structure and method of semiconductor device

The present invention relates to a test structure and method of a semiconductor test device.

With the development of technology, the design and manufacture of semiconductor devices have become more complicated due to shrinking sizes, increasing functions, and more circuits. Therefore, many manufacturing processes are required to realize these tiny and efficient semiconductor devices. At present, there has been a large demand for modifying the structure and method of testing and manufacturing semiconductor devices in order to improve the stability of the device and reduce the manufacturing cost and processing time.

According to an embodiment of the present invention, a method for testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer; At one edge, the test signal is sent to the first DUT through the first register; the first measurement signal is sent through the first pad of the first wafer; at the second edge of the clock signal, the first measurement signal is sent through The second register transmits the test signal to the second object under test; and transmits the second measurement signal through the second pad of the second wafer, wherein the first pad and the second pad are aligned in the vertical direction .

According to an embodiment of the present invention, a method for testing a semiconductor device includes Including: a first register for transmitting a clock signal to a first wafer and a second register for a second wafer, wherein the first wafer further includes a first object to be tested, and the second wafer further includes A second object to be tested, and the first wafer and the second wafer form a wafer stack; transmit a test signal to the second register; the test signal passes through the clock signal at the first time of the clock signal The second register is transmitted to the second DUT and the first register; and the test signal is transmitted to the first DUT via the first register at the second time of the clock signal , Wherein the second time is later than the first time.

According to an embodiment of the present invention, a semiconductor structure includes a first wafer and a second wafer. The first wafer includes a plurality of first semiconductor devices and a first separation region separates the first semiconductor devices, wherein the first separation region includes a first pad, a first DUT, and a first circuit, the first circuit It is configured to test the first object under test according to a test signal, and the first pad is configured to transmit a first measurement signal of the first object under test. The second wafer includes a plurality of second semiconductor devices and a second separation region separates the second semiconductor devices, wherein the second separation region includes a second pad, a second DUT, and a second circuit, the second circuit It is configured to test the second object under test according to the test signal, and the second pad is configured to transmit a second measurement signal of the second object under test. The first pad is aligned in a vertical direction and electrically connected to the second pad. The first circuit and the second circuit are further configured to test the first object under test and the second object under test at different times.

The various objects, features, aspects, and advantages of the present invention will become more apparent from the implementation of the preferred embodiments of the present invention together with the accompanying drawings. The same numbers in the accompanying drawings represent similar components.

100: Wafer stack

100F: surface

101a, 101b, 101c, 101d, 101e: wafer

102: Semiconductor device

104: Cutting track area

106: test structure

112a, 112b, 112c, 112d, 112e: substrate

114a, 114b, 114c, 114d, 114e: front side interconnection structure

116a, 116b, 116c, 116d, 116e: backside interconnection structure

122, 122a, 122b: DUT

122-e1~122-eK, 122-d1~122-dK: DUT

124: conductive layer

124a: Horizontal conductive thread

124b: Vertical conductive path

126: Pad

126a: Select the pad

126b: Measuring pad

200: test system

204: Select Circuit

206: switch circuit

208: DUT

210, 220, 230, 240: conductive layer

302-a1~302-aN: pad

302-b1~302-bN: pad

302-c1~302-cN: pad

302-d1~302-dN: pad

302-e1~302-eN: pad

304: conductive structure

304-aN, 304-bN: conductive structure

304-cN, 304-dN: conductive structure

306: conductive structure

306-a2~306-a(N-2): conductive structure

306-b2~306-b(N-2): conductive structure

306-c2~306-c(N-2): conductive structure

306-d2~306-d(N-2): conductive structure

308: conductive structure

308-a1, 308-c1: conductive structure

308-b(N-1), 308-d(N-1): conductive structure

400: Test circuit

500, 600, 700: method

502, 504, 506, 508, 510: steps

602, 604, 606, 608: steps

702, 704, 706, 708, 710: steps

712, 714, 716: steps

Clock: Clock signal

Data: Test signal

R11~R2K: register

L11~L2K: Delay unit

T0~T10: time

P1, P2, P3: pads

V1: Vertical conductive path

Z1: zone

The aspect of the present invention will be better understood from the following embodiments and the accompanying drawings. It should be noted that according to industry standard practice, various features are not drawn to actual scale. In fact, for clear description, the size of various features can be enlarged or reduced arbitrarily.

FIG. 1A is a schematic diagram of a wafer stack according to an embodiment of the present invention.

FIG. 1B is a cross-sectional view of the test structure according to FIG. 1A according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a testing system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a wafer stack according to an embodiment of the present invention.

Fig. 4A is a schematic diagram of a test circuit according to an embodiment of the present invention.

Fig. 4B is a waveform diagram of a test circuit according to an embodiment of the present invention.

Fig. 5 is a flowchart of a testing method according to an embodiment of the present invention.

Fig. 6 is a flowchart of a testing method according to an embodiment of the present invention.

FIG. 7 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present invention, specific examples of components and configurations are described below. Of course, these are only examples and not limited. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first and second features are formed in direct contact, and it also includes an embodiment where the first and second features are formed in direct contact. Additional features are formed between the second features, so that the first and second features can be embodiments that are not in direct contact. In addition, the present invention may repeat reference numbers and/or letters in each example. This is repeated for the purpose of simplification and clarity, and it does not represent the relationship between the various embodiments and/or configurations described above.

In addition, the spatial relative terms used in this manual, such as "below", "below", "below", "above", "above", etc., are for easy description and explanation of a pair of elements or features as shown in the figure. The relationship of another element or feature. The relative terms of space are intended to cover different directions in use or operation of the device in addition to the directions described in the drawings. The device can be rotated in other directions (rotated by 90 degrees or other angle directions), and the space used in this manual The relative terms can therefore be interpreted in the same way.

Although the numerical ranges and parameters that illustrate the broad range of the present invention are approximate values, the numerical values set forth in the specific examples are presented as precisely as possible. However, any value essentially contains certain errors that are usually inevitably found in the various test and measurement deviations. At the same time, as used in this manual, the terms "about", "substantial" and "substantially" generally mean within 10%, 5%, 1% or 0.5% of a specific value or range. Or, when considered by those with ordinary knowledge in the field, the terms "about", "substantial" and "substantially" mean within the acceptable standard error of the average. Except in the operation/work examples, or unless otherwise clearly stated, all numerical ranges, quantities, numerical values and percentages (such as material quantity, duration, temperature, operating conditions, quantity ratios, etc.) disclosed in this specification are in any case The following should be understood as modified by the terms "about", "substantial" or "substantially". Therefore, unless there are teachings to the contrary, the numerical parameters described in the scope of the present invention and the following patent applications are approximate values that can be changed as needed. At the very least, each numerical parameter should at least be explained based on the number of significant figures presented and by applying ordinary rounding techniques. The range can be expressed in this specification as from one end point to the other end point or between the two end points. Unless otherwise stated, all ranges disclosed in this specification include endpoints.

In the latest semiconductor manufacturing layout, 3D integrated circuit (3D integrated circuit, 3DIC) has been regarded as one of the important technologies. By stacking different wafers and bonding and packaging electronic components on different wafers, it can be formed The electronic packaging device has higher performance, less power consumption, and smaller size. During the manufacturing process of semiconductor devices including three-dimensional integrated circuits, wafers or wafers need to be tested to ensure that the yield of the manufactured semiconductor devices meets expectations. For example, a method called wafer acceptance test (wafer acceptance test, WAT) forms certain dummy structures on the manufactured wafer and tests these dummy structures for early development. Whether there is any deviation in the current production process. The WAT method can use the dicing lanes in the wafer to separate different chips to form dummy structures and related circuits as test keys. Each test pattern can be used for different test purposes, such as forming Transistor device, and test the resistance or current value. When the WAT method is used to detect circuit defects in the test pattern at the early stage of the manufacturing process of the semiconductor device, it means that the physical or electrical characteristics of the manufactured wafer are likely to have similar defects or yield problems. The tested defective wafers can be further inspected or corrected, or discarded from the production line to save manufacturing cost and time.

Although the wafer acceptance test method has been used in the test process of the two-dimensional integrated circuit, the current test method and circuit still cannot complete the test of the three-dimensional integrated circuit in an efficient manner. For example, in the formation of a stack of wafers, the test patterns formed by the wafers stacked on top of each other must be staggered in the vertical direction for the test pads of the signal input and output terminals to be electrically connected to each other through the formation of conductive paths. These test pads perform individual tests on the wafers underneath. However, this will greatly increase the area of the wafer occupied by the test structure, and increase the cost of wafer manufacturing.

The embodiments of the present disclosure are related to a structure and method for testing semiconductor devices. With the test structure and test method discussed in the present disclosure, it is possible to electrically connect and access the upper and lower (that is, in the vertical direction) overlapping test pads in the upper and lower wafers, and receive from the test pads Measurement results of individual DUTs on individual wafers. Since the test pads of different wafers can overlap up and down, the wafer area occupied by the test structure will not increase with the number of stacked wafers, thus maximizing the effective manufacturing area of the wafers and improving production efficiency And reduce production costs.

FIG. 1A is a schematic diagram of a wafer stack 100 according to an embodiment of the present invention. The wafer stack 100 is formed by stacking a plurality of wafers 101, such as wafers 101a, 101b, and 101c. in In some embodiments, the wafer 101 is used to form the test structure or the test circuit of the embodiment of the present invention. The following description of each wafer 101a, 101b, or 101c will be based on the description of the wafer 101 and will not be described separately. As shown in FIG. 1A, the wafer 101 is a semiconductor wafer, which may include a semiconductor material such as silicon. In one embodiment, the wafer 101 includes other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. The wafer 101 can be held by a wafer stage or a suction cup.

Each of the wafer 101 defines a device area, where the device area is used to manufacture one or more semiconductor devices 102, and the device area may be arranged on the wafer 101 in a matrix. Each of the semiconductor devices 102 may include various functional components formed on the surface of the wafer 101. For example, these functional components can be transistors, diodes, capacitors, or conductive interconnects. The semiconductor device 102 shown in FIG. 1A may include completed or unfinished semiconductor circuits. A spacing area or scribe lane area 104 may be defined between adjacent semiconductor devices 102 for separating different semiconductor devices 102. The cutting lane area 104 may be formed into a lattice structure intersecting each other and arranged in rows and columns. When the wafer 101 or the wafer stack 100 is diced to produce individual semiconductor devices 102, a dicing knife or a laser can be used to perform a dicing operation along the scribe lane area 104. After the manufacturing and testing process of the semiconductor device 102 is completed, the semiconductor device 102 is singulated into individual dies by removing the scribe lane area 104. In some embodiments, during the singulation process, the scribe lane area 104 is partially or completely removed.

In one embodiment, the test structure 106 is formed in the scribe lane area 104 of the wafer 101. In one embodiment, the test structure 106 is formed as an independent circuit and is physically and electrically separated from the semiconductor device 102. The design of the test structure 106 can be used to determine and reflect the geometric pattern accuracy and electrical performance of the components of the semiconductor device 102 fabricated on the wafer 101. In one embodiment, the shape and structure of the test pattern included in the test structure 106 can be used to determine Whether the semiconductor device 102 manufactured on the wafer 101 meets the design requirements.

In one embodiment, the test structure 106 includes at least components such as the object to be tested, pads, and conductive paths, and is configured to receive the test signal and transmit the test signal to the input end of the object to be tested via the conductive path. The output terminal of the object transmits the measurement signal representing the test result to the external test instrument through the conductive path and the pad to detect whether the function of the object under test meets expectations. The detailed structure and function of the test structure 106 will be described in subsequent paragraphs. In one embodiment, during the semiconductor process for forming the semiconductor device 102, the test structure 106 is formed in the scribe lane area 104 at the same time. In one embodiment, the process of forming the test structure 106 is the same process as the process of forming the semiconductor device 102. Since the formation methods and parameters used for the semiconductor device 102 and the test structure 106 can be the same, defects found in the test structure 106 may also appear in the semiconductor device 102. Therefore, before a comprehensive test is performed, the test structure 106 is suitable as an indicator to monitor whether the manufacturing process is proper.

In some embodiments, the respective semiconductor device 102, the scribe lane area 104, and the test structure 106 in the scribe lane area are first formed on the wafers 101a, 101b, and 101c. The layout of these different wafers 101a, 101b, and 101c can be the same. Therefore, when multiple wafers 101a, 101b, and 101c are stacked on top of each other to form a semiconductor stack 100, their respective semiconductor devices 102 and scribe lane regions 104 can also be used. Align each other up and down. In some embodiments, the test structures 106 in different wafers 101a, 101b, and 101c may be different. In some embodiments, the test structures 106 in different wafers 101a, 101b, and 101c are electrically connected to each other through vias.

FIG. 1B is a cross-sectional view of the test structure 106 according to FIG. 1A along the section line AA according to an embodiment of the present invention. FIG. 1B shows an enlarged view of the wafer stack 100 in the scribe lane area 104. In the illustrated embodiment, the wafer stack 100 is composed of multiple (e.g., five) wafers 101 (e.g., wafers 101a, 101b, 101c, 101d, and 101e) stacked one above the other. In some embodiments, Each wafer 101 includes a substrate 112, a front-side interconnect structure 114, and a back-side interconnect structure 116 in the vertical direction of the scribe lane area 104. Although the semiconductor device 102 is not shown in FIG. 1B, the scribe lane area 104 and the semiconductor device 102 of each wafer 101 share the substrate 112, the front-side interconnect structure 114, and the back-side interconnect structure 116 therein. In some embodiments, some wafers 101 only include the front-side interconnect structure 114 or only the back-side interconnect structure 116. Functionally, the test structure 106 at least includes circuit structures or test patterns disposed in the substrate 112, the front-side interconnect structure 114, and the back-side interconnect structure 116, including, for example, the DUT 122, the conductive layer 124, the pads 126, and silicon. Channel 132.

The substrate 112 includes a semiconductor material, such as bulk silicon. In some embodiments, the substrate 112 is used as an interposer substrate. In some embodiments, the substrate 112 may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, and so on. In some embodiments, the substrate 112 is a p-type semiconducting substrate (acceptor type) or an n-type semiconducting substrate (donor type). Another option is that the substrate 112 includes another elemental semiconductor, such as germanium; compound semiconductors, including gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, or GalnAsP; or a combination thereof. In another embodiment, the substrate 112 is a semiconductor on insulator (SOI). In other embodiments, the substrate 112 may include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer laminated with another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In some embodiments, different wafers 101 may have different thicknesses. For example, the thickness of the lowermost wafer 101e is greater than the thickness of the upper wafer 101a, 101b, 101c, or 101d.

In some embodiments, one or more device under test (DUT) 122 is formed in the substrate 112. In FIG. 1B, the DUT 122 is a transistor, which may include a gate, a drain, a source, and other doped regions, conductive paths, or dielectric layers. However, to be The measured object 122 may also exist in other forms of circuits, such as resistors, inductors, capacitors, or other suitable circuit structures. In some embodiments, the DUT 122 includes a specific test pattern with a specific size and geometric structure for testing the reliability and accuracy of the manufacturing process of the semiconductor device 102.

The front-side interconnect structure 114 or the back-side interconnect structure 116 is used to electrically connect the DUT 114 to other devices or structures on the same wafer 101, or to electrically connect the components in different wafers 101 that are adjacent to each other. Device or structure. The front-side interconnect structure 114 may include a plurality of conductive layers 124. Each conductive layer 124 includes a conductive material, such as copper, titanium, tungsten, aluminum, silver, or a combination thereof. In some embodiments, each conductive layer 124 includes a multilayer structure, such as a diffusion barrier layer and a conductive filling layer. Each conductive layer 124 may include a horizontal conductive line 124a or a vertical conductive path 124b, wherein the horizontal conductive line 124a is electrically coupled to another adjacent horizontal conductive line 124a located above or below through at least one vertical conductive path 124b. In this embodiment, the number and structure of the horizontal conductive lines 124a and the vertical conductive paths 124b of the front-side interconnect structure 114 are shown for illustration. The front-side interconnect structure 114 may include other numbers of conductive layers and other wiring patterns.

Similar to the front-side interconnect structure 114, the back-side interconnect structure 116 may also include a plurality of conductive layers 124. Each conductive layer 124 may include a horizontal conductive line 124a or a vertical conductive path 124b, wherein the horizontal conductive line 124a is electrically coupled to another adjacent horizontal conductive line 124a located above or below through at least one vertical conductive path 124b. In this embodiment, the number and structure of the horizontal conductive lines 124a and the vertical conductive vias 124b of the backside interconnect structure 116 are shown for illustration. The backside interconnect structure 116 may include other numbers of conductive layers and other wiring patterns.

In addition, the front-side interconnect structure 114 includes a dielectric layer 136 for connecting the conductive layer 124 is electrically insulated from other components. Similarly, the backside interconnect structure 116 includes a dielectric layer 136 for electrically insulating the conductive layer 124 from other components. In some embodiments, the dielectric layer 136 fills a portion of the front-side interconnect structure 114 or the back-side interconnect structure 116 that is not part of the conductive layer 124. In some embodiments, the dielectric layer 136 may be formed of oxide, such as undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxide, silicon nitride, silicon oxynitride, low dielectric Coefficient material and so on. The low dielectric constant material may have a dielectric constant (k) value lower than 3.8, but the dielectric material of the dielectric layer 136 may also be close to 3.8.

In some embodiments, the front-side interconnect structure 114 includes the pads 126 of the test structure 106. The pad 126 is made of a conductive material, and is electrically connected to the other horizontal conductive lines 124a or the vertical conductive paths 124b of the front-side interconnect structure 114. In some embodiments, the pad 126 is the outermost conductive layer 124 of the front-side interconnect structure 114 or the back-side interconnect structure 116, and is used to connect the front-side interconnect structure 114 or the back-side interconnection of the upper and lower adjacent wafers 101. The pad 126 of the structure 116 is electrically connected. In some embodiments, the pad 126 is used to electrically connect a test instrument outside the wafer stack 100, which includes a test probe, and is used to select the address selection signal and the corresponding signal of the predetermined DUT 122 set by the test instrument. The test signal is transmitted to the test structure 106, and is used to transmit the test result of the predetermined test object 122 to the test instrument by contacting the probe thereon. In some embodiments, the pad 126 includes a selection pad 126a and a measurement pad 126b, wherein the selection pad 126a is configured to transmit a predetermined DUT address selection signal to a selection circuit or switch in the test structure 106 A circuit (not shown), and the measurement pad 126b is configured to transmit the test result of the DUT 122 to the test instrument via the front-side interconnect structure 114 or the back-side interconnect structure 116.

In some embodiments, the substrate 112 of the wafer 101 further includes a silicon via 132. The silicon via 132 includes conductive materials, such as copper, titanium, tungsten, aluminum, silver, or a combination thereof. In some embodiments, each silicon via 132 includes a multilayer structure, such as a layer of diffusion resistance. Barrier layer and a conductive filling layer. The silicon via 132 generally extends through the substrate 112 on which it is located, and is used to electrically connect the structures above and below the substrate 112 to each other. In some embodiments, the front-side interconnect structure 114 and the back-side interconnect structure 116 of the same wafer 101 are electrically connected via silicon vias 132 in the substrate. In some embodiments, the silicon vias 132 of the wafers 101 adjacent to each other vertically overlap each other. For example, the silicon vias 132 in the substrate 112d of the wafer 101d are aligned with the silicon vias 132 in the substrate 112e of the wafer 101e. The overlap in the vertical direction saves the area of the cutting lane area 114 occupied by the test structure 106. In some embodiments, the upper and lower adjacent silicon vias 132 and the pads 126 overlap in the vertical direction. For example, the silicon vias 132 in the substrate 112d of the wafer 101d are connected to the backside interconnect structure 116d of the wafer 101d. The pad 126 overlaps in the vertical direction, and also overlaps the pad 126 of the front-side interconnect structure 114d of the wafer 101d in the vertical direction, saving the area of the scribe lane area 114 occupied by the test structure 106.

In some embodiments, the wafer stack 100 uses the pads 126 of each wafer 101 to be electrically connected to each other, so that the test structure 106 is formed through the front-test interconnect structure 114, the back-test interconnect structure 116, and the silicon via 132. The electrical connection can span the entire wafer stack 100. Therefore, the address selection signal or clock signal of the test instrument can be transmitted to the pad 130 of the wafer 101a through the surface layer of the wafer stack 100 (for example, the front side 100F of the wafer 101a), and pass through the front side of different wafers 101. The connection structure 114 or the backside interconnection structure 116 is transferred to the DUT 122 in each wafer 101 for testing. Therefore, in some embodiments, the pads 126 of the upper and lower adjacent wafers 101 overlap in the vertical direction. For example, the pads 126 in the backside interconnect structure 116 of the wafer 101d are mutually opposite to the front side of the wafer 101e. The pads 126 of the connecting structure 114e overlap in the vertical direction to facilitate the bonding of the pads 126 and save the area of the cutting path area 114 occupied by the pads 126.

In some embodiments, the test structure 106 also includes other components, such as a selection circuit (not shown) and a switch circuit (not shown), which are used to transmit the address selection signal to the desired A certain DUT 122 of a certain specific wafer 101 is not transmitted to other DUTs 122 at the same time; or it is set to receive a certain DUT 122 from a certain specific wafer 101 The measurement results transmitted by each output terminal will not receive the measurement results of other objects to be measured and cause the measurement results to be mixed with signals of different objects to be measured. The related details of the selection circuit and the switch circuit will be described in the related description of FIG. 2.

FIG. 2 is a schematic diagram of a testing system 200 according to an embodiment of the present invention. The test system 200 includes the test structure 106 shown in FIGS. 1A and 1B. In some embodiments, the test system 200 includes a pad 126, a selection circuit 204, a switch circuit 206, and a DUT array 208. The pad 126 includes a selection pad 126a and a measurement pad 126b, and the related content has been described in It is explained in the related description of Figure 1B, so it will not be repeated.

The selection circuit 204 is electrically connected to the selection pad 126a via the conductive layer 210 (corresponding to the conductive layer 124 in the front-side interconnect structure 114 or the back-side interconnect structure 116). In some embodiments, the selection circuit 204 is configured to implement an address selection circuit or an address decoding circuit, which provides a predetermined address of the DUT array 208 via an address selection signal. In some embodiments, the selection circuit 204 is used to select transmission paths between the measurement pad 126 b and the predetermined array 208 of the object under test, wherein these transmission paths may be formed in the conductive layer 210. In some embodiments, the selection circuit 204 is composed of a transistor or a logic gate. In some embodiments, the selection circuit 204 includes a register or a flip-flop, such as a D-type flip-flop, an SR-type flip-flop, a multiplexer, a demultiplexer, or the like. The implementation of the selection circuit 204 described above is only an example, and other circuits that can implement the address selection function or the address decoding function in the existing technology can also be used to implement the selection circuit 204, which can be regarded as the scope of the disclosure.

In some embodiments, the selection circuit further includes a delay unit or a delay circuit (not shown, seen in FIG. 4A) for delaying the input test signal or clock signal. Delay circuit can be It is formed by a transistor or a logic gate, for example, a delay circuit is combined with a pair of reverse gates. The delay circuit can use flip-flops or logic gates for different combinations or serial connections to produce the effect of delaying signals, so that different DUT arrays 208 can be controlled by the same clock signal and receive test signals at different time points. Test without interfering with each other. In some embodiments, the transistor of the selection circuit 204 is formed in the substrate 112 of each wafer 101. In some embodiments, the lines connecting the selection circuit 204 or the selection circuit 204 and the switch circuit 206 or the selection pad 206a are formed in the conductive layer 124 of the front-side interconnect structure 114 or the back-side interconnect structure 116 of each wafer 101 .

In some embodiments, the switch circuit 206 is connected to the measurement pad 126b via a conductive layer 220, where the conductive layer 220 is similar to the conductive layer 124 of FIG. 1B and can be formed on the front side interconnect structure 114 or the backside of each wafer 101. Side interconnect structure 116. In some embodiments, the switch circuit is electrically connected to the DUT 122A via the conductive layer 230 and electrically connected to the DUT 122B via the conductive layer 240, wherein the conductive layer 230 or 240 is similar to the conductive layer 124 of FIG. 1B It can also be formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of each wafer 101. The test object 122A or 122B in the test object array 208 is similar to the test object 122 in FIG. 1B and can be formed on the substrate 112 of each wafer 101. In some embodiments, the switch circuit 206 is configured to receive the address selection signal of the selection circuit 204 to select the predetermined DUT 122A or 122B. In some embodiments, the switch circuit 206 is configured to open or close the connection between the input terminal or the output terminal of the DUT 122A or 122B and the outside. In some embodiments, the switching circuit 206 is composed of a transistor or a logic gate. In some embodiments, any switch in the switch circuit 206 includes a transmission gate or the like. For example, the transmission gate can be composed of a P-type transistor and an N-type transistor. The gates of the two transistors are connected but receive the selection signal of the opposite level (that is, the logically different voltage levels). The source or drain of the crystal is connected in pairs. Connect the test signal to be controlled to one end of the source or drain of the logic gate, and by setting the turn-on level of the selection circuit 204 (for example, logic high) The two transistor gates of the transmission gate controlled by the off level (such as the logic low level) or the off level (for example, the logic low level) can determine whether the test signal can pass from the source to the drain of the transmission gate, or from the drain to the source. The implementation of the transmission gate described above is only an example, and other circuits that can implement the switching function in the existing technology can also be used to implement the switching circuit 206, which can be regarded as the scope of the disclosure. In some embodiments, the transistors of the switching circuit 206 are formed in the substrate 112 of each wafer 101, and the conductive lines connecting the switches of the switching circuit 206 are formed on the front side of each wafer 101 through the layout of the conductive layer 124. In the interconnect structure 114 or the backside interconnect structure 116.

The DUT array 208 is electrically connected to the switching circuits 206a and 206b via the conductive layer 124 in the front-side interconnect structure 114 or the back-side interconnect structure 116. In some embodiments, the DUT 122A or 122B in the DUT array 208 includes the same or similar elements or structures in the semiconductor device 102, such as transistors, capacitors, resistors, inductors, doped regions, and dielectric layers. , Or other similar ones. In some embodiments, the DUT 122A or 122B has an input terminal for receiving the input test signal and an output terminal for providing a measurement signal for the test result. For example, the gate and base of the DUT 122A or 122B can be used as input terminals, and the drain or source can be used as output terminals. The implementation of the test object 122A or 122B described above is only an example, and other structures that can be used as the test objects 122A and 122B in the existing technology also belong to the scope of the present disclosure. In some embodiments, the DUT array 208 is formed in the substrate 112 of each wafer 101. In other embodiments, the DUT array 208 is formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of each wafer 101.

FIG. 3 is a schematic diagram of a wafer stack 100 according to an embodiment of the present invention. 1B and FIG. 3, FIG. 3 only shows a part of the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101 in the wafer stack 100, and the part of the interconnect structure 114 shown includes the outermost layer (possibly the most The upper or lowermost layer) is the conductive layer and includes the pad array. For example, part of the interconnect structure 114a~114e It includes the pad arrays 302-ax, 302-bx, 302-cx, 302-dx and 302-ex (x=1~N represents the location or order of the pads, and N represents the total number of pads), used to test The signal and the clock signal are transmitted to the DUT 122 of the respective wafers 101a~101e, and the measurement signal can be measured by the pad arrays 302-ax, 302-bx, 302-cx, 302-dx and 302-ex(x =1~N) Transmit to external test equipment. For the convenience of description, the letters (using the letter y as the general name) and numbers (using the letter x as the general name) added after the label of a particular pad 302 respectively indicate the number of the wafer 101 on which it is set and the number in the corresponding pad array 302 The position, for example, the pad 302-a1 represents the pad that is disposed on the wafer 101a and is located at the first position (x=1).

1B, FIG. 2 and FIG. 3, the pad array 302 may include a selection pad 126a and a measurement pad 126b. In addition, as shown in FIG. 2, each wafer 101 may include two layers of pad arrays 302 disposed on the upper and lower outermost conductive layers. However, for ease of description, FIG. 3 only shows one layer of each wafer 101. The conductive layer and its pad array 302 are described as needed.

In some embodiments, the pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex are arranged in rows or columns in the respective wafers 101a to 101e, for example, as shown in FIG. 3 In the embodiment of, the pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex each include a pad array 302-a1~302-aN, 302- consisting of N pads b1~302-bN, 302-c1~302-cN, 302-d1~302-dN and 302-e1~302-eN. In some embodiments, different pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex have the same sorting position (that is, the same value of x), regardless of whether they are arranged on the front side In the interconnection structure 114 or the backside interconnection structure 116, the positions in the respective wafers 101a to 101e or the front side interconnection structure 114 and the backside interconnection structure 116 are the same. In one embodiment, different pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex have the same sort position (that is, have the same x value) on their respective wafers. The coordinates of 101a~101e relative to the center point of the wafer surface are relative The same. In some embodiments, different pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex have the same sorted position (ie, have the same x value) that overlap each other in the vertical direction . In one embodiment, the pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex in each front-side interconnect structure 114 are the same as those in the back-side interconnect structure 116 in the same wafer 101 In the pad arrays 302-ax, 302-bx, 302-cx, 302-dx, and 302-ex, a pair of pads having the same sort position (that is, having the same x value) overlap each other in the vertical direction. In the present disclosure, if at least 20% of the area of one pad completely overlaps with another pad in the vertical direction, the two pads can be said to overlap in the vertical direction. In some embodiments, if at least 50% or at least 80% of the area of one pad completely overlaps with another pad in the vertical direction, the two pads can be said to overlap in the vertical direction. Since the test pads of the stacked wafers 101a~101e can be overlapped in the vertical direction, the test can be performed without completely staggering. Therefore, the area occupied by the pads can be fixed and will not increase with the number of stacked wafers. Increase, but the number of DUTs available for testing in individual wafers has not decreased, and may be more.

In some embodiments, the vertically stacked pads 302 (corresponding to the pads 126 of FIG. 1B and FIG. 2) of the wafers 101a to 101e stacked on top of each other are electrically connected to each other to form a test structure as shown in FIG. 1B or FIG. 2 106, and the structures constituting these electrical connections are represented by conductive structures 304, 306, and 308 in FIG. 3. In the following description, the letters (using the letter y as the generic name) and numbers (using the letter x as the generic name) added after the label of the conductive structure (ie 304, 306 or 308) respectively indicate the number of the wafer 101 on which it is set and the corresponding The positions in the pad array 302, for example, the conductive structure 304-a1 represents a conductive structure disposed on the wafer 101a and corresponding to the position x=1 of the pad 302.

In one embodiment, the conductive structures 304, 306, and 308 may be composed of the conductive layer 124 in the front-side interconnect structure 114 or the back-side interconnect structure 116 of FIG. 1B and the silicon via 132 in the substrate 112. In one embodiment, the conductive structures 304, 306, and 308 may be electrically conductive at multiple levels The line 124a is connected with the vertical conductive path 124b, and the silicon path 132 is formed. 1B, the rectangular area Z1 defined by the Yushu line includes a part of the dicing area 104 of the wafers 101d and 101e stacked on top of each other, and the wafer 101d and the wafer 101e each include pads P1 and P2, wherein the pad P1 And P2 silicon overlaps in the vertical direction, and its configuration is similar to that of the pad 302 overlapped in the vertical direction in FIG. 3. From the example circuit of the rectangular area Z1, it can be seen that the pads P1 (in this example, the pad array 302 of FIG. 3 represents the pads of the outermost conductive layer located on the upper side) via multiple layers in the front-side interconnect structure 114 of the wafer 101d The horizontal conductive line 124a and the multi-layer vertical conductive path 124b are electrically connected to the silicon path V1 in the substrate 112d of the wafer 101d, and then pass through the vertical conductive path 124b and the pads in the backside interconnect structure 116 of the wafer 101d P3 (in this example, the pad array 302 of FIG. 3 represents the pad of the outermost conductive layer located below) is electrically connected to the pad P2 in the front-side interconnect structure 114 of the wafer 101e.

In some embodiments, at least a part of the interconnect structure used to electrically connect the pads P1 and P2 (such as the silicon via V1 or the vertical conductive via 124b) overlaps the pads P1 and P2 in the vertical direction, which can reduce mutual The length of the connecting structure and the area occupied by the cutting track area 104 can save wiring space and improve the resistance-capacitance delay (RC-delay) effect caused by the interconnection structure. In some embodiments, if the pads in the same wafer 101 need to be electrically connected, they can be horizontally connected by the conductive layer 124 in the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101. The electrical connection.

Refer to Figure 3 again. In one embodiment, the test signal and the measurement signal are transmitted through different pads 302, so the pads 302 can be divided into different groups due to their functions, and correspond to the first conductive structures 304, 304, and 304 of the different pad groups. The configuration of the second conductive structure 306 and the third conductive structure 308 may also be different. In one embodiment, the test control signal is transmitted to the different wafers 101a~101e through the first pad group 302-yN (y=a, b, c, d, e), and the first pad group 302-yN (y=a, b, c, d, e) The pad group 302-yN can correspond to the selection pad 126a of FIG. 2 for receiving a clock signal, an address selection signal, or a power reference voltage. The clock signal, address selection signal, or power reference voltage can be connected to the wafer stack 100 through the top pad of the first pad group 302-yN (for example, the pad 302-aN of the wafer 101a), and then through The first conductive structures 304-aN, 304-bN, 304-cN, and 304-dN are transferred to the wafers 101b~101e. The first conductive structures 304-aN, 304-bN, 304-cN, and 304-dN correspond to Figure 2 The conductive layer 210 can be formed on the wafers 101a, 101b, 101c, 101d, and 101e, depending on whether the pads in the first pad group 302-yN are located on the uppermost conductive layer or the lowermost layer of the wafer 101. Depends on the conductive layer. The transmission path of the clock signal Clock (represented by a dotted line) is first transmitted from the test instrument to the pad 302-aN to reach the wafer 101a, and then passes through the first conductive structures 304-aN, 304-bN, 304-cN, and 304- dN reaches the wafers 101b~101e, respectively. In one embodiment, the first conductive structure 304 corresponds to the conductive layer 210 of FIG. 2 and is used to electrically connect the first pad group 302-yN (y=a, b, c, d, e) and not shown Now it corresponds to the other pads 302-yx (x=1~N-1). Regardless of the time delay caused by the first conductive structures 304-aN, 304-bN, 304-cN, and 304-dN, the clock signal can be regarded as arriving at each wafer 101a-101e at the same time. Then, the clock signal is horizontally transmitted to each selection circuit through the conductive layer 124 of the front-side interconnect structure 114 or the back-side interconnect structure 116 of each wafer 101 to test and select a predetermined DUT 122 at a predetermined time.

In one embodiment, the test signal Data is generated by a built-in signal generator (not shown, which can be formed in the substrate 112e of the wafer 101e, for example), and the measurement signal generated by the test result is generated by the second The pad group 302-yx (y=a, b, c, d, e; x=2~N-1) is composed of the pad group 302-yx, which can correspond to the measurement pad 126b in FIG. 2. The transmission path of the test signal Data (indicated by the dotted line) is first sent from the first wafer to be side (for example, wafer 101e), and reaches different side objects 122 in the wafer 101e in sequence according to the different cycles of the clock signal. . Whenever the test signal Data (or address Select signal) When a DUT is turned on at 122, the obtained measurement signal is transmitted to the testing machine using one or more of the pads 302-ex (x=2~N-2). Different DUTs 122 use the same test signal Data for testing during different clock periods, and use the common measurement pad 302-ex (x=2~N-2) to transmit the measurement signal until the wafer 101e The last DUT 122 completes the test. The measurement signal of the pad 302-ex of the wafer 101e is through the second conductive structure 306-dx, 306-cx, 306-bx and 306-ax (x=2~N-2) and the second pad group 302-dx, 302-cx, 302-bx and 302-ax are transmitted to the testing machine. In some embodiments, the second conductive structures 306-ax, 306-bx, 306-cx, and 306-dx are formed on the wafers 101a to 101e, respectively, depending on the second pad groups 302-dx, 302-cx, The pads in 302-bx and 302-ax are arranged on the uppermost conductive layer or the lowermost conductive layer of the wafer 101 where they are located. In one embodiment, the second conductive structure 306 corresponds to the conductive layer 220 of FIG. 2 and is used to electrically connect the second pad group 302-yx (y=a, b, c, d, e; x=2 ~N-2) does not appear in the corresponding other pads 302-yx (x=1, N-1, N).

When the last test object 122 in the wafer 101e is tested or the test is completed, the test signal Data is simultaneously transmitted to the wafer 101d, and a test process similar to that of the wafer 101e is performed in the wafer 101d. The test signal Data arrives at different side objects 122 in the wafer 101d in sequence according to different cycles of the clock signal. Whenever the test signal Data (or address selection signal) turns on a DUT 122, the obtained measurement signal uses one or more of the pads 302-dx (x=2~N-2) Transfer to the test machine. Different DUTs 122 use the same test signal Data for testing during different clock periods, and use the common measurement pad 302-dx (x=2~N-2) to transmit the measurement signal until the wafer 101d The last DUT 122 completes the test. The measurement signal of the pad 302-dx of the wafer 101d is through the second conductive structures 306-cx, 306-bx, and 306-ax (x=2~N-2) and the second pad group 302-cx, 302-bx and 302-ax are transmitted to the testing machine.

When the last DUT 122 of the wafer 101d is tested or the test is completed, The test signal Data will be transmitted to the wafer 101c. The above-mentioned transmission sequence of the test signal Data or the test sequence of the DUT 122 is only an example, and the sequence of the test signal Data passing through different wafers 101a to 101e can be changed according to requirements. When the test signal Data reaches each wafer 101a~101e, all the objects to be tested in the same wafer 101 will be tested before the next wafer 101 is tested, and the same wafer 101 The test time of the different DUT 122 is separated by the period of the clock signal. This ensures that different wafers 101 or different DUTs 122 can share the second pad group 302-yx (y=a, b, c, d, e; x=2~N-1) during the test process The measurement signal is sent to the test instrument without signal interference caused by the simultaneous transmission of the measurement signal.

In some embodiments, the third pad group is electrically connected to the third conductive structure 308 so that the test signal Data is transmitted between the wafers 101 connected up and down. For example, when the test signal Data reaches the last DUT 122 of the wafer 101e for testing, it is also transmitted to the wafer 101d. In one embodiment, the test signal Data is first transmitted to the pad 302-e(N-1) above the wafer 101e, which faces the pad 302-d(N-1) facing the wafer 101d facing the wafer 101e -1). Since the pad 302-e (N-1) and the pad 302-d (N-1) are electrically connected through bonding, the test signal Data is directly transmitted to the wafer 101d. In an embodiment, the third conductive structure 308-d(N-1) may correspond to the conductive layer 220 of FIG. 2 and may be formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101d.

When the test signal Data reaches the pad 302-d (N-1) of the wafer 101d, the transmission path of the front-side interconnect structure 114 or the back-side interconnect structure 116 is used to transmit the test signal Data to the first test signal of the wafer 101d. Object 122, and perform tests on other objects to be tested in sequence. When the test signal Data reaches the last DUT 122 of the wafer 101d, it is also sent to the pad 302-d1. In one embodiment, the pad 302-d1 and the pad 302-c1 are directly bonded or electrically connected through the third conductive structure 308-c1, so that the test signal Data can be transmitted from the wafer 101d to the wafer 101c, where the third conductive structure 308-c1 may correspond to the conductive layer 220 of FIG. 2 and may be formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101c.

According to the above-mentioned transmission method of the test signal Data, the test structure 106 is configured to transmit the test signal Data to the pad 302-c (N- 1). The pads 302-c (N-1) and 302-b (N-1) are directly connected or electrically connected through the third conductive structure 308-b (N-1), so that the test signal Data can be transmitted from the wafer 101c To the wafer 101b, the third conductive structure 308-b(N-1) may correspond to the conductive layer 220 of FIG. 2 and may be formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101c. Furthermore, the pad 302-b1 and the pad 302-a1 are directly bonded or electrically connected through the third conductive structure 308-a1, so that the test signal Data can be transmitted from the wafer 101b to the wafer 101a, wherein the third conductive structure 308-a1 may correspond to the conductive layer 220 of FIG. 2 and may be formed in the front-side interconnect structure 114 or the back-side interconnect structure 116 of the wafer 101a. Finally, when the test signal Data is output to the pad 302-a (N-1) through the last DUT 122 of the wafer 101a and sent to the testing machine, it indicates that all DUTs 122 have been tested.

In one embodiment, the third conductive structure 308 is only used to electrically connect to the third pad group 302-yx (y=a, b, c, d, e; x=1, N-1). Now it corresponds to the other pads 302-yx (x=2~N-2, N). Furthermore, the third conductive structure 308 is different from the first conductive structure 304 in that each of the third conductive structures 308 only electrically connects two overlapping pads of two adjacent wafers, and is located at the same position (by x represents) the third conductive structure 308 will not continuously appear on adjacent wafers to ensure that when the test signal Data reaches the first wafer 101 to be tested, it will pass through all the tested objects 122 before continuing. Transfer to the next wafer 101 to be tested.

The above-mentioned pad group classification is only an example, and the present disclosure may also have other pad grouping methods.

FIG. 4A is a schematic diagram of a test circuit 400 according to an embodiment of the present invention. The test circuit 400 may be formed in the stacked wafer 101, and FIG. 4A only shows two adjacent wafers 101d and 101e as an example, and the test circuit of the present disclosure is not limited to the embodiment of FIG. 4A.

As shown in FIG. 4A, the test circuit of the wafer 101e includes test objects e1, 122-e2, ... 122-eK (K represents the total number of test objects) and a selection circuit, wherein the selection circuit includes a register R11, R12...R1K are used to respectively transmit the test signal Data to the corresponding DUT 122-e1~122-eK. The test circuit of the wafer 101e also includes a plurality of delay units L11~L1K respectively corresponding to the registers R11~R1K. In one embodiment, each of the test objects 122-e1 to 122-eK includes a transistor (similar to the test object 122A or 122B in FIG. 2), which has a gate to receive the test signal Data. In one embodiment, the registers R11~R1K include D-type flip-flops, which include a data input terminal D, a data output terminal Q, and a clock input terminal Clk. The registers R11~R1K are connected in series to make the temporary storage The data input terminal D of the register R12~R1K is connected with the data output terminal Q of the previous stage register R11~R1 (K-1). In one embodiment, the circuit connecting the registers R11 to R1K and the DUT 122-e1 to 122-eK may correspond to the conductive layer 210, 230, or 240 in FIG. 2.

The data input terminal D of the first stage register R11 receives the test signal Data from the signal generator, which has a signal length T_d. The delay units L11~L1K are connected in series, so that the clock input terminal Clk of the register R11 receives the clock signal Clock of the test instrument through the delay unit L11, where the clock signal Clock can pass through the first pad shown in Figure 3 The group 302yN and the first conductive structure 304 are transmitted and have a period T_c. In an embodiment, the signal length T_d is greater than the period T_c.

The clock input Clk of each of the registers R12~R1K is connected to the clock signal Clock transmitted by the previous-stage delay units L11~L1K via a corresponding delay unit L12~L1K. In one embodiment, each of the registers R11~R1K has substantially the same output delay. The delay time TL1, and each of the delay units L11 to L1K has substantially the same delay time TL2. In one embodiment, the delay time TL1 is greater than the delay time TL2, so that the serially connected front and rear registers can output the test signal Data through different clock cycles.

The test circuit of the wafer 101d includes the objects to be tested 122-d1, 122-d2,...122-dK and a selection circuit. The selection circuit includes registers R21, R22...R2K to separate the test signal Data Send to the corresponding test object 122-d1~122-dK. The test circuit of the wafer 101d also includes a plurality of delay units L21~L2K respectively corresponding to the registers R21~R2K. In one embodiment, each of the test objects 122-d1 to 122-dK includes a transistor (similar to the test object 122A or 122B in FIG. 2), which has a gate to receive the test signal Data. In one embodiment, the registers R21~R2K include D-type flip-flops, which include a data input terminal D, a data output terminal Q, and a clock input terminal Clk. The registers R21~R2K are connected in series to make the temporary storage The data input terminal D of the register R22~R2K is connected with the data output terminal Q of the previous stage register R21~R2(K-1). The data input terminal D of the first stage register R21 is connected to the data output terminal Q of the register R1K of the wafer 101e, and the data output terminal Q of the last stage register R2K is connected to the next wafer The data input terminal D of the register 101 (for example, wafer 101c, not shown in FIG. 4A) is connected. The delay units L21~L2K are connected in series, so that the clock input terminal Clk of the register R21 receives the clock signal Clock of the test instrument through the delay unit L21, and the clock input terminal Clk of each register R22~R2K It is connected to the clock signal Clock transmitted by the previous-stage delay unit L21~L2K through a corresponding delay unit L22~L2K.

In one embodiment, the circuit connecting the registers R21 to R2K and the DUT 122-d1 to 122-dK may correspond to the conductive layer 210, 230, or 240 in FIG. 2. In one embodiment, each of the registers R21~R2K has substantially the same output delay time TL1, and each of the delay units L21~L2K has substantially the same delay time TL2. In one embodiment, when the delay is The time TL1 is greater than the delay time TL2, so that the serially connected front and rear registers can output the test signal Data through different clock cycles.

FIG. 4B is a waveform diagram 400 of a test circuit according to an embodiment of the present invention. 4A and 4B, the test signal Data is generated by the signal generator at time T0 and arrives at the data input terminal D of the register R11 at time T1, and the clock signal Clock is generated at time T0 and at time T2 It reaches the clock input terminal R11-Clk of the register R11 and the clock input terminal R21-Clk of the register R21, where the time T2 is later than the time T1. The register R11 can output the data of the data input terminal D to the output terminal Q after a delay time TL1 is passed on a trigger edge (such as a rising edge or a falling edge) according to the clock signal Clock. In the embodiment of FIG. 4B, the rising edge of the clock signal Clock (labeled as rising arrows W1 and W2) is used as the trigger edge for the signal output from the trigger registers R11~R1K, where Wi represents the rising edge of the i-th cycle .

After the register R11 receives the rising edge W1 of the clock signal Clock, the test signal Data is output to the data output terminal R11-Q at time T4 after a delay time TL1. 4A, the data output terminal R11-Q of the register R11 transmits the test signal Data to the DUT 122e-1 and the next-level register R12-D. Therefore, at time T4, the input terminal of the DUT 122-e1 receives the test signal Data (for example, used to bias the gate and base of a transistor) and measures the signal (for example, drain or source). The extreme voltage value or current value) is transmitted to the testing instrument through the second pad group 302yx (x=2~N-2) and the second conductive structure 306 in FIG. 3. It can be seen from the above description that the test object 122e-1 is tested during the first period corresponding to the rising edge W1. In one embodiment, after the register R11 measures the object 122-e1 under test, the selection circuit 204 or the switch circuit 206 shown in FIG. 2 turns off the object 122-e1 under test. In one embodiment, after the register R11 completes the measurement of the DUT 122-e1 and the rising edge W2 of the clock signal has passed, the selection circuit 204 or the switch circuit 206 shown in FIG. 2 sets the DUT 122 -e1 is off.

In addition, at the same time, the delay unit L11 corresponding to the register R11 outputs the clock signal to the delay unit L12 and reaches the clock input terminal R12-Clk of the register R12 at time T3 after the delay time TL2. Since the delay time TL1 is greater than the delay time TL2, the time T3 is earlier than the time T4, so the data output terminal R12-Q of the register R12 does not output the test signal Data at the time T3. Therefore, after the time T4, except for the test object 122-e1, the other test objects (for example, the test objects 122-e2~122-eK) have not received the test signal Data, so they are closed. The second rising edge W2 of the clock signal clock reaches the clock input terminal R12-clk of the register R12 at time T5 after a period T_c. At this time, the register R12 receives the rising edge W2 of the clock signal Clock After the delay time TL1, the test signal Data is output to the data output terminal R12-Q at time T6.

The data output terminal R12-Q of the register R12 transmits the test signal Data to the DUT 122e-2 and the register R13-D of the next stage. Therefore, at time T6, the input terminal of the DUT 122-e2 receives the test signal Data (for example, used to bias the gate and base of a transistor) and measures the signal (for example, drain or source). The extreme voltage value or current value) is transmitted to the testing instrument through the second pad group 302yx (x=2~N-2) and the second conductive structure 306 in FIG. 3. It can be seen from the above description that the test object 122e-2 is tested during the second period corresponding to the rising edge W2. In one embodiment, after the register R12 measures the object 122-e2 under test, the selection circuit 204 or the switch circuit 206 shown in FIG. 2 turns off the object 122-e2 under test. In one embodiment, when the register R12 completes the measurement of the test object 122-e2, and after the next rising edge of the clock signal (that is, the first rising edge after the rising edge W2), as shown in FIG. 2 The illustrated selection circuit 204 or switch circuit 206 turns off the DUT 122-e2.

The above-mentioned test process of the test objects 122-e1 and 122-e2 continues to the last register R1K of the wafer 101e. At time T7, the Kth cycle of the clock signal Clock The WK-th rising edge of the signal reaches the clock input terminal R1K-Clk, and after the delay time TL1, the register R1K outputs the test signal Data to the data output terminal R1K-Q at time T8 and the test signal Data is connected The test object 122-eK is received to complete the test of the wafer 101e.

3 and 4A, the data output terminal R1K-Q of the register R1K is also electrically connected to the pad 302-e (N-1), and through the third conductive structure 308-d (N-1) or wafer The front-side interconnect structure 114d or the back-side interconnect structure 116d of 101d is electrically connected to the data input terminals R21-D of the register R21. Therefore, considering that the delay time of the line transmission is negligible, the time T8 when the test signal Data reaches the data output terminal R1K-Q can be regarded as the time to reach the data input terminal R21-D. Since the time T8 is later than the arrival time T7 of the rising edge WK, the data output terminal R21-Q of the register R21 does not output the test signal Data at the time T8. Therefore, after the time T8, except for the DUT 122-eK, other DUTs (for example, the DUT 122-d1~122-dK) have not received the test signal Data, so they are closed. The (K+1)th rising edge W(K+1) of the clock signal clock reaches the clock input terminal R21-clk of the register R21 at time T9 after a period T_c, and the register R21 receives After the rising edge W(K+1) of the clock signal Clock, after a delay time TL1, the test signal Data is output to the data output terminal R21-Q at time T10 and transmitted to the DUT 122-d1.

FIG. 5 is a flowchart of a testing method 500 according to an embodiment of the present invention. The test method 500 can be performed with reference to FIG. 3 and FIGS. 4A and 4B. The test method 500 is only an example, and other steps can be added or removed, or the order between steps can be changed. In step 502, the clock signal (for example, the clock signal Clock) is transmitted to the first register (for example, register R11) of the first wafer (for example, wafer 101e) and the second wafer (for example, wafer 101d) ) Of the second register (for example, register R21). In one embodiment, the first wafer and the second wafer form a wafer stack. In step 504, at the first edge (for example, rising edge W1) of the clock signal, pass the first temporary The memory transmits the test signal (for example, the test signal Data) to the first DUT (for example, the DUT 122-e1).

In some embodiments, the step of transmitting the clock signal to the first register of the first wafer and the second register of the second wafer includes passing through the third pad of the first wafer (for example, the third pad of FIG. 3). The pad 302-eN) and the fourth pad of the second wafer (for example, the pad 302-dN of FIG. 3) transmit the clock signal to the first register and the second register, wherein the third pad And the fourth pad is aligned in the vertical direction.

In some embodiments, the clock signal (for example, the clock signal R1K-Clk in FIG. 4B) passes a delay time (for example, the edge WK at time T7) is transmitted to the third register ( For example, the register R1K in Figure 4A).

In some embodiments, the data input terminal of the second register (for example, the data input terminal D of the register R21 in FIG. 4A) is connected to the data output terminal of the third register (for example, the data input terminal of the register R1K in FIG. 4A). Data output terminal Q).

In step 506, the first measurement signal is transmitted through the first pad of the first wafer (for example, the second pad group 302-e2~302-e(N-2)). In step 508, at the second edge (for example, rising edge W(K+1)) of the clock signal, transmit the test signal to the second DUT (for example, DUT 122) via the second register -d1). In step 510, the second measurement signal is transmitted through the second pad of the second wafer (for example, the second pad group 302-d2~302-d(N-2)). The first pad and the second pad are aligned in a vertical direction.

FIG. 6 is a flowchart of a testing method 600 according to an embodiment of the present invention. The test method 600 can be performed with reference to FIG. 3 and FIGS. 4A and 4B. The test method 600 is only an example, and other steps may be added or some steps may be removed, or the order between the steps may be changed. In step 602, the clock signal (such as the clock signal Clock) is sent to the first register of the first wafer (such as wafer 101d) (E.g., register R21) and a second register (e.g., register R1K) of the second wafer (e.g., wafer 101e), wherein the first wafer further includes a first object to be tested (e.g., object to be tested) 122-d1), the second wafer further includes a second object to be tested (for example, the object to be tested 122-eK), and the first wafer and the second wafer form a wafer stack. In step 604, the test signal (for example, the test signal Data) is sent to the second register. In step 606, the test signal is transmitted to the second DUT and the first register via the second register at the first time of the clock signal (for example, time T8 in FIG. 4B). In step 608, at the second time of the clock signal (for example, time T10 in FIG. 4B), the test signal is transmitted to the first DUT via the first register, wherein the second time is later than the first timing.

In one embodiment, the step of transmitting the test signal to the first register via the second register at the first time of the clock signal includes sending the test signal via the first register (for example, register R21) The data output terminal (Q), the third pad of the second wafer (such as pad 302-eN in FIG. 3) and the fourth pad of the first wafer (such as pad 302-dN in FIG. 3) are transferred to the first The register, in which the third pad and the fourth pad overlap in the vertical direction.

FIG. 7 is a flowchart of a method 700 for manufacturing a semiconductor device according to an embodiment of the present invention. For the semiconductor device manufacturing method 700, refer to FIGS. 1, 3, and 4A and 4B. The semiconductor device manufacturing method 700 is only an example, and other steps may be added or some steps may be removed, or the order between steps may be changed. In step 702, a plurality of wafers (for example, wafer 101 in FIG. 1) are provided. In step 704, the device area and dicing lane area of each wafer are defined in the wafers (such as the dicing lane area 104 of FIG. 1), and a semiconductor device (such as the semiconductor device 102 of FIG. 1) is formed in the device area. ). In one embodiment, the process of forming the semiconductor device includes development, exposure, ion implantation, etching, polishing, and the like. In step 706, a test pattern is formed in the scribe lane area (for example, the test structure 106 in FIG. 2, FIG. 3, and FIG. 4). In step 708, the crystal circle A wafer stack (such as the wafer stack 100 in FIG. 1) is formed, and a test structure (such as the test structure 106 in FIG. 1) is formed according to the test patterns in the wafers. In step 710, the test structure is tested. In one embodiment, the test method uses the test method described in FIG. 2, FIG. 3, FIG. 4A, and FIG. 4B). In step 712, it is confirmed whether the test result meets the design specification. If the test result does not meet the design specification, the semiconductor device manufacturing method 700 proceeds to step 714 to improve the semiconductor device in the wafer stack or discard the wafer stack. If the test result meets the design specification, the semiconductor device manufacturing proceeds to step 716 to dicing the wafer stack. In one embodiment, when the wafer stack is diced, part or all of the test structure is removed. After the wafer stack is cut, individual semiconductor dies are produced. In one embodiment, the individual semiconductor die is packaged.

In an embodiment of the present disclosure, a method for testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer; At the first edge, the test signal is transmitted to the first DUT through the first register; the first measurement signal is transmitted through the first pad of the first wafer; at the second edge of the clock signal, Transmit the test signal to the second DUT via the second register; and transmit the second measurement signal via the second pad of the second wafer, wherein the first pad and the second pad are in a vertical direction Aligned.

In an embodiment of the present disclosure, a method for testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer, wherein the first wafer It also includes a first object to be tested, the second wafer also includes a second object to be tested, and the first wafer and the second wafer form a wafer stack; transmitting a test signal to the second register; Transmitting the test signal to the second DUT and the first register via the second register at the first time of the clock signal; and the test signal at the second time of the clock signal Through the A register is transmitted to the first DUT, wherein the second time is later than the first time.

In an embodiment of the present disclosure, a semiconductor structure includes a first wafer (such as the wafer 101e in FIG. 1B) and a second wafer (such as the wafer 101d in FIG. 1B). The first wafer includes a plurality of first semiconductor devices (such as the semiconductor device 102 of FIG. 1A) and a first separation region (such as the separation region 106 of FIG. 1A) separates the first semiconductor devices, wherein the first separation region includes The first pad (for example, the measurement pad 126b in FIG. 1B), the first object to be measured (for example, the object under test 122 in FIG. 1B), and the first circuit (for example, the selection circuit 204 or the switch circuit 206 in FIG. 2), the first A circuit is configured to test the first object under test according to a test signal, and the first pad is configured to transmit a first measurement signal of the first object under test. The second wafer includes a plurality of second semiconductor devices (such as the semiconductor device 102 of FIG. 1A) and a second separation region (such as the separation region 106 of FIG. 1A) separates the second semiconductor devices, wherein the second separation region includes The second pad (for example, the measurement pad 126b in FIG. 1B), the second object to be measured (for example, the object under test 122 in FIG. 1B), and the second circuit (for example, the selection circuit 204 or the switch circuit 206 in FIG. 2), the first The two circuits are configured to test the second object under test according to the test signal, and the second pad is configured to transmit a second measurement signal of the second object under test. The first pad is aligned in a vertical direction and electrically connected to the second pad. The first circuit and the second circuit are further configured to test the first object under test and the second object under test at different times.

In one embodiment, the first circuit further includes a register (for example, register R11 in FIG. 4A) to receive the test signal, and a delay unit (for example, delay unit L11 in FIG. 4A), wherein the delay unit passes through the first crystal The third round pad (for example, pad 302-eN in FIG. 3) receives the clock signal and transmits the clock signal to the register.

The features of several embodiments are described above, so those skilled in the art can better understand the aspect of the present invention. Those who are familiar with the art should understand that they can directly use the present invention as a basis for designing or modifying other processes or structures to achieve the same purpose of the embodiments introduced in this specification And/or achieve the same advantages. Those familiar with the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions and substitutions can be made in this specification without departing from the spirit and scope of the present invention.

500: method

502: Step

504: Step

506: step

508: step

510: Step

Claims (10)

A method of testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer; A register transmits the test signal to the first DUT; transmits the first measurement signal through the first pad of the first wafer; when the clock signal is at the second edge, transmits it through the second register The test signal is transmitted to the second object to be tested; and the second measurement signal is transmitted through the second pad of the second wafer, wherein the first pad and the second pad are aligned in a vertical direction. The method according to claim 1, wherein the step of transmitting the clock signal to the first register of the first wafer and the second register of the second wafer includes passing through the third pads of the first wafer, respectively And the fourth pad of the second wafer transmits the clock signal to the first register and the second register, wherein the third pad and the fourth pad are aligned in a vertical direction. The method according to claim 1, further comprising transmitting the clock signal to the third register of the first wafer after a delay time. The method according to claim 3, wherein the data input terminal of the second register is connected to the data output terminal of the third register. A method for testing a semiconductor device includes: transmitting a clock signal to a first register of a first wafer and a second register of a second wafer, wherein the first wafer further includes a first object to be tested, The second wafer further includes a second object to be tested, and the first wafer and the second wafer form a wafer stack; the test signal is transmitted to the second register; the test signal is at the clock The first time of the signal is transmitted to the second DUT and the first register via the second register; and the test signal is transmitted via the first register at the second time of the clock signal To the first test object, the second time is later than the first time. The method according to claim 5, wherein the first time is the first edge of the clock signal and is delayed by a delay time, and the second time is the second edge of the clock signal, and the second edge is The time between the first edge is the period of the clock signal. The method according to claim 5, further comprising transmitting the first measurement signal of the first object under test through the first pad of the first wafer, and transmitting the second measurement signal through the second pad of the second wafer The second measurement signal of the object under test. The method according to claim 5, wherein transmitting the test signal to the first register via the second register at the first time of the clock signal includes passing the test signal via the first register The data output terminal of the second wafer, the third pad of the first wafer, and the fourth pad of the first wafer are transferred to the first register, wherein the third pad and the fourth pad overlap in a vertical direction. A semiconductor structure includes: a first wafer including a plurality of first semiconductor devices and a first separation region to separate the first semiconductor devices, wherein the first separation region includes a first pad, a first object to be tested, and A first circuit configured to test the first object under test according to a test signal, and the first pad is configured to transmit a first measurement signal of the first object under test; and a second wafer , Including a plurality of second semiconductor devices and a second separation area to separate the second semiconductor devices, wherein the second separation area includes a second pad, a second DUT, and a second circuit, and the second circuit is configured to The second object under test is tested according to the test signal, and the second pad is configured to transmit a second measurement signal of the second object under test, wherein the first pad is aligned in the vertical direction and electrically connected to the second object Two pads, the first circuit and the second circuit are further configured to test the first DUT and the second DUT at different times. The semiconductor structure according to claim 9, wherein the first circuit further comprises: a register configured to receive the test signal; and a delay unit configured to receive the clock signal via the third pad of the first wafer and Send the clock signal to the register.

Images