TWI529738B - Flash -backed dram module with state of health and or status information available through a configuration data bus - Google Patents

Description

Have a health status and/or status available via the configuration data bus Flash Flash Memory DRAM Module

The present application claims priority to U.S. Patent Application Serial No. 12/369,027, filed on Feb. 11, 2009. Priority of U.S. Patent Application Serial No. 12/369,040, filed on Feb. 11; priority to U.S. Patent Application Serial No. 12/369,046, filed on Feb. 11, 2009; US Patent Application Serial No. 12/369,052; priority to U.S. Patent Application Serial No. 12/369,076, filed on Feb. 11, 2009; Priority to PCT Patent Application No. PCT/US09/33755, filed on Feb. 11, 2009.

The disclosed subject matter relates to a phased flash flashback dual-line memory module (DIMM) module.

Digital processing devices such as RAID systems sometimes use, for example, a memory cache to improve the performance of read and write operations. Volatile memory is typically used to implement the cache. However, if the power source of the volatile memory fails, the data stored in the volatile memory may be lost. In addition, volatile memory devices such as DRAM memory modules typically require certain parameters describing the nature of the DRAM device that is to be placed in a separate non-volatile memory located on the memory module. The module. An example of this is Sequence Presence Detection (SPD). However, the storage of this information may only require the addition of the entire non-volatile memory to the volatile memory for this purpose.

The present disclosure relates to a flash memory dual-line memory module (DIMM) module that includes a non-volatile memory, a volatile memory, and a controller. During normal operation, the DIMM is powered by a primary power source. When the primary power source is interrupted, an alternate power source supplies sufficient temporary power to the DIMM to allow the controller to transfer data from the volatile memory to the non-volatile memory before the power from the alternate power source is exhausted. in. When the primary power source becomes available again, the controller transmits the data stored in the non-volatile memory back to the volatile memory. When the controller moves the data from the volatile memory to the non-volatile memory, the controller places the memory portion of the data to be moved into a normal operation state, and the memory portion of the data is not moved. Placed in a low power state.

In one aspect, a memory device for use with a primary power source includes: a volatile memory including a plurality of memory portions, the complex Each of the plurality of memory portions has a normal operating state and a low power state; an interface for connecting to a standby power source configured to power at one of the primary power sources Temporarily supplying power to the volatile memory after the loss occurs; a non-volatile memory; and a controller communicating with the volatile memory and the non-volatile memory and being programmed to detect the primary power source One of the power losses, and each time at least one of the memory portions is responsive to moving the data from the volatile memory to the non-volatile memory, and when moving the data from the volatile memory to the non-volatile memory, it will be positive The portion of the memory from which the mobile data is placed is placed in a normal operating state, and the portion of the memory from which the data is not being moved is placed in a low power state.

In another aspect, a method includes detecting a power failure of a primary power source of a volatile memory, the volatile memory including a plurality of memory portions, each of the plurality of memory portions Having a normal operating state and a low power state; and in response to detecting the power failure and when the volatile memory is powered by a backup power source: at least one memory portion is stored in the volatile memory each time The data in the middle moves to the non-volatile memory; and when the data is moved from the volatile memory to the non-volatile memory, the memory portion from which the data is being moved is placed in a normal operating state, and will not be positive The mobile data is placed in a low power state from the memory portion.

In another aspect, a memory device for use with a primary power source includes: a volatile memory including a plurality of memory segments, the plurality of memory segments being at least one start address and a corresponding at least one end address definition; an interface for connecting to an alternate power source configured to be present after a power loss from one of the primary power sources occurs Powering the volatile memory; a non-volatile memory; and a controller communicating with the volatile memory and the non-volatile memory and being programmed to detect a power loss of the primary power source And responsive to moving the data from the volatile memory to the non-volatile memory based on the at least one start address and the at least one end address. In some aspects, there is only one at least one start address and only one at least one end address exists, and moving data from the volatile memory to the non-volatile memory includes moving only at a start address and The data in the volatile memory at the address between the end addresses.

In another aspect, a method includes: detecting a power failure of one of a primary power source of a volatile memory, the volatile memory comprising a plurality of memory segments, the plurality of memory segments being at least a start address and a corresponding at least one end address definition; and in response to detecting the power failure and when the volatile memory is powered by a standby power source: based on at least one start address and at least one end bit The address moves the data stored in the volatile memory to a non-volatile memory. In some aspects, there is only one at least one start address and only one at least one end address exists, and moving data from the volatile memory to the non-volatile memory includes moving only at a start address and The data in the volatile memory at the address between the end addresses.

In another aspect, a device includes: a non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to be a primary power source of a volatile memory Moving a data from the volatile memory to the non-volatile memory after a power loss occurs; and a backup power source providing temporary power to the controller and the volatility after the power loss of the primary power source occurs Memory, the backup power source includes: one a capacitor bank having an output terminal; a voltage source connected to the voltage source to charge the capacitor bank to a normal operating voltage; and a health state monitor programmed to be based on the output terminal of the capacitor bank A voltage produces a fault signal.

In another aspect, a method includes interrupting charging of a capacitor bank by a voltage source configured to provide temporary power to a controller, the controller being programmed to be in a volatile memory One of the main power sources generates power loss from the volatile memory to a non-volatile memory, and provides power to a volatile memory after the power loss occurs in a main power source; When charging is interrupted, applying a predetermined resistance to an output terminal of all of the capacitor banks for a predetermined period of time; monitoring the output terminal of the capacitor bank during the predetermined period to determine whether the voltage at the output terminal falls to a predetermined period Below the voltage limit; and if the voltage at the output terminal falls below the predetermined threshold voltage within the predetermined time period, a fault signal is generated.

In another aspect, a device includes volatile memory; one or more non-volatile memory wafers, each of which is used to store data moved from the volatile memory; an interface for Connected to an alternate power source configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; a controller associated with the volatile memory and non-volatile Memory communication, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory wafer after a power loss of the primary power source of the volatile memory occurs; and the description will be The parameters of the volatile memory are stored in at least one of the non-volatile memory chips The non-volatile memory chips are stored from the volatile memory. In some aspects, the parameters include sequence presence detection information.

In another aspect, a method includes describing a volatile memory based storage after a power loss of one of the primary power sources of the volatile memory occurs, that is, when the volatile memory is temporarily powered by an alternate power source. In a parameter of at least one of the non-volatile memory chips, the non-volatile memory chips store data transferred from the volatile memory to move the data from the volatile memory to the non-volatile memory chip. Each of the non-volatile memory chips is used to store data transferred from the volatile memory. In some aspects, the parameters include sequence presence detection information.

In some aspects, a memory device includes: a volatile memory; an interface for connecting to a backup power source configured to supply power after a power loss of one of the primary power sources occurs To the volatile memory; non-volatile memory; a first configuration data bus for accessing parameters describing the substantially permanent characteristics of the volatile memory; a second configuration data bus, The at least one of the health status information of the standby power source and the status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus bar protocol; a controller, which is in communication with the first configuration data bus, the second configuration data bus, the volatile memory, and the non-volatile memory, the controller is programmed to detect the main power source a power loss and in response to moving the data from the volatile memory to the non-volatile memory, wherein the first configuration information of the controller is at least readable and writable by the first configuration data bus Persons; and wherein the state of health information and the status information via at least one of At least one of the second configuration data bus readable and writable information.

In another aspect, a memory device for use with a primary power source and a backup power source includes: a volatile memory; an interface for connecting to an alternate power source, the alternate power source configured Temporarily supplying power to the volatile memory after power loss from one of the primary power sources occurs; each of the plurality of turns is for receiving a different corresponding non-volatile memory chip; a plurality of interfaces, Each of them is for communicating with any non-volatile memory connected to one another via a respective one of the plurality of turns; a controller programmed to receive non-volatile according to which ones A memory chip to initiate an optional set of the plurality of interfaces, wherein the controller is also programmed to move data from the volatile memory to any of the selectable sets connected to the interface by the selected interface Non-volatile memory reacts to power loss from one of the primary power sources.

In another aspect, a method includes detecting a power failure of one of a primary power source of a volatile memory; and in response to detecting the power failure and when powering the volatile memory with a backup power source: Moving the data stored in the volatile memory to a non-volatile memory, the non-volatile memory comprising an optional number of non-volatile memory wafers, wherein the movement is based on the optional number of non-volatiles Memory chip.

In another aspect, a memory device for use with a host processor and a main power source includes: non-volatile memory; volatile memory; an interface for connecting to a backup power source, The alternate power source is configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; isolation logic for controlling the host processor to An access to the volatile memory, the isolation logic having a first mode and a second mode, the isolation logic providing the host processor with the volatile memory for storing or reading data during the first mode Access, and the isolation logic isolates the volatile memory from access by the host processor during the second mode; and a controller that controls the isolation logic, the controller being programmed to The isolation logic is placed in the first mode when the volatile memory is being powered by the primary power source, and the isolation logic is placed when the power from the primary power source to the volatile memory is interrupted In the second mode, data is transferred from the volatile memory to the non-volatile memory.

In another aspect, a method includes: detecting a power failure of one of a primary power source of a volatile memory; and responding to detecting the power failure and when the volatile memory is powered by a backup power source Changing a mode of the isolation logic from a first mode to a second mode, the first mode providing a host processor for storing or reading while the volatile memory is being powered by the primary power source Accessing the volatile memory of the data, the second mode isolating the volatile memory from access by the host processor; and moving the data stored in the volatile memory to a non-volatile memory body.

100‧‧‧Dual-line memory module (DIMM)

105‧‧‧ interface

110‧‧‧ Controller

115‧‧‧FPGA programmable read-only memory

120‧‧‧ volatile memory

121‧‧‧DRAM chip

122‧‧‧DRAM chip

130‧‧‧Non-volatile memory

131‧‧‧Flash Chip/Flash Device

132‧‧‧flash device

140‧‧‧Isolation Logic

150‧‧‧ Signal

161‧‧‧PLL

162‧‧‧ 存存器

163‧‧‧FET bus switch / FET multiplexer

164‧‧‧FET Switch/FET Multiplexer

170‧‧‧Interface line/signal

171‧‧‧VBACK

200‧‧‧Reserved power supply/standby power source/backup power module

210‧‧‧EDL capacitor

220‧‧‧ Standby controller/charger and monitor

300‧‧‧Replacement power module

310‧‧‧Backup battery

D1‧‧‧ diode

Q1‧‧‧Optoelectronics

Q3‧‧‧Optocrystal

Q4‧‧‧Optocrystal

U1‧‧‧Power Regulator

U11‧‧‧Health Status Monitor

U2‧‧‧Power Regulator

U3‧‧‧Power conditioner

U4‧‧‧Power Regulator

U6‧‧‧Charger

Figure 1 is a block diagram of a two-line memory module (DIMM).

Figure 2 is a block diagram of a capacitor-based backup power supply that can be used to power the components of Figure 1 in the event of a power failure.

Figure 3 is a block diagram of a battery-based backup power supply that can be used to power the components of Figure 1 in the event of a power failure.

Figure 4 is a diagram showing an example state of the DIMM illustrated in Figure 1. And the converted block diagram.

Fig. 5 is a timing chart showing various read operations of the internal integrated circuit (I2C) interface of the DIMM illustrated in Fig. 1.

Fig. 6 is a timing chart showing various write operations of the internal integrated circuit (I2C) interface of the DIMM illustrated in Fig. 1.

Figure 7 shows the architecture of the DIMM illustrated in Figure 1.

Figure 8 shows the architecture for powering the DIMMs illustrated in Figure 1 .

Figure 9 is a more detailed illustration of the backup power supply of Figure 2.

Referring to FIG. 1, the depicted embodiment of the present invention is a dual row memory module (DIMM) 100 that includes volatile memory 120, non-volatile memory 130, isolation logic 140, and controller 110. DIMM 100 is coupled to a primary power source (not shown) to support normal operation and is also coupled to alternate power source 200 (see Figure 2). When the DIMM 100 is operating at the power supplied by the primary power source, an external system (eg, a RAID system) stores the data in the volatile memory 120 via the interface 105 and reads the data from the volatile memory 120. However, when power from the primary power source 200 is interrupted, the alternate power source supplies sufficient temporary power to the DIMM 100 so that the controller 110 can cause the isolation logic 140 to isolate the volatile memory 120 from the external system, and then from the standby The data is transferred from the volatile memory 120 to the non-volatile memory 130 before the power of the power source 200 is exhausted. When the primary power source becomes available again, the controller 110 transmits the data stored in the non-volatile memory 130 back to the volatile memory 120, and causes the isolation logic 140 to wave The hair memory 120 is then connected to the external system.

Volatile memory 120 is a DRAM array that includes various DRAM wafers, such as DRAM wafer 121 and DRAM wafer 122. The non-volatile memory 130 includes various flash memory devices, such as a flash device 131 and a flash device 132. Due to the limitation of the DIMM 100, all of the data stored in the volatile memory 120 cannot be moved to the non-volatile memory 130 at one time. One of these limitations is that it cannot be written to the flash device of the non-volatile memory 130 as quickly as it is read from the DRAM device of the volatile memory 120. In view of this difference, each time a DRAM wafer moves data from the volatile memory 120 to the non-volatile memory 130. In addition, during the transfer of data from the volatile memory 120 to the non-volatile memory 130, the DRAM chip that is not actively being transferred enters a low power state, and the low power state maintains the data stored therein, but is operated normally. The state consumes less power. In a DRAM chip of volatile memory 120, this low power state is a self-renew mode. By having the DRAM die that is not actively transmitting enter a low power state, the module 100 requires less power during standby operation than would otherwise be the case. For example, this allows for the use of a smaller and cheaper alternative power source.

Figure 2 shows a block diagram of this power source. In particular, Figure 2 shows an electrochemical double layer (EDL) capacitor backup power module 200 that interacts with DIMM 100 using interface wires (eg, power, I/O, etc.) 170 (EDL capacitors are also known as supercapacitors) And ultra high capacitors). Capacitor 210 supplies backup power to DIMM 100 when the power to the main power source of DIMM 100 fails. Charger and monitor 220 charges capacitor 210 and performs capacitor 210 The health status is monitored to alert the DIMM 100, for example, if the capacitor 210 fails and the backup power is no longer available. In some cases, a battery can be selected to replace the capacitor. For example, FIG. 3 shows a block diagram of a battery backup power module 300 that can be used in place of the module 200.

The non-volatile memory 130 embeds sequence presence detection (SPD) information for the volatile memory 120 (eg, information describing the size and speed of the DRAM chips in the volatile memory 120). By using the non-volatile memory 130 to store the SPD information of the volatile memory 120, the volatile memory 120 avoids the need to have a separate EEPROM module for storing this information. Avoiding the addition of a separate EEPROM can save cost, reduce the size of the module 100, and reduce the number of components required.

DIMM 100 includes two I2C busses between an external system and controller 110. I2C busbars are commonly used to attach low speed peripheral devices to various devices when, for example, simplicity and low manufacturing cost are more important than speed. The first I2C bus is used for access sequence presence detection (SPD) EEPROM ("SPD I2C Bus"). It is defined by the standard JEDEC specification. The second I2C bus is used to access information of other modules 100, such as status information and health status (SoH) information for the controller 110, the non-volatile memory 130, and the backup power source 200 ("NVDIMM I2C bus" "). The status information may include, for example, the current state of the flash memory (write, erased, erased, corrupted, etc.); the number of bad blocks that were replaced; the number of remaining spare blocks; completed The total number of download cycles; the number of ECC errors in the last download; the number of ECC errors in the last restore; the status of the last download (in progress, no error completion, error completion, etc.); In the line, no error completion, error completion, etc.); flash header information. The SoH information may include, for example, the current state of the alternate power source (charged, discharged, positively charged, etc.), whether any capacitors that make up the alternate power source have failed (and if failed, determine which capacitors have failed) and standby The type of power source (for example, a capacitor or battery).

Block diagram detail

Flash memory 130 provides non-volatile storage on DIMMs and is implemented using Secure Digital (SD)/Multimedia Card + (MMC+). The controller 110 can support various configurations, for example, four independent SD/MMC+ interfaces are connected to four SD mass storage devices, and each SD mass storage device uses a 4-bit data bus with 20 million bytes/second. The bandwidth operation, or interface is connected to four MMC+ mass storage devices, each MMC+ mass storage device uses an 8-bit data bus and operates with a bandwidth of 40 million bytes per second. One advantage of using SD/MMC technology is that the complexity of managing flash memory is hidden from controller 110 by using a simple, low pin count interface. The flash memory can be implemented as a single device (eg, SanDisk iNAND) or can be constructed on the same DIMM using a discrete SD controller with a separate NAND memory device. In either case, the SD/MMC controller is responsible for ECC and bad block management depending on the NAND technology used.

The sequence presence detection (SPD) data is stored in a flash memory of the first 256 bytes, the flash memory being attached to the first SD/MMC+ interface (ie, the flash wafer 131). A typical write protection mechanism is implemented using flags stored within the flash configuration space. The controller 110 implements a read cache and write mechanism for the SPD data, wherein the SPD information can be stored in the controller 110. The cache is in the memory (except on the flash chip 131). During system power on, controller 110 extracts SPD data from flash memory. The read operation on the SPD I2C interface uses the cache data while writing the write operation to the flash memory immediately. The SPD I2C interface will ignore any read or write requests during write operations to this flash memory.

The status information is stored in the flash memory of the second 256th byte, and the flash memory is attached to the first SD/MMC+ interface. This interface allows the user to monitor and configure the operation of non-volatile functions. This area is also used to track system status during the last power cycle. The controller 110 implements a read cache and write cache mechanism for configuring data, wherein the status information can be stored in the cache memory on the controller 110 (except on the flash chip 131). During the power-on of the system, the FPGA extracts data from the flash memory. The read and write operations on the NVDIMM I2C interface use cache data. The cached data is written back during the power outage and power loss (standby) events.

The controller 110 is an advanced embedded processor having a custom 133 MHz DDR controller, four custom SD/MMC+ host interfaces, an SPD I2C interface, and an NVDIMM I2C interface. The microprocessor can be, for example, a soft 32-bit Altera NIOS RISC processor that can execute firmware from an internal memory instance in an FPGA (Programmable Read Only Memory (PROM) 115). The processor controls the operation state of the data movement of the module 100 between the DDR interface and the SD/MMC+ interface, and controls communication between the SPD interface and the NVDIMM I2C interface. The custom DDR interface allows the controller 110 to operate the DRAM array on a per-tuple channel basis. The interface has individual control of the CKE signal, allowing control of each device in the DRAM array. Controller in array The first 8 bytes in each tuple channel are used in the column to set the internal phase alignment of the bus. Four custom SD/MMC+ interfaces are designed for embedded applications that do not require features such as hot swap. The interface supports 1-bit, 4-bit, and 8-bit operations at clock rates up to 50MHz. These interfaces can also be operated simultaneously to synchronize four SD/MMC+ cards, allowing high frequency wide read and write operations without the need for extensive data buffering. For applications that need to remove the SD/MMC+ card, the FPGA host interface allows the cards to be reordered without the cards being installed in the correct order.

Volatile memory 120 is a DRAM array. Various example configurations are shown in the table below, which include an 8-bit Error Correcting Code (ECC) for the actual data per 64 bits. In an example of an NVDIMM with two billion bytes, one row can be turned on or off based on current memory requirements. It can be turned off to save power when a row is not needed. When the data (actual data and ECC) is moved from the volatile memory 120 to the non-volatile memory 130, the non-volatile memory 130 stores the actual data and the ECC, and the actual data stored in the non-volatile memory 130. There is no difference from ECC. When the data is moved back from the non-volatile memory 130 to the volatile memory 120, the controller 110 restores the actual data and ECC suitable for the particular DRAM device being used back to the volatile memory 120.

PLL 161 is a high performance, low time skew, PLL based, zero delay buffer that spreads a differential input clock signal to the DRAM array. The DDR clock from the edge connector is multiplexed with the DDR2 clock from controller 110 to prevent PLL 161 from entering its low power state and preventing PLL 161 from tri-state its output. In this example design, the selected PLL must operate at the desired system rate and the slower DDR controller rate. In general, the PLL skips itself and operates as a small delay buffer at the slowest clock rate.

The control and address signals are re-driven via the register 162 to the DRAM device on the rising clock edge (data access is delayed by one clock). Controller 110 uses three states to access the address and control signals. When the controller 110 controls the DRAM 120, the FET bus switch 163 can be used to isolate the register from the edge connector and the controller 110 can directly drive the register input. When the system controls the DRAM array, the FET bus switch 163 is turned "on" and the FPGA tri-states its output. The CKE signal is processed differently from other control signals. Switching between the two modes of operation has less glitchless to ensure that DRAM 120 is still in self-renew mode. For these signals, FET switch 163 is used to multiplex between the edge connector (to the system) and controller 110.

The high frequency wide FET multiplexer 163 and the FET multiplexer 164 are designed to support high frequency wide applications such as memory interleaving, bus isolation, and low distortion signal gating. FET multiplexer 163 and FET multiplexer 164 isolate module 100 from the system bus during a power loss event. FET multiplexer uses charging The pump increases the gate voltage of the transfer transistor and provides a low, flat on-state resistance. This low, flat on-state resistance allows for minimum propagation delay and supports rail-to-rail switching on data input/output (I/O). FET multiplexers are also characterized by low data I/O capacitors to minimize capacitive loading and signal distortion on the data bus.

Depending on the configuration of the module 100, not all of the data stored in the volatile memory 120 is reserved to the non-volatile memory 130. Alternatively, module 100 can be configured to reserve (and later restore) data stored in selected portions of volatile memory 120. The information stored in non-volatile memory is typically key/directory information used to determine the location of information (eg, files) in the file system. The key/directory information is an extremely important piece of information that will be selected by all users. However, other types of information may also be stored in the volatile memory 120. For example, software program information (eg, ".exe" files) that are not changed may be stored in the volatile memory 120. Controller 110 includes a register that allows a user to segment volatile memory 120. The start address is stored in a register and the end address is stored in a second register. All data stored between these two addresses will be backed up and restored. Data stored outside of these addresses will not be backed up/restored. The values of these registers are controlled via the NVDIMM I2C bus. The user can choose, for example, to specify a start address and an end address so that only critical/directory information can be backed up/restored. One reason for choosing to restore only critical/directory information is to improve recovery time by not wasting time recovering information that does not require recovery from non-volatile memory 130 (eg ".exe" is likely to have not changed and can be used when needed Loaded from the host system). Module 100 can be configured to support a variety of flash chips (e.g., 1-4) and can be programmed with firmware based on a selected number. The number of flash chips used may be based, for example, on the size of the volatile memory that needs to be spared and the time that the backup must occur (eg, the amount of time the backup power is available) or based on reaching a desired recovery rate ( That is, more flash devices allow for a faster recovery time). For example, for a controller that can support up to four flash chips, the controller will have four bus bars. Each of the bus bars can be connected to (or not connected to) the flash wafer according to a selected number of flash wafers. The selected number of flash wafers (eg, 1, 2, or 4) are connected to the bus bar and soldered to a printed circuit board (PCB). For a module 100 designed to accommodate up to four flash chips, if only two flash chips are installed, the remaining space for the two flash chips that are not installed remains empty and the controller 110 is programmed To attempt to communicate with only the two installed flash chips. For a constant standby time or recovery time, the number of flash wafers may increase in proportion to the size of the volatile memory. Alternatively, the standby time and recovery time can be reduced by increasing the number of flash chips.

Signal description

The module 100 implements a 72-bit DDR2 memory interface with a 244-pin mini DIMM connector. The connector signal designation is defined in the JEDEC Standard 21C, page 4.20.14-2 of the DDR2 registered small DIMM design specification (currently available at www.jdec.org). Each of these signals may be part of signal 150 or signal 170. Signals corresponding to each of the 244 pins are not shown in Figure 1 to avoid making Figure 1 difficult to read.

The NVDIMM_RESET signal initializes the controller 110 and forces the controller to restart its state machine. When the standard RESET_IN input is determined, the controller 110 is also reset (along with, for example, the volatile memory 120 and the register 162). When the controller 110 is held in reset by NVDIMM_RESET, the module 100 will operate normally. That is, when NVDIMM_RESET is asserted, FET switch 163 remains on, allowing the system to access DRAM memory 120 without further interaction.

The NVDIMM_PG signal reports the power status in the user's system. When the signal is high, the system power rail operates within specifications. When the signal goes to a low level, the power loss approaches and the controller 110 moves the data to the flash memory 130. If the DRAM device data is moved to the flash memory (as indicated by the NVCACHE_ENABLE signal), the system causes all DRAM devices (eg, 121-122) to enter self-renew operation before negating NVDIMM_PG. If NVCACHE_ENABLE is low when NVDIMM_PG is negative, the data in the DRAM device is ignored during the power loss event.

The NVCACHE_ENABLE signal reports the presence of cached data that should be moved to the flash memory in the DRAM device in the event of a system power failure. If NVCACHE_ENABLE is high when NVDIMM_PG is negative, controller 110 moves the data in the DRAM device to the flash memory. If NVCACHE_ENABLE is low when NVDIMM_PG is negative, the DRAM contents are ignored and are not stored in the flash memory 130. The last order is used by the system to shut down normally (for example, in response to a user request to shut down without a power failure). When NVDIMM_PG is low, NVCACHE_ENABLE can be ignored by controller 110 to prevent false signals. Sexual transitions affect any alternate event.

During a restore operation, NVCACHE_ENABLE is used by the system to signal controller 110 to erase flash memory 130. The dirty tag within the flash memory is not cleared until the signal exchange with NVCACHE_ENABLE is completed. This allows, for example, the system to handle another power loss event during the restore operation.

After moving the data from the flash memory 130 to the DRAM 120, a DRAM_AVAILABLE signal indicating that the system can access the data is determined. When the system decides that flash memory 130 should be cleared (eg, to prevent data from being restored again after a power loss event), the system negates (falls edge) NVCACHE_ENABLE to reset the flash memory. The system waits for NVDIMM_READY to be determined before determining NVCACHE_ENABLE again. The system can continue to use module 100 until NVDIMM_READY is determined, but no data will be available during the power loss event.

The CACHE_DIRTY signal indicates that the flash memory 130 contains Data image of DRAM 120. During the "standby" state, the CACHE_DIRTY signal indicates the beginning of the alternate process. During the "power on" state, CACHE_DIRTY indicates that flash memory 130 contains a backup video file. The signal remains high until the NVCACHE_ENABLE signal is negated (falling edge), indicating that the cached data has been read from DRAM 120.

The DRAM_AVAILABLE signal indicates when the system can access the DRAM 120. Controller 110 has control of DRAM 120 when DRAM_AVAILABLE is low. When the signal is high, the system can cause the DRAM device (e.g., 121-122) to exit self-renew and access the data. in In the case of powering up flash memory 130 with data, DRAM_AVAILABLE will remain negative until the flash data is moved to DRAM 120. Once the signal is determined, the system can read and write to DRAM 120, but NVCACHE_ENABLE cannot be determined until module 100 is ready. A delay may occur between the determination of DRAM_AVAILABLE and NVCACHE_ENABLE, for example, after the restore operation, because the volatile memory 130 is being erased or the alternate power source is being recharged. The system may choose to read only from the volatile memory 120 during this time (as opposed to reading from and writing to the volatile memory 120 from the volatile memory 120).

The NVDIMM_READY signal indicates that the module 100 is capable of handling power loss events. This signal is undefined until the external power source is healthy and fully charged. When configured to completely erase flash memory 130, the NVDIMM_READY signal is also not determined until flash memory 130 is fully initialized to a known state. This feature allows the design to support flash memory devices that do not support full-speed burst write operations without erasing the flash memory. During normal system operation (idle state), the system cannot determine NVCACHE_ENABLE until NVDIMM_READY is determined. NVDIMM_READY is negated during the standby operation. NDIMM_READY is negated during the restore operation. If the controller 110 determines at any time that the power loss event cannot be properly processed, for example, if the EDL capacitor bank fails to perform a self-test operation, the controller 110 negates NVDIMM_READY to inform the system to move any cached data from the DIMM memory (eg, Move the data to a permanent storage such as the hard drive of the system).

NVDIMM_SEATED is a pull-up pin on the DIMM pin that allows the system to detect module 100. The system can also detect module 100 by attempting to read from the NVDIMM I2C interface to see if the I2C slave interface is responding.

The NVDIMM I2C slave interface on controller 110 provides a full functional user interface to controller 110. The user can configure and control the controller 110 and access detailed status information using NVDIMM_SDA and NVDIMM_SCL (signal 152).

V3P3_AUX is an auxiliary 3.3V rail that supplies power to non-volatile logic during normal system operation. During the power loss state, the module 100 switches from this supply and operates from VBACK 171 (the voltage rail used by the power supply during standby operation) until the controller 110 turns itself off.

The module 100 also includes a third I2C interface between the controller 110 and the backup power source 200 ("backup power I2C interface"). The backup power I2C interface allows the controller 110 to communicate with the external standby power module using VBACK_SDA and VABACK_SCL. Via the interface, the controller 110 can determine the type of alternate power method (eg, an EDL capacitor or battery) and determine the state of charge and health of the power source. Information communicated in the backup power I2C interface can be communicated as part of the SoH information in the NVDIMM I2C interface. The standby power reset (VBACK_RESET) allows the controller 110 to reset the external standby power module. The VCHRG voltage rail supplies power to the EDL capacitor charging or external battery backup power module. The voltage rail is a nominal 12 volt rail that can achieve 500 mA.

The signal TEST_RX and the signal TEST_TX are composed of one 57.6Kbaud serial link production test interface. These test signals are tri-stated and floating during normal system operation.

State and state transition

FIG. 4 illustrates a state diagram showing various states and state transitions of the module 100. For example, regardless of the state in which the module is operating, the module 100 is initialized to a "power on" state by system reset. In this case, the module initializes all logic and extracts the configuration from the flash memory before determining what happened to the last power cycle. For example, the module loads firmware from FPGA PROM 115; CACHE_DIRTY is determined, and NVDIMM_READY and DRAM_AVAILABLE are negated. The SD/MMC+ flash memory is initialized to the SD/MMC+ transfer state. The flash configuration block is read to determine the state of the last power cycle. If the "Used" tab is set and the previous standby operation is successfully completed, the status is transitioned to the "Erase" state (if configured to erase the execution time area). If not configured to erase the execution time zone, the state is transitioned to the "reset" state. If the "Used" tab is set and the backup operation has not been successfully completed, move the status to the "Erase" status (if the "Erase" bit is set) or move to the "Inactive" setting of DRAM_AVAILABLE and CACHE_DIRTY. status. If the previous "erase" state is not completely completed and the "erase" bit is set, it is switched to the "erase" state to re-execute the erase cycle. If the "used_tag" is not set, CACHE_DIRTY is negated, DRAM_AVAILABLE is determined, and the state transitions to the "idle" state.

When the system power is applied, the "idle" state is the normal operating state. If CACHE_DIRTY has been set and then NVCACHE_ENABLE is available OK, CACHE_DIRTY is denied. CACHE_DIRTY can be used to acknowledge a response to an unsuccessful restore operation due to an invalid backup. If NVCACHE_ENABLE is determined and NVDIMM_READY is determined, then it is determined that CACHE_DIRTY will confirm that the controller is now operating in a non-volatile state (power loss will trigger an alternate operation). If NVCACHE_ENABLE is negative, CACHE_DIRTY is denied to confirm that the controller is now operating in a volatile state (power loss will not be performed alternately). If the alternate power source is within the voltage specification, then it is determined that the NVDIMM_READY indicates that the system can support a power failure. If the alternate power source fails to self-test (or controller 110 cannot complete the standby operation for any other reason), then negating NVDIMM_READY will signal the system to clear the cache memory. If CACHE_DIRTY is determined and NVDIMM_PG is negative, power is lost and the DRAM memory contains data to be written to the flash memory. In this case, the controller 110 negates DRAM_AVAILABLE and NVDIMM_READY and transitions to the "standby" state. If CACHE_DIRTY is negated and NVDIMM_PG is negated, the DRAM memory does not contain valid data and the power is normally turned off. In this case, DRAM_AVAILABLE and NVDIMM_READY (if set) are negated and transitioned to the "power off" state.

The "standby" state is responsible for moving data from DRAM 120 to flash memory 130 when operating at standby power. If the "short pulse waveform interference" bit is not set, the controller 110 waits for the CKE to be low to ensure that the DRAM memory is self-renewed (if the standby operation starts, the "short pulse waveform interference" bit Set, but the power rises during operation). machine The load regulator switches from standby power to power supply. The DDR bus is disconnected and the controller 110 drives the DRAM 120. Because the system may be powered down, the controller 110 masks the NVCACHE_ENABLE signal. Controller 110 determines the "used" register and writes to the flash configuration page to record the beginning of the alternate process. If there is a checkpoint due to a transition from the "short pulse waveform interference" state, the controller 110 restarts the standby from the checkpoint. Additionally, for each DRAM device of DRAM 120, the DRAM device is caused to exit self-renew and write to the contents of flash memory 130. If the NDIMM_PG is determined during the memory copy operation, the active DRAM device is returned to self-renew, the current spare point is checked, and the "short pulse waveform interference" state is moved. When all of the DRAM devices have been copied to flash and the flash has completed its program loop, controller 110 writes the current state information in the flash configuration and waits for the program loop to complete. Finally, the controller 110 moves the module 100 to the "power off" state.

If the system power is still available, the "power down" state handles the power down operation to prevent the memory module 100 from restarting in advance. That is, the NVDIMM_PG may indicate a power loss event, but the system power may not have been removed from the memory module. If operating at standby power, controller 110 switches the onboard regulator back to normal power. The controller 110 tristates the interface between the controller and the multiplexer 163 and connects the DRAM device to the DDR bus. If the NVDIMM_PG is determined, the system power still exists, so the system restarts by moving to the "power on" state.

The glitch state indicates the condition in which the system temporarily loses power, but the power has returned before the standby operation is completed, allowing the user to retrieve DRAM content without using flash data. "short-time pulse waveform interference" The status can be entered multiple times during the standby operation. There are two results in the "short pulse waveform interference" state. The power loss event continues and the data within DRAM 120 is backed up to flash 130 or the data within DRAM 120 is captured and NVCACHE_ENABLE is negated. If the power loss is temporary, the memory module must still recharge the EDL capacitor to a known state prior to determining NVDIMM_READY and allow the system to be non-volatile. To this end, the module 100 records the event by determining the "short-time waveform interference" register to indicate the power restored before the standby power loss; switching the on-board regulator from the normal system power to the power supply; The device 110 is tri-stated and reconnects the DDR bus to the DRAM memory; determines the DRAM_AVAILABLE indicating that the data is available; masks the NVCACHE_ENABLE signal because the system can clear the data of the DRAM device; if the NVDIMM_PG is determined and the NVCACHE_ENABLE is negated, then No need to copy in flash memory, negate CACHE_DIRTY and switch to "erase" state; if NVCACHE_ENABLE is determined and NVDIMM_PG is negative, power is lost and DRAM memory contains data to be written to flash memory , negating DRAM_AVAILABLE and transitioning to the "standby" state to restart from the checkpoint.

The erase state is used to apply portions of the DRAM 120 for time-critical, non-volatile applications (eg, if the user has decided to store non-critical/directory information in the volatile memory 120 and has not selected to spare /Restore the non-critical/directory information). In the erased state, controller 110 can be configured to zero a single contiguous region in the address space. This feature prevents False ECC errors within DRAM memory. The module 100: disconnects the DDR bus and causes the controller 110 to drive the DRAM memory; if the erase function is interrupted by the NVDIMM_PG negating the indicated power loss, the mode is switched to the "power off" state; for each DRAM, The configured address space is initialized to zero and the associated ECC value is initialized; when all DRAMs are completed, transition to the "reset" state.

The "reset" state passes the contents of the flash memory 130 back to the DRAM 120. This state is not exited until the system indicates that the recovered data in the DRAM has been read to process the power loss event during this state. A power loss event during the "recovery" state causes the same image to be restored to the DRAM memory on the next power-on event. Module 100: if not already done, disconnect the DDR bus and cause the controller 110 to drive the DRAM memory; recording the recovery operation in the flash configuration memory has begun to allow the system to detect multiple recovery events; DRAM, copying content from the flash memory to DRAM; when all DRAMs are completed, updating the "mode" byte with the value stored in the flash configuration (system with "mode" value only read-only "mode" value) and causing the DRAM to enter self-renew operation; if the recovery function is interrupted by the NVDIMM_PG negating the indicated power loss, then transitioning to the "power down" state; the controller 110 is tri-stated and will The DDR bus is reconnected to the DRAM 120; the DRAM_AVAILABLE is determined; and when the NVCACHE_ENABLE transitions from the high level to the low level (falling edge), the transition to the "erase" state is performed to erase the flash content.

Some flash memory devices require the erase of memory to achieve maximum bandwidth performance during large sequential write operations. In these embodiments, the system is Less clear any flag indicating that a portion of the copy or image is present in the flash memory. The erase operation cannot occur until the system has indicated that any data (i.e., recovered data or partial spare data) in the DRAM 120 has been read from the DRAM 120. The module 100 enters the "erase" state and: if the erase cycle is interrupted by another power loss, the erase cycle is first restarted; the controller 110 is tri-stated and the DDR bus is reconnected to the DRAM 120; Determining DRAM_AVAILABLE; if necessary, writing to the flash configuration to clear any flags indicating potential spare or backup image files within the flash memory and marking an erase cycle has begun; if "erase" is temporarily stored If the device is determined, the flash memory module is erased; if the erase function is interrupted by the NVDIMM_PG negating the indicated power loss, the mode is switched to the "power off" state; when the erase cycle is normally completed, the update is updated. Flash configuration; when the erase operation is completed, transition to the "idle" state.

I2C interface

The FPGA controller has two separate slave I2C interfaces that are controlled using the same protocol, such as the industry standard two-wire I2C serial EEPROM (ie, the SPD I2C interface and the NVDIMM I2C interface). The base address for the SPD I2C interface is set to standard 0xA0, and the base address for the NVDIMM I2C interface is set to 0xB0. A 1-bit address offset is applied to the two base addresses to allow the two interfaces to be joined together and interoperate with other modules as needed. That is, the SPD I2C interface and the NVDIMM I2C interface can be implemented as a single physical interface using different address ranges. The controller 110 uses the first 512 byte blocks in the flash memory that is attached to the first SD/MMC+ interface. The first half of the block is for SPD The data, and the second half of the block is used for flash configuration. Figure 5 shows the functional operation using the I2C interface read. Figure 6 shows the functional operation using the I2C interface write.

Debug, maintenance, testing and scanning

Module 100 also includes functionality for debugging, maintenance, testing, and scanning. For example, if the controller is implemented using an Altera processor, the Altera JTAG UART interface is a full-featured debug and monitoring interface that allows the user to access the firmware functionality. With the Altera tool suite, firmware can be monitored and/or overwritten with new firmware for research purposes. Using the built-in UART function, the JTAG interface can be used to simulate a serial interface that allows low-speed custom communication. Similarly, for larger FPGA configurations, the firmware can be incorporated into the test user interface to perform diagnostic tests on DRAM and flash memory for testing purposes. The test user interface is also accessed via the UART built into the Altera JTAG interface.

Controller 110 may be reset to allow testing of DRAM 120 and SD/MMC+ flash 130 during production testing. Therefore, when the controller 110 is held in reset, the FET switch 163 and the FET switch 164 on the DDR interface are maintained in an appropriate state. At the same time, controller 110 tristates the SD/MMC+ interface to allow for needle bed testing of flash memory.

The controller 110 has a production test control that controls the configuration firmware to perform production testing on the DDR interface and the SD/MMC+ interface to ensure proper connectivity. The controller 110 reads and writes to the DDR memory device to utilize the address, data, and control signals of the DDR. Similarly, the controller 110 transmits sufficient data to use all the messages via the SD/MMC+ command and data bus. number. As a terminal customer production test, the NVDIMM I2C interface provides a mechanism to control standby and restore operations and direct access to flash and DDR memory.

FPGA architecture

Figure 7 shows an example architecture of controller 110 that uses an embedded NIOS processor with an Avalon bus to connect IP blocks together (e.g., if the controller uses Altera processors (Altera) JTAG) to implement). Changes to Altera's design include another I2C interface for the new feature structure (NVDIMM I2C interface), updated GPIO, and modified firmware.

Power description

The power supply of module 100 performs many system operations. It produces the voltage rails required by controller 110 and isolates module 110 from the system rails during a power failure. Figure 8 shows the structure of the power supply.

During normal operation, transistor Q3 and diode D1 direct system power VDD and V3P3_AUX to the device on module 100. V3P3_AUX is an additional edge connector pin that powers a non-standard device on module 100. VDD is a standard modular power source that includes many edge connector pins. The VMEM is a power rail that supplies power to the module 100 device. The V3P3_AUX voltage rail is converted to the three additional power rails required by the controller 110. In general, the V1P2 voltage rail and the V1P8 voltage rail supply most of the controller power, while the V2P5 rail powers the FPGA analog PLL and the V3P3 powers the FPGA digital I/O, oscillator, and SD/MMC+ card.

The controller 110 is notified of an approaching power loss via the edge connector signal or via the NVDIMM I2C interface. Once it happens, the controller 110 is connected Passing Q1 and Q4 and disconnecting transistor Q3 to obtain power from the EDL capacitor bank, the EDL capacitor bank is coupled to VBACK 171 and isolates the module from system power. This power switch has no contacts, such as, for example, in this condition power regulators U1, U2, U3, and U4 are configured to not cause controller 110 to reset or cause DRAM 120 to lose data. One way to switch between power supplies is to use a diode switch. Diode D1 prevents, for example, the EDL capacitor voltage from being fed back into the V3P3_AUX supply due to charge sharing between the "decoupled" capacitors on the two tracks. If a transistor is used, the EDL capacitor voltage can cause The power supply has a glitch (one of the capacitors is an EDL capacitor bank). Depending on the type of power loss event, controller 110 may be requested to stop using the EDL capacitor bank and be requested to return to system power. Again, this power switch has no contacts to prevent data loss or glitches on the power rail.

Module 100 also charges with the VCHRG power supply and monitors the EDL capacitor bank. This voltage rail is designated for charging purposes only, and the module continues to operate normally even when VCHRG is not connected. In order to improve the power efficiency of the EDL capacitor bank, the minimum input voltage of U3 and U4 can be as low as possible. Since the alternate operation must be completed before U3 or U4 reaches its specification limit, this minimum input specification limits the low end of the EDL capacitor discharge curve. For this reason, the V3P3 regulator U1 is a boost regulator from the V1P8 supply, allowing the minimum EDL discharge level to be as low as possible.

When the cascade regulator affects the efficiency of the power supply, V3P3 and V2P5 are relatively lower power than the V1P8 power supply. Due to the lower minimum discharge level, the power loss of the cascaded V3P3 regulator U1 is significantly lower than the modified EDL Capacitor bank efficiency. A 1V reduction in the minimum EDL capacitor bank voltage results in a 10% improvement in total system power, while a cascaded V3P3 regulator U1 represents a roughly 30% reduction in the efficiency of the V3P3 power rail only (which is roughly 5 of the total system power). %-10%).

The system of Figure 1 supports four configurations of DRAM devices with different numbers of SD/MMC+ memory devices. Each configuration has a different PCB layout that allows the power supply design to be adjusted to support different loads. The power supply is designed to handle 70°C ambient (PCB) temperatures without forced airflow. The components for the power supply design are located on one side of the PCB and have a maximum height of 4 mm. The power supply uses only 3 吋 x 1 板 of board space, including any heat sink.

The VDD system rail is over-constrained such that the voltage drop at transistor Q3 does not cause the VMEM supply to exceed the downstream device range. The voltage drop budget for the Q3 transistor voltage drop has been chosen at any percentage of the nominal value, but better performance is needed.

The regulators shown in the figures are functional and can be combined into a multi-output regulator device. All voltage rails have monitors ("PG" signals) that can be combined with or combined into a single device. The V3P3 monitor is separate because the V3P3 monitor monitors the V3P3 rail when the V3P3_AUX rail is the power source. If VCHRG is not supplied, the V3P3 regulator does not operate, but this is not an error because the module 100 must still operate continuously (see Figures 2 and 3). In order to increase the energy storage efficiency of the EDL capacitor bank, the minimum allowable input voltage to the regulator should be as low as possible. The table below provides additional information about the regulator.

annotation:

1. The closest headroom of all regulators and limits the effectiveness of the EDL capacitor bank.

2. Low quiescent current requirement when the regulator is idle (capacitive load) during normal operation.

3. Based on the specifications of the configuration. See the section on voltage rails for specifications. Since power consumption is still an estimate, devices that are close to current specifications should be studied.

The power transistor is responsible for moving the DRAM device to the standby power and isolating the standby power from the system power VDD and V3P3_AUX. Capacitor charger U6 handles power loss and prevents the EDL capacitor bank from being discharged back via the charger. Transistor Q3 and transistor Q4 are n-channel MOSFETs and are controlled by an FPGA that uses 3.3V control signals to remove the need for high side drivers. Transistor Q1 is a p-channel MOSFET directly controlled by the FPGA or an n-channel MOSFET with a high-side drive mechanism (VCHRG power supply or VCAP power supply cannot be used normally unless the module continues to operate without such power supply) operating). The currents listed in the table below have a certain over-spec design tolerance, so a transistor that is close to meeting this specification can also be used in this example design. During a power loss event, the transistors operate only until the EDL capacitor bank is discharged (eg, a maximum of about 2 minutes).

annotation:

1. Based on VCAP (2.8v) low power supply specifications and 2% tolerance of the power supply voltage.

2. Based on the low power supply current specification of the power supply and the 2% tolerance of the power supply voltage.

EDL capacitor power supply

Returning to Figures 2 and 3, the EDL capacitor 210 or backup battery 310 connected to the VBACK 171 is external to the module 100 because it is physically large and temperature sensitive. The long-term lifetime of EDL capacitors and batteries is sensitive to ambient temperature and the operating voltage of the capacitor. For this design, the operating voltage has been chosen such that the capacitor will withstand ambient temperatures of less than 50 °C for at least 10 years. In general, the backup power is located near the air intake or near another relatively cool location within the chassis. The standby controller 220 performs a periodic health check on the alternate power source to determine if the power supply is no longer sustainable and reports status via the NVDIMM I2C interface.

The long-term lifetime of an EDL capacitor shows the temperature and operating voltage. For example, in aluminum capacitors, the temperature is usually reduced by 10 times per 10 °C. Also like an aluminum capacitor, this capacitor is sensitive to the operating voltage index. Maxwell Technologies uses a thermal-non-thermal (T-NT) model to model the life of PC10 capacitors in hours: Where T is the Kay temperature and V is the operating voltage in volts. This model assumes that the capacitor has been reduced by 20% from its initial value at the end of the capacitor's lifetime. A number of different operating environments are presented in the table below to demonstrate the expected life of the PC10 capacitor:

As shown, the capacitors operate at low operating voltages that affect the structure of the voltage regulator. In a parallel configuration, the total capacitance is the sum of all capacitors. However, this discharge current is large for a small voltage swing during use. Voltage regulators require a boost switch mode power architecture with high current inductors. In a series configuration, the total capacitance is the reciprocal of the sum of the reciprocals of the capacitance, but the total operating voltage has increased. Problems include balancing the operating voltage between capacitors and keeping the number of capacitors reasonable. For design exploration purposes, an operating temperature of 50 ° C has been chosen, allowing the design to use a 75% capacitor operating voltage for a 10-year lifetime. This condition allows a temperature rise of 15 ° C outside the common 35 ° C external ambient temperature of the corporate computer within the server room. Another target environment would be a telecommunications NEBS standard with a maximum ambient temperature of 40 °C, which can be increased to within the equipment frame during short-term HVAC failures. The ambient temperature of 50 ° C at a higher temperature of 5 ° C. The length of each short-term temperature failure is defined as up to 96 hours, but not more than 15 days per year.

Figure 9 shows an external EDL capacitor backup power architecture, which is a more detailed version of Figure 2. Some embodiments provide a capacitor charger, such as a capacitor bank charger that implements a constant current, constant voltage design. The charger applies a constant current to the capacitor bank until the capacitor bank reaches its final full charging voltage. At that time, the charger applies a constant voltage to float the capacitor bank. The floating voltage is applied because the EDL capacitor has a relatively large leakage current that requires the balancing resistor within the capacitor bank to be biased to ensure that all capacitors within the capacitor bank have an equivalent charging voltage. Since the size of the capacitor bank can be optimized for each configuration, the floating voltage can be programmed by a resistor to the nearest 1%. The float voltage can be set from VCHRG (minus a certain headroom height) to 6 volts. The design can utilize LiOn battery charger technology (usually a single-ended primary inductor converter or SEPIC architecture), but other techniques can be used. Some chargers require a small processor to monitor the charge cycle and switch the charger from constant current operation to constant voltage operation. For such designs, the processor within controller 110 can be used depending on the complexity of the algorithm and the hardware connectivity to the charger design. The following table provides information related to VCHRG and VCAP.

annotation:

1. Depending on the system, for example, in some embodiments, a wider power range There can be advantages.

2. The nominal floating voltage of the capacitor bank. During the discharge cycle, the regulator continues to operate until the capacitor bank discharges to 2.8V or lower.

annotation:

1. Based on an example customer specification, the charger consumes no more than the maximum size under all conditions.

2. Based on U1 operating at 70% efficiency, U3 operating at 80% efficiency, and U4 operating at 90% efficiency, VCAP operating at 2.8V (low end of operating range) has a 2% loss. .

The described embodiments also include a health status monitor for the backup power source. EDL capacitors have a finite lifetime that is sensitive to the operating voltage, ambient or storage temperature, and the number of charge/discharge cycles (wear). In some applications, only the operating voltage and ambient temperature are important, for example, if the number of prediction periods is 100 times smaller than the specification. The lifetime of an EDL capacitor is based on a capacitor that is reduced to a specified threshold (in most cases, a 30% drop from the initial capacitance) or an ESR that increases to a specified threshold (depending on the manufacturer, 30% to 100% increase in initial ESR). Assuming the sensitivity of the EDL capacitor to stress, the controller monitors the health of the capacitor. The health status monitor U11 (Fig. 9) can be combined with the charger U6 according to the implementation. If the capacitor bank is charged enough to handle the power loss, the health monitor will notify the FPGA. In general, the charger U6 must be able to "break" during the test. open". For example, in embodiments having a plurality of series capacitors, the voltage at each capacitor can be monitored and sent to a signal that can be inspected via the backup power supply I2C bus. This allows identification of the particular capacitor that has failed and indicates that the alternate power source has all failed.

Measuring the time from energization (applying VCHRG power) to when the VCAP reaches a fully charged state provides one way to estimate the health of the capacitor bank. Controller 110 can report whether module 100 is capable of processing a power loss event. If the capacitor bank never reaches a fully charged state, the system detects this condition and announces an error.

To measure the capacitance, fully charge the capacitor. The charger is first disconnected and a fixed known load (resistor) is applied to the capacitor bank for a certain period of time to slightly discharge the capacitor. In general, the load current is too small to prevent ESR impact measurements. If the VCAP supply drops below a fixed voltage, the measurement method can be as simple as triggering an interrupted voltage comparator on controller 110. If the interrupt is triggered during the test, the capacitance is too low and the capacitor bank fails the test. One problem is that because the power loss event may occur just after the self-test, the capacitor is partially discharged, which must be considered within the energy budget.

In order to minimize the cost of the EDL capacitor power supply, the self-testing intelligence is positioned on the module 110. To control the logic in the power supply, use an I2C to the GPIO expander device. Therefore, the controller 110 can control and monitor the signals on the standby power module (eg, 200 or 300).

As discussed, under certain conditions, it may be preferable to select a battery that is superior to an EDL capacitor because the battery has a higher energy density than an EDL capacitor. And therefore requires less volume and quality. For example, a single A123 battery has a current rating of 2.3 Ah at 3.3 V, weighs 70 grams and requires 2 cubic feet. If the module 100 requires 5 watts for 2 minutes, the required energy is only 0.05 Ah, which exceeds the order of magnitude of the battery capacity. Most battery chargers for portable laptops have all the necessary features for a backup power supply. In addition, most of these devices have an integrated I2C interface for monitoring, configuration, and control that can be used by module 100.

SD data format

In a single SD/MMC+ card operation, the first block of the SD card (byte 0 to byte 511) is used for SPD and flash configuration purposes. The remaining blocks in the SD card are used for backup data. During the standby operation, the spare data is streamed from the first DRAM device in a continuous byte stream and written into a single flash memory. The standby controller then repeats the process for other DRAM devices until the standby of all other devices is completed. During the restore operation, the data is streamed from a single flash memory in a sequential byte and written to the first DRAM device. The standby controller then repeats the process for other DRAM devices until all other devices are completed. The standby controller stream reads and writes data to the flash memory using a single continuous read/write operation. This mechanism allows the SD card to execute at the maximum bandwidth, but it has the side effect that if the length of each DRAM backup image file is not a multiple of 512 bytes, the arrangement of each DRAM backup image file may exceed SD. The boundary of the card block.

For dual SD/MMC+ card operation, the first block of the SD card (byte 0 to byte 511) in slot 0 is used for SPD and flash configuration purposes. The first block of another SD card in slot 1 is not used and is ignored. In standby During operation, the data is streamed from the first DRAM device in a continuous byte group and simultaneously written into the two flash memories. The data stream is split into two flash write data streams by sending all even bytes to slot 0 and sending all odd bytes to slot 1. The standby controller then repeats the process for other devices until all DRAM devices are completed. During a restore operation, data is read from two flash memories that are serially interleaved via a byte to form a single stream of data written into the first DRAM for combination. The standby controller then repeats the process for other DRAM devices until all devices are completed. The standby controller stream reads and writes data to the flash memory for each SD card using a single continuous read/write operation. This mechanism allows the SD card to execute at the maximum bandwidth, but it has the side effect that if the length of each DRAM backup image file is not a multiple of 1 kHz, the arrangement of each DRAM backup image file may exceed the traversal. The boundary of the SD card block.

For four-wire SD/MMC+ card operation, the first block of the SD card (byte 0 to byte 511) in slot 0 is used for SPD and flash configuration purposes. The first block of another SD card in slot 1 is not used and is ignored. During the standby operation, the data is streamed from the first DRAM device in a continuous byte group and simultaneously written to all of the flash memory. The data stream is divided into four flash write data streams by sending every 4 bytes to an interface. The standby controller then repeats the process for other devices until all DRAM devices are completed. During a restore operation, data is read from two flash memories that are serially interleaved via a byte to form a single stream of data written into the first DRAM for combination. The standby controller then repeats the process for other DRAM devices until all devices are completed. Standby controller Streaming uses a single continuous read/write operation to read and write data to the flash memory for each SD card. This mechanism allows the SD card to execute at the maximum bandwidth, but it has the side effect that if the length of each DRAM backup image file is not a multiple of 2 kilobytes, the arrangement of each DRAM backup image file may exceed The boundary of the SD card block.

The following table provides an example of the worst-case write/read bandwidth for each SD/MMC card and for each MMC+ card using 20 million bytes/sec and 40 million bytes/sec, respectively. Standby time. This calculation also includes the worst case SD/MMC+ write interval used to update the flash configuration.

Pre-burning self-test operation

DIMM 100 also includes self-test functionality. Self-test can be triggered by using the PRODTEST input on the FPGA and via the NV I2C interface. Store the results of this self-test permanently until another self-test sequence The column erases the flash memory. In one example, self-test: receive DDR interface (FET switch off); set the ongoing SELFTEST test bit high; fill DRAM memory with 0xA5; fill flash memory with 0x00; turn on progress LED; The DRAM memory is spared to the flash memory; the DRAM memory is filled with 0x00; the DRAM memory is restored from the flash memory; the content of the DRAM memory is tested; and if an error is detected, an error LED is set and the result is stored. In the flash. If no errors are found, the process returns to fill the flash memory with 0x00. The self-test method can be defined by various users of the system of Figure 1, for example, the methods can be defined by the customer.

Visual indicator

Especially when multiple modules 100 are used within a system, the visual indication on the board allows for the diagnosis of system problems with the memory module. Under the following conditions, the slow flash of an LED is 0.25 second on and 1 second off, and the fast flash of one LED is 0.5 second on and 0.5 second off. The memory module has LEDs to indicate that alternate operations are occurring. Assuming some configuration takes many minutes to complete the standby operation, the LED indicates to the service technician that the module 100 or capacitor bank must be undisturbed after the power loss event.

Provide a visual indication to the backup power source to indicate that the backup power is correct Connected, charged, fully charged or disabled. For example, this may be useful in systems having multiple modules 100, and it is possible that a service technician must physically identify a failed module or capacitor for replacement.

Visual indicator LEDs were also used during the burn-in test. If either of the self tests fails during the burn-in test, the red LED is locked. To demonstrate that the self-test operation is in progress, the green LED will flash during the self-test. When the test is in progress, the green LED is toggled at the end of each test cycle (write/read DRAM and read/write flash memory).

For example, an external system can include various types of systems, such as a host, a server, a client, and a network of various systems. The volatile memory 120 may include, for example, dynamic random access memory (DRAM), Z-RAM®, static random access memory (SRAM), and dual transistor RAM (TTRAM). Non-volatile memory 130 may include, for example, read only memory (ROM), flash memory, ferroelectric RAM (FeRAM), programmable metallization unit (PMC), and the like. In some embodiments, backup power supply 200 can be included as part of DIMM 100, while in other embodiments, backup power supply 200 can be, for example, an external device. The non-volatile memory 130 and the volatile memory 120 can be of various sizes and need not be the same size. During alternate operations, various embodiments may move all of the data stored in the volatile memory 120 to a non-volatile memory 130 or a portion of the data stored in the volatile memory 120. set. The same is true during the recovery operation from the non-volatile memory 130 to the volatile memory 120. Some embodiments of FIG. 1 do not include each component and/or function of FIG. For example, some embodiments do not include isolation logic 140. Some embodiments do not store SPD information in volatile memory 120. Some embodiments simultaneously move all data stored in volatile memory 120 to Non-volatile memory 130 (eg, all DRAM devices at the same time), and some embodiments move the data stored in volatile memory 120 in chunks to non-volatile memory 130, for example, one DRAM device at a time.

Controller 110 can be implemented, for example, using various FPGAs, controllers, processors, and/or memories. In another embodiment, the non-volatile controller 110 is a special application integrated circuit (ASIC) that includes a flash chip interface within the controller. By incorporating the flash die interface into the ASIC controller, the external SD/MMC+ controller will not be used and the save/restore performance can be improved. In another embodiment, the volatile memory 120 can be divided into various segments by using various start and end addresses. These addresses can be configured by the scratchpad in the NVDIMM I2C bus set controller 110. Which segments (and in what order) defined by such addresses should be spared and/or restored can also be controlled by setting a register in controller 110. Although the present invention has been described and illustrated in the foregoing embodiments of the present invention, it is understood that the present invention is described by way of example only, and the embodiments of the present invention may be practiced without departing from the spirit and scope of the invention The spirit and scope of the present invention is limited only by the scope of the following claims.

100‧‧‧Dual-line memory module (DIMM)

105‧‧‧ interface

110‧‧‧ Controller

115‧‧‧FPGA programmable read-only memory

120‧‧‧ volatile memory

121‧‧‧DRAM chip

122‧‧‧DRAM chip

130‧‧‧Non-volatile memory

131‧‧‧Flash Chip/Flash Device

132‧‧‧flash device

140‧‧‧Isolation Logic

150‧‧‧ Signal

161‧‧‧PLL

162‧‧‧ 存存器

163‧‧‧FET bus switch / FET multiplexer

164‧‧‧FET Switch/FET Multiplexer

170‧‧‧Interface line/signal

171‧‧‧VBACK

Claims (16)

A memory device comprising: a volatile memory; an interface for connecting to a backup power source configured to supply power to the volatility after a power loss of one of the primary power sources occurs Memory; non-volatile memory; a first configuration data bus, the first configuration data bus is used to access parameters describing the substantially permanent characteristics of the volatile memory, wherein the parameters are stored In a first address space; a second configuration data bus, the second configuration data bus is used to access the health status information of the standby power source, the health status information includes whether the backup power source has One of the failure indications, wherein the health status information is stored in a second address space, wherein the first configuration data bus and the second configuration data bus implement an identical bus arrangement, and wherein the The one address space and the second address space are separate from each other; a controller, the controller and the first configuration data bus, the second configuration data bus, the volatile memory, and the Volatile memory communication, the controller being programmed to detect an indication of whether the alternate power source has failed by extracting the health status information from the second address space, and in response to the indication, Sending, by the host, one of the backup power source failures, and in response to a command from the host based on the alarm of the failed alternate power source, moving data from the volatile memory to the non-volatile memory for Avoid data loss, The data to be moved includes at least one of cache data, user data and operating system data; wherein the first configuration information of the controller is readable and writable via the first configuration data bus At least one of the information; and the health status information is at least one of readable and writable via the second configuration data bus. The memory device of claim 1, wherein the health status information includes a status of the standby power source, the status indicating that the standby power source is at least one of a charged state, a discharged state, and a charged state. The memory device of claim 1, wherein the health status information indicates whether any of the capacitors including the alternate power source have failed. The memory device of claim 3, wherein the health status information indicates which of the capacitors including the alternate power source has failed. The memory device of claim 1, wherein the health status information indicates a type of the alternate power source. The memory device of claim 5, wherein the type is a capacitor or a battery. The memory device of claim 1, wherein the second configuration data bus is configured to access status information of the non-volatile memory, wherein the status information indicates that the non-volatile memory is in a write state, At least one of the erased state, the erased state, and the damaged state. The memory device of claim 1, wherein the second configuration data bus is configured to access status information of the non-volatile memory, wherein the status information includes header information of the non-volatile memory. The memory device of claim 1, wherein the second configuration data bus is configured to access status information of the non-volatile memory, wherein the status information includes a number of damaged memory blocks, The number of spare memory blocks, the number of completed download cycles, the number of Error Correcting Code (ECC) errors in a final download, the number of ECC errors in a final restore, one of the last downloads At least one of a state and a state of a final restoration. The memory device of claim 1, wherein the volatile memory comprises a dynamic random access memory. The memory device of claim 1, wherein the non-volatile memory comprises electronic erasable programmable read only memory (EEPROMs). The memory device of claim 1, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). The memory device of claim 1, wherein the controller is further programmed to move data from the non-volatile memory to the volatile memory when power recovery of one of the primary power sources occurs. The memory device of claim 1, wherein the same bus bar protocol is an internal integrated circuit bus bar protocol. The memory device of claim 1, wherein the parameters comprise sequence presence detection information. The memory device of claim 1, wherein the data comprises at least one of a file system key material and a file system directory material.