TW201106371A - A flash backed DRAM module - Google Patents

Abstract

A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.

Description

201106371 VI. INSTRUCTIONS: This application claims the priority of U.S. Patent Application Serial No. 12/369,027, filed on Feb. 11, 2009, and claims the U.S. Patent Application No. Priority No. 12/369,032; priority to US Patent Application No. 12/369, No. 4, filed on February 11, 2009, filed on February 12, 2009. Priority of US Patent No. 369,046; priority to U.S. Patent Application Serial No. 12/369, No. 52, filed on February 29, 2009; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> /us〇9/33755 priority. [Technical Field] The disclosed subject matter relates to a stage backup flash memory double-line memory module (DIMM) module. [Prior Art] Digital processing devices such as RAID systems sometimes use, for example, a memory cache to improve the performance of read and write operations. Volatile memory is often used to implement the cache. However, if the power source of the volatile ticks fails, then the data stored in the volatile memory can be lost. In addition, volatile memory devices such as DRAM memory modules typically require certain parameters describing the nature of the DRAM device that is to be placed in a separate non-volatile memory located on the memory module. One example of this is the Sequence Presence Detection (.SPD). However, the storage of this information may only require the addition of the entire non-volatile memory to the volatile memory for this purpose. SUMMARY OF THE INVENTION The present disclosure is directed to a flash memory dual-line memory module (DIMM) module that includes a non-volatile memory, a volatile memory, and a controller. During normal operation, the DIMM is powered by a primary power source. When the primary power source is interrupted, an alternate power source supplies sufficient temporary power to the DIMM to allow the controller to transfer data from the volatile memory to the non-volatile memory before the power from the alternate power source is exhausted. in. The controller returns the data stored in the non-volatile memory back to the volatile memory when the primary power source becomes available again. When the controller moves the data from the volatile memory to the non-volatile memory, the controller places the memory portion of the data to be moved into a normal operation state, and the memory portion of the data is not moved. Placed in a low power state. In one aspect, a memory device for use with a primary power source includes: a volatile memory that includes a plurality of memory portions, each of the plurality of memory portions having a normal operating state and A 201106371 low power state interface for connecting to a standby power source configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; a non-volatile And a controller that communicates with the volatile memory and the non-volatile memory and is programmed to detect a power loss of the primary power source, and each time at least one of the memory portions is responsive to The data moves from the volatile memory to the non-volatile memory, and when the data is moved from the volatile memory to the non-volatile memory, the memory portion from which the data is being moved is placed in a normal operating state' The portion of the memory from which the data is not being moved is placed in a low power state. In another aspect, the method includes: a debt detecting a volatile power source, a main power source, a power failure, the volatile memory including a plurality of memory portions, and the plurality of memory portions Each has a normal operating state and a low power state; and in response to detecting the power failure and the volatile memory is powered by the backup power source: at least one memory portion will be stored in the volatile each time The data in the memory moves to the non-volatile memory; and when the data is moved from the volatile memory to the non-volatile memory, the portion of the memory from which the data is being moved is placed in the normal operating state' and will not be positive The mobile data is placed in a low power state from the memory portion. In another aspect, a device and a device include: a volatile memory, the plurality of memory segments are defined by at least one end address; and a memory used together with the main power source includes a plurality of memory regions a segment, a start address and a corresponding at least r' for connection to a backup work '201106371 source, the alternate power source configured to temporarily supply power to the volatilization after a power loss from one of the main power sources occurs a non-volatile memory; and a controller that communicates with the volatile memory and the non-volatile S memory and is programmed to detect a power loss of the primary power source and is based on The at least one start address and the at least one end address are responsive to moving data from the volatile memory to the non-volatile memory. In some aspects, there is only one at least one start address and only one at least one end address exists, and moving data from the volatile memory to the non-volatile memory includes moving only to a start address The data in the volatile memory at the address between the address and the end address. In another aspect, a method includes: detecting a power failure of one of a primary power source of a volatile memory, the volatile memory comprising a plurality of memory segments, the plurality of memory segments being at least a start address and a corresponding at least one end address definition; and in response to detecting the power failure and when the volatile memory is powered by a standby power source: based on at least one start address and at least one end bit The site moves the data stored in the volatile § memory to a non-volatile memory. In some aspects, there is only one at least one start address and only one at least one end address exists, and moving the data from the volatile memory to the non-volatile S memory includes moving only in a start bit The information in the volatile memory at the address between the address and an end address. In another aspect, a device includes: a non-volatile memory; a controller in communication with the non-volatile memory, wherein the controller is programmed to be a primary power source of a volatile memory a power loss [201106371 occurs after the data is moved from the volatile memory to the non-volatile memory; and a backup power supply that provides temporary power to the controller after the power loss of the primary power source occurs Volatile memory The backup power supply includes: a capacitor bank having an output terminal; - a connection to a voltage source that charges the capacitor bank to a normal operating voltage; and a health monitor that is programmed A fault signal is generated based on a voltage at the output terminal of the capacitor bank. In another aspect, a method includes interrupting charging of a capacitor bank by a voltage source configured to provide temporary power to a controller, the controller being programmed to be in a volatile memory One of the main power sources generates power loss from the volatile memory to a non-volatile memory, and provides power to a volatile memory after the power loss occurs in a main power source; When charging is interrupted, applying a predetermined resistance to an output terminal of all of the capacitor banks for a predetermined period of time; monitoring the output terminal of the capacitor bank during the predetermined period to determine whether the voltage at the output terminal falls to a predetermined period Below the voltage limit, and the voltage at the output terminal to the right falls below the predetermined threshold voltage within the predetermined time period, a fault signal is generated. In another aspect, a device includes a volatile memory; one or more non-volatile memory chips, each of which is stored in a data stored from the volatile S-reminis; an interface, Connected to an alternate power source configured to temporarily supply power to the volatile memory after a power loss occurs in one of the main power sources; a controller, which is associated with volatile memory and Volatile memory communication, wherein 8 201106371 the controller is programmed to move data from the volatile memory to the non-volatile memory chip after the power loss of one of the main power sources of the (four) memory occurs; The parameters describing the volatile memory are stored in at least one of the non-volatile memory chips, and the non-volatile memory chips are stored from the volatile memory. In some cases, the parameters include sequence presence detection information. In another aspect, a method includes describing a volatile memory based storage after a power loss of one of the primary power sources of the volatile memory occurs, that is, when the volatile memory is temporarily powered by an alternate power source. In a parameter of at least one of the non-volatile memory chips, the non-volatile memory chips store data transferred from the volatile memory to move the data from the volatile memory to the non-volatile memory chip. Each of the non-volatile memory chips is used to store data transferred from the volatile memory. In some aspects, the parameters include the presence of detection information in the sequence. In some aspects, a memory device includes: a volatile memory; an interface for connecting to a backup power source configured to supply power after a power loss occurs in one of the primary power sources To the volatile memory; non-volatile memory; a first configuration data bus for accessing parameters describing the presence detection of the volatile memory; a second configuration data bus, At least one of health status information for accessing the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus are implemented

a same bus bar protocol; a controller that communicates with the first configuration data M 201106371, the second configuration data bus, the volatile memory, and the non-volatile memory, the controller is programmed Transmitting to detect a power loss of the primary power source and in response to moving the data from the volatile memory to the non-volatile memory, wherein the first configuration information of the controller is via the first configuration data bus At least one of readable and writable information; and wherein at least one of the health status information and the status information is at least one of readable and writable information via the second configuration data bus. In another aspect, a memory device for use with a primary power source and a backup power source includes: a volatile memory; an interface for connecting to an alternate power source, the alternate power source configured To temporarily supply power to the volatile memory after the power loss from one of the main power sources occurs; the full operation is forced, and the benefit is _iU..

One of the power losses reacts.

In a non-volatile memory, the non-volatile memory includes an optional number of non-volatile memory chips, wherein the movement is based on the selectable number of non-volatile memory chips. In another aspect, a memory device for use with a host processor and a primary power source includes: a non-volatile memory; a volatile memory; an interface for connecting to an alternate power source The standby power source is configured to temporarily supply power to the volatile memory after power loss from one of the primary power sources occurs; and isolation logic for controlling access by the host processor to the volatile memory The isolation logic has a -first mode and a second mode, the isolation logic providing the host processor with access to the volatile memory for storing or reading data during the first mode, and the The isolation logic isolates the volatile memory from access by the host processor during the second mode; and a controller 'which controls the isolation logic, the controller is programmed to when the volatile memory is being The isolation logic is placed in the first mode when the primary power source is powered, and when the power from the primary power source to the volatile memory is interrupted, the isolation logic is placed in the second mode and the data is The volatile memory is transmitted to the non-volatile memory. In another example, the method includes: detecting a power source of one of the main power sources of the volatile memory, and responding to detecting the power failure and the volatile memory is replaced by the standby power. When the source is powered: one mode of the isolation logic is changed from the first mode to the second mode, and the first mode is when the volatile memory is being powered by the main power (four) - the host processor provides a pair for storage Or reading the volatile memory of the data. The second mode separates the volatile memory from the host processor [s 201106371; and moves the data stored in the volatile memory [Non-Volatile Memory] [Embodiment] Referring to Figure 1 , the described embodiment of the present invention is a dual-line memory module (DIMM) 100, which includes volatile memory 12 〇, non-volatile memory Body 130, isolation logic 14〇 and controller n〇. DIMM 100 is connected to a primary power source (not shown) to support normal operation and is also connected to alternate power source 200 (see Figure 2). When the DIMM 1 is operating at the power supplied by the primary power source, an external system (e.g., a RAID system) stores the data in the volatile memory 12 via the interface 105 and reads the data from the volatile memory 120. However, when the power from the primary power source 2 is interrupted, the backup power source supplies sufficient temporary power to the DIMM 100 so that the controller 11 can cause the isolation logic 14 to isolate the volatile memory 120 from the external system, and The data is then transferred from the volatile memory to the non-volatile memory 13Q I before the power from the alternate power source 200 is depleted. When the primary power source becomes available again, 'control n 1 ίο will survive. The data in the volatile memory 传 is passed back to the volatile memory H i 2Q + 'and causes the isolation logic to reconnect the volatile memory 120 to the external system. Volatile memory 120 is a DRAM array that includes various DRAM wafers, such as DRAM wafers i 2 and DRAM wafers 122. Non-volatile memory 13〇 includes various flash memory devices, “12 201106371 J such as Shaanxi flash device 13 1 and flash device 丨 3 2. Due to the limitation of DIMM丨〇〇, it cannot be stored in volatile at one time. All of the data in the memory 120 is moved to the non-volatile memory 13G. One of these limitations is that it cannot be written to the non-volatile memory 13 as quickly as the DRAM device of the volatile memory 120 reads. In the flash device, in consideration of this difference, each time a DRAM wafer moves data from the volatile memory to the non-volatile memory 13Ge, in addition, the data is transferred from the volatile memory 120 to the non-volatile memory 13 During the process, the DRAM chip that is not actively being transferred enters a low power state, the low power state retains the data stored therein, but consumes less power than the normal operating state. In the DRAM chip of the volatile memory 12, This low power state is a self-renew mode. By allowing a DRAM chip that is not actively transmitting to enter a low power state, the module 1 需要 requires less power during standby operation than would otherwise be the case. In this case, this allows the use of a smaller and cheaper alternative power source. Figure 2 shows a block diagram of this power source. In particular, Figure 2 shows an electrochemical double-layer (EDL) capacitor backup power module. 2〇〇, it uses an interface line (for example, power, 1/〇, etc.) 17〇 to interact with DIMM 10〇 (EDL capacitors are also called supercapacitors and ultra-high capacitors). Electric grid 21 0 is in DIMM 1 〇〇 The backup power is supplied to the DIMM 100 when the main power source fails. The charger and monitor 22 充电 charges the capacitor 210 and performs a health monitoring of the capacitor 21 以便 to, for example, fail the capacitor 210 to provide backup power. In the case of DIMM 1 〇〇 alarm. In some cases, the battery can be replaced by the electric 13 201106371 container. For example, Figure 3 shows the battery backup power module 300 used in place of the module 2 之Non-volatile memory 130 embeds sequence presence detection (SPD) information for volatile memory 12〇 (eg, information describing the size and speed of DRAM chips in volatile memory i2Q) By using the non-volatile memory 130 to store the spD information of the volatile memory 12, the volatile memory 120 avoids the need to have a separate EEPROM module for storing this information. Avoiding the addition of a separate EEpR〇M can save cost. The size of the small module 100 and the number of required components are reduced. The DIMM 100 includes two i2c busbars between the external system and the controller 11A. When, for example, simplicity and low manufacturing cost are more important than speed, I2C The busbars are typically used to attach low speed peripheral devices to various devices. The first I2C busbar is used to access the sequence presence detection (spD) EEPROM ("SPD I2C Busbar"). It is defined by the standard jedec specification. The second I2C bus is used to access information of other modules, such as status information and health status (s〇H) for controller 11 非, non-volatile memory 丨 3 〇 and standby power source 200. Information ("NVDIMM I2c Bus"). The status information may include, for example, the current state of the flash memory (write, erased, erased, corrupted, etc.); the number of bad blocks that were replaced; the number of remaining spare blocks; completed The total number of download cycles; the number of ECC errors in the last download; the number of ECC errors in the final restore; the status of the last download (in progress, no error completion, error completion, etc.); the final state of recovery (in progress, No error completion, error completion, etc.); flash header information. The s〇H information '201106371 may include, for example, the current state of the alternate power source (charged, discharged, positively charged, etc.), whether any of the capacitors that make up the alternate power source have failed (and if it has failed, determine which capacitors have Failure) and the type of alternate power source (eg, capacitor or battery). Block Diagram 钿f Flash § Recall 1 provides non-volatile storage on the DIMM and is implemented using Secure Digital (SD) / MultiMedia Card + (MMC+). The controller 11 supports various configurations. For example, four independent SD/MMC+ interfaces are connected to four SD mass storage devices, and each SD mass storage device uses a 4-bit data bus with 2 megabytes. / sec bandwidth operation, or interface to four MMC + mass storage devices, each MMC + mass storage device uses 8 _ data bus, operating with 4 〇 7G group / sec bandwidth. One of the advantages of using SD/MMC technology is that the complexity of managing flash memory is hidden from controller 110 by a simple, low pin count interface. Flash memory can be implemented as a single device (e.g., 'SanDisk iNAND) or can be constructed on a single mMM using discrete § controllers with separate NAND memory devices. In either case, the SD/MMC controller is responsible for ECC and bad block management depending on the NAND technology used. The sequence presence detection (SPD) data is stored in the first 256-bit flash memory, and the flash memory is attached to the first SD/MMC+ interface (ie, the flash memory is stored in the flash) A flag within the configuration space is used to implement a typical write protection mechanism. The controller 11 implements a read cache and write mechanism for SPD data, wherein the spD information can be stored [15 201106371 on the controller 110 In the 5 memory (except on the flash chip 13 1). In the system power-on period, the control is controlled by 11 U〇 from the flash memory k to take the SPD material. In spD j Run Query # π ± The read operation on the interface is fast = 'At the same time, the write operation is immediately written to the flash memory. During the write operation to the flash memory, the interface will ignore any read. Or write request. : The information is stored in the second 256-bit flash memory flash memory attached to the SD-MMC + interface. This interface allows the user to monitor and configure non-volatile functions. Operation. This area is also used to track the status of the system during the last power cycle. The read cache and write cache mechanism for configuration data, wherein the state information can be stored in the cache memory on the control g 11G (except on the (4) wafer 131). During the system power on period, the FPGA Flash memory extraction data. The read and write operations on the NVDIMMI2C interface use the data. During the power outage and power loss (standby) events, the cache data is written back. The controller 110 is an advanced embedded processor. The processor has a custom 133 MHz DDR controller, four custom SD/MMC+ host interfaces, an SPD I2C interface, and an NVDIMM I2C interface. The microprocessor can be, for example, a soft 32-bit Altera NIOS RISC processor. It can execute the firmware from the internal memory instance in the FPGA (programmable read-only memory (pR〇M) n5). The processor controls the module between the DDR interface and the SD/MMC + interface. Move the operating state and control the communication between the SPD interface and the NVDIMMI2C interface. The 16 201106371 DDR interface allows the controller 110 to operate the DRAM array on a per-tuple channel basis. The interface has individual control of the CKe signal. Thus Allows control of each device in the DRAM array. The controller uses the first 8 bytes of each byte channel in the array to set the internal phase alignment of the bus. Four custom SD/MMC + interfaces are designed For embedded applications that do not require features such as hot swap. The interface supports 1-bit, 4-bit and 8-bit operations at clock rates up to 5 〇 MHz. These interfaces can also be used simultaneously. Operation synchronizes four SD/MMC+ cards, allowing high-bandwidth read and write operations without extensive data buffering For applications that need to remove SD/MMC+ cards, the FPGA host interface allows for heavy-duty installations without the correct order Sort the cards. The volatile s-resonance 120 is a DRAM array. Various example configurations are shown in the table below, which include an 8-bit Error Correcting Code (ECC) for the actual data per 64 bits. In an example of a two-billion-bit NVDIMM, one row can be turned on or off based on current memory requirements. Turn off when a row is not needed to save power. When moving the data (actual data and Ecc) from the volatile memory 12〇 to the non-volatile memory! 3 〇, non-volatile memory! The actual data and ECC are stored and stored; ^The actual data in the non-volatile memory 13〇 is different from the ECC*. When the data is transferred from the non-volatile memory and the sputum back to the volatile simon memory 120, the controller 复原 restores the actual data and ECC of the special DRAM device suitable for ί to the volatile memory 12〇 in. 201106371 NVDIMM Total DRAM Device Configuration DRAM 4^# Column 256 megabytes 512 megabytes 32M words X 16 bits 5 1 512 million bytes 1 billion bits 64M words X 16 bits 5 1 1 billion bits 1 billion bits 128M words x8 bits 9 1 2 billion bits 1 billion bits 128M words X 8 bits 18 2 PLL 161 is a high performance, low time skew, Based on a PLL, zero delay buffer, this buffer spreads a differential input clock signal to the DRAM array. The DDR clock from the edge connector is multiplexed with the DDR2 clock from controller 110 to prevent PLL 161 from entering its low power state and to prevent PLL 161 from tri-state its output. In this example design, the selected PLL must operate at the desired system rate and at the slower DDR controller rate. In general, the PLL skips itself and operates as a small delay buffer at the slowest clock rate. The control and address signals are re-driven via register 162 to the DRAM device on the rising edge of the clock (data access is delayed by one clock). Controller 110 uses three states to access the address and control signals. When controller 110 controls DRAM 120, FET bus switch 163 can be used to isolate the register from the edge connector and controller 110 can directly drive the register input. When the system controls the DRAM array, the FET bus switch 163 is turned "on" and the FPGA tri-states its output. The CKE signal is processed differently from other control signals. Switching between the two modes of operation has less glitchless to ensure that DRAM 120 is still in self-renew mode. For these signals, FET switch 163 uses [ 18 201106371 to multiplex between the edge connector (to the system) and the controller i. The wide bandwidth FET multiplexer 163 and FET multiplexer 164 are designed to support still wide bandwidth applications such as memory interleaving, bus isolation, and low distortion signal gating. The FET multiplexer 16s and FET multiplexer 164 isolates the module 丄〇〇 from the system bus during power loss events. The fet multiplexer uses a charge pump to increase the gate voltage of the transfer transistor to provide a low, flat on-state resistance. This low, flat on-state resistance allows for minimum propagation delay and supports rail-to-rail switching on data input/output (1/〇). FET彡Ji ϋ also features low data 1/〇 capacitance to minimize capacitive loading and signal distortion on the data bus. Depending on the configuration of the module 100, not all of the data stored in the volatile memory 120 is reserved for the non-volatile memory 13A. Alternatively, module 1 can be configured to reserve (and (4) recover) the data stored in the selected W-knife of volatile memory 12A. The information stored in the non-volatile memory is usually the key/directory information used to determine the location of the information (eg, files) in the system. The key/directory information is basically the most important information that all users will choose to reserve. However, other types of information can also be stored in volatile memory. For example, software program information that does not change (for example, the 'coffee' slot) can be stored in a volatile memory file. The controller m includes a register that allows the user to segment the volatile suffix 120. The start address is stored in a register and the end address is stored in a second register. It is expected that all data between these two addresses will be backed up and restored. Data stored outside of this address will not be backed up/restored. The value of these registers is controlled via the 19 201106371 I2C bus. The user can choose, for example, to specify a start address and an end address so that only critical/directory information can be renewed. The reason for choosing to restore only critical/directory information is to improve recovery time by not recovering from good time and without the need to recover from non-volatile memory (10) (eg "exe" is probably not changed and can be Load from the host system when needed). Module 100 can be configured to support a variety of flash chips (e.g., 1-4) and can be programmed according to a selected number. The number of flash chips used may be based, for example, on the size of the volatile memory that needs to be spared and the time that the backup must occur (eg, the amount of time the backup power is available) or based on achieving a recovery hazard. (ie, more flash devices allow for a faster recovery time). For example, for a controller that can support up to four flash chips, the controller will have four bus bars. Each of the bus banks can be connected to (or not connected to) the flash wafer according to the number of turns of the flash wafer. The selected number of flash wafers (e.g., 2 or 4) are connected to the bus bar and soldered to a printed circuit board (PCB). For a module 1 designed to accommodate up to four flash chips, if only two flash chips are installed, the remaining space for the two flash chips that are not mounted remains ^ and the controller 110 Stylized to attempt to communicate with only the two installed flash chips. For a constant (four) time or recovery time, the flash wafer: number can be increased in proportion to the size of the volatile memory. Alternatively, the spare time and recovery time can be reduced by increasing the number of flash chips. Signal Description [s] 20 201106371 Module 100 implements a 72-bit DDR2 memory interface with a 244-pin mini DIMM connector. The connector signal designation is defined in the JEDEC Standard 21C, page 4.20.14-2 of the DDR2 registered small DIMM design specification (currently available at www.jdec.org). Each of these signals may be part of signal 150 or signal 170. The signal corresponding to each of the 244 pins is not shown in Figure 1 to avoid making Figure 1 difficult to read. The NVDIMM-RESET signal initializes controller 110 and forces the controller to restart its state machine. When the standard RESET_IN input is determined, the controller 110 is also reset (together with, for example, the volatile memory 120 and the register 162). When controller 110 is reset by NVDIMM-RESET, module 100 will operate normally. That is, when NVDIMM_RESET is asserted, FET switch 163 remains on, thereby allowing the system to access DRAM memory 120 without further interaction. The NVDIMM_PG signal reports the power status in the user's system. When the signal is high, the system power rail operates within specifications. When the signal changes to a low level, the power loss approaches and the controller 110 moves the data to the flash memory 130. If the DRAM device data is moved to flash memory (as indicated by the NVCACHE_ENABLE signal), the system causes all DRAM devices (e.g., 121-122) to enter self-renew operation before negating NVDIMM_PG. If NVCACHE-ENABLE is low when NVDIMM_PG is negative, ij ignores the data in the DRAM device during the power loss event. 21 201106371 The NVCACHE_ENABLE signal reports the presence of cached data that should be moved to the flash memory in the DRAM device in the event of a system power failure. If NVCACHE_ENABLE is high when NVDIMM-PG is negative, controller 110 moves the data in the DRAM device to the flash memory. If NVCACHE_ENABLE is low when NVDIMM-PG is negative, the DRAM contents are ignored and are not stored in flash memory 130. The last order is used by the system to shut down normally (for example, in response to a user request to shut down without a power failure). When NVDIMM-PG is low, NVCACHE_ENABLE can be ignored by controller 110 to prevent false transitions on the signal from affecting any alternate events. During a restore operation, NVC ACHE_ENABLE is used by the system to signal controller 110 to erase flash memory 130. The used tag (radity tag) within the flash memory is not cleared until the signal exchange with NVCACHE_ENABLE is completed. This allows, for example, the system to handle another power loss event during the restore operation. After moving the data from the flash memory 130 to the DRAM 120, a DRAM_AVAILABLE signal indicating that the system can access the data is determined. When the system decides that flash memory 130 should be cleared (e.g., to prevent the data from being restored again after a power loss event), the system negates (falls edge) NVCACHE_ENABLE to reset the flash memory. The system waits for NVDIMM_READY to be determined before determining NVCACHE_ENABLE again. The system can continue to use module 100 until NVDIMM_READY is determined, but no data will be available during the power loss event. 22 201106371 The CACHE-DIRTY signal indicates that the flash memory 130 contains a data image of the DRAM 120. During the "standby" state, the CACHE_DIRTY signal indicates the beginning of the alternate process. During the "power on" state, CACHE_DIRTY indicates that flash memory 130 contains a backup image file. The signal remains high until the NVCACHE_ENABLE signal is negated (falling edge), indicating that the cached data has been read from DRAM 120. The DRAM-AVAILABLE signal indicates when the system can access the DRAM 120. Controller 110 has control of DRAM 120 when DRAM_AVAILABLE is low. When the signal is high, the system can cause the DRAM device (e.g., 121-122) to exit self-renew and access the data. In the case of powering up flash memory 130 with data, DRAM_AVAILABLE will remain negative until the flash data is moved to DRAM 120. Once the signal is determined, the system can read and write to DRAM 120, but NVCACHE_ENABLE cannot be determined until module 100 is ready. A delay can occur between the determination of DRAM_AVAILABLE and NVCACHE_ENABLE, for example, after the restore operation, because the volatile memory 130 is being erased or the alternate power source is being recharged. The system may choose to read only from the volatile memory 120 during this time (as opposed to reading from and writing to the volatile memory 120 from the volatile memory 120). The NVDIMM-READY signal indicating module 100 is capable of handling power loss events. This signal is undefined until the external power source is healthy and Γ fully charged. When configured to completely erase the flash memory 130 23 201106371, the NVDIMM_READY signal is also not determined until the flash memory 130 is fully initialized to a known state. This feature allows the design to support flash memory devices that do not support full-speed burst write operations without erasing the flash memory. During normal system operation (idle state), the system cannot determine NVCACHE_ENABLE until NVDIMM_READY is determined. NVDIMM_READY is negated during the standby operation. NDIMM-READY is negated during the restore operation. If the controller 110 determines at any time that the power loss event cannot be handled correctly, for example, if the EDL capacitor bank fails to perform a self-test operation, the controller 110 negates NVDIMM_READY to inform the system to move any cached data from the DIMM memory (eg, Move the data to a permanent storage such as the hard drive of the system). NVDIMM—SEATED is the pull-up pin on the DIMM pin. The pull-up pin allows the system to detect the module 100. ^The system can also detect the module 100 by attempting to read from the NVDIMM I2C interface. See if the I2C slave interface generates a response. The NVDIMM I2C slave interface on controller 110 provides a complete functional user interface to controller 110. The user can configure and control the controller 110 and access detailed status information using NVDIMM-SDA and NVDIMM_SCL (signal 152). V3P3_AUX is an auxiliary 3.3V rail that supplies power to non-volatile logic during normal system operation. During the power loss state, the module l〇p switches from this supply and operates from VBACK 171 (the power rail used by the power supply during the standby operation 24 201106371) until the controller 110 turns itself off. The module 100 also includes a third I2C interface between the controller 110 and the backup power source 200 ("backup power I2C interface"). The backup power I2C interface allows the controller 110 to communicate with the external backup power module using VBACK-SDA and VABACK_SCL. A mode of the standby power method (e.g., an 'EDL capacitor or battery) can be determined via the interface&apos; controller 110, and the state of charge and health of the power source can be determined. Information communicated in the backup power I2C interface can be communicated as part of the SoH information in the NVDIMM I2C interface. The standby power reset (VBACK_RESET) allows the controller 110 to reset the external standby power module "VCHRG voltage rail" to the EDL capacitor charging or the external battery backup power module. The voltage rail is a nominal 12 volt rail that can achieve 500 mA. The signal TEST_RX and the signal TEST_TX form a production test interface for a 57.6Kbaud serial link. These test signals are tri-stated and floating during normal system operation. State and State Transitions Figure 4 illustrates a state diagram showing various states and state transitions of module 100. For example, regardless of the state of operation of the module, the module 100 is initialized to a "power on" state by system reset. In this case, the module initializes all logic and extracts the configuration from the flash memory before determining what happened to the last power cycle. For example, the module loads firmware from FPGA PROM 115; CACHE_DIRTY is determined to be 'and' NVDIMM READY and DRAM_AVAILABLE are negated. 25 201106371 SD/MMC + flash memory is initialized to SD/MMC + transfer state. The configuration block is read to determine the state of the last power cycle. If the "used" tag is set and the previous standby operation is successfully completed, the state is switched to the "erased j state" (if configured to erase Execution time zone. If the execution time zone has not been configured to erase, the state is switched to the "reset" state. If the "Used" tab is set and the backup operation has not been successfully completed, move the status to the "Erase" state (if the "Erase" bit is set) or move to the DRAM-AVAILABLE and CACHE-DIRTY settings. The "idle" state. If the previous "erase" status is not completely completed and the "erase" bit is set, it is converted to the "erase" state to re-execute the erase cycle. If the "Used" tab is not set, the Bay 1J CACHE-DIRTY is negated, DRAM_AVAILABLE is determined, and the state transitions to the "Intermittent" state. When the system power is applied, the "intervening" state is the normal operating state. If CACHE_DIRTY has been set and then NVCACHE_ENABLE is determined, BJ1J CACHE-DIRTY is negated. CACHE-DIRTY can be used to acknowledge a response to an unsuccessful restore operation due to an invalid backup. If NVCACHE_ENABLE is determined and NVDIMM_READY is determined, then it is determined that CACHE-DIRTY will confirm that the controller is now operating in a non-volatile state (power loss will trigger an alternate operation). If NVCACHE_ENABLE is negative, then CACHE DIRTY is denied to confirm that the controller is now operating in a volatile state - Γ (power loss will not be performed alternately). If the alternate power source is within the voltage gauge 26 201106371, it is determined that the NVDIMM_READY indicates that the system can support a power failure. If the alternate power source fails to self-test (or controller 110 cannot complete the standby operation for any other reason), then NVDIMM-READY will signal the system to clear the cache memory. If CACHE_DIRTY is determined and NVDIMM_PG is negative, power is lost and the DRAM memory contains data to be written to the flash memory. In this case, the controller 110 denies DRAM_AVAILABLE and NVDIMM_READY and transitions to the "standby" state. If CACHE-DIRTY is negated and NVDIMM_PG is negated, the DRAM memory does not contain valid data and the power is normally turned off. In this case, DRAM-AVAILABLE and NVDIMM-READY (if set) are negated and transitioned to the "power off" state. The "standby" state is responsible for moving data from DRAM 120 to flash memory 130 when operating at standby power. If the "short pulse waveform interference" bit is not set, the controller 110 waits for the CKE to be low to ensure that the DRAM memory is self-renewed (if the standby operation starts, the "short pulse waveform interference" bit Set, but the power rises during operation). The on-board regulator switches from standby power to power supply. The DDR bus is disconnected and the controller 110 drives the DRAM 120. Because the system may be powered down, controller 110 masks the NVCACHE_ENABLE signal. Controller 11 determines the "used" register and writes to the flash configuration page to record the beginning of the alternate process. If there is a checkpoint due to a transition from the "short-time waveform interference" state, the controller 110 restarts the standby from the checkpoint. In addition, for every 27 201106371 dram device of the DRAM 120, the DRAM device is caused to re-enter the self and rewrite the memory UOM capacity. If the NDIMM_PG is determined during the memory copy operation, the active DRAM device is returned to self-renew, the current spare point is checked, and the "short pulse waveform interference" state is moved. When all DRAM devices have been copied to flash and the flash has completed its program loop, controller 110 writes the current state information in the flash configuration and waits for the program to cycle. Finally, controller 110 moves the module to the "power off" state.

If the system power is still available, the "power down" state handles the power down operation to prevent the memory module 100 from restarting in advance. That is, the NVDIMMJG can indicate a power loss event, but the system power may not have been removed from the memory module. If operating at standby power, controller 110 switches the onboard regulator back to normal power. The controller 变为10 tristates the interface between the controller and the multiplexer 163 and connects the DRAM device to the DDR bus. If the NVDIMM-pG is determined, the system power still exists, so the system moves to Restart in the "Power On" state. The glitch state indicates the condition in which the system temporarily loses power, but the power has returned before the standby operation is completed, allowing the user to retrieve DRAM content without using flash data. “Short Intermittent Waveform Interference j state can be entered multiple times during standby operation. There are two results in the “short pulse waveform interference” state. The power loss event continues and the data within DRAM 120 is backed up to flash 13 or the data within DRAM 120 is captured and NVC ACHE_ENABLE % is negated. If the power loss is temporary, the memory module must still [28 201106371 must recharge the EDL capacitor to a known state prior to determining NVDIMM__READY, and allow the system to be non-volatile. To this end, the module 100 records the event by determining the "short-time waveform interference" register to indicate the power restored before the standby power loss; switching the on-board regulator from the normal system power to the power supply; The device 110 is tri-stated and reconnects the DDR bus to the DRAM memory; determines the DRAM_AVAILABLE indicating that the data is available; masks the NYCACHE_ENABLE signal because the system can clear the data of the DRAM device; if the NVDIMM_PG is determined and the NVCACHE-ENABLE is negated Bay ij does not need to be partially copied in the flash memory, negates CACHE_DIRTY and transitions to the "erase" state; if NVCACHE_ENABLE is determined and NVDIMM_PG is negated, the power is lost and the DRAM memory contains the memory to be written to the flash memory. The data of the body, negating DRAM_AVAILABLE and transitioning to the "standby" state to restart from the checkpoint. The erase state is used to apply portions of the DRAM 120 for time-critical, non-volatile applications (eg, if the user has decided to store non-critical/directory information in the volatile memory 120 and has not selected to spare / Restore this non-critical/directory information). In the erased state, controller 110 can be configured to zero a single contiguous region in the address space. This feature structure prevents false ECC errors within the DRAM memory. Module 100: disconnecting the DDR bus and causing the controller 110 to drive the DRAM memory; if the erase function is interrupted by the NVDIMM_PG negating the indicated power f loss, then switching to the "power off" state; for each DRAM , 29 201106371 Initializes the configured address space to zero and initializes the associated ECC value; when all DRAMs are completed, transitions to the "reset" state. The "restore j state returns the flash memory 130 content back to the DRAM 120 ° without exiting the state until the system indicates that the recovered data in the DRAM has been read" to process the power loss event during this state. The power loss event during the period causes the same image to be restored to the DRAM memory on the next power-on event. Module 1〇〇: If not already done, then disconnect the DDR bus and cause the controller to drive the DRAM memory; recording the restore operation in the flash configuration memory has begun to allow the system to detect multiple recovery events. For each DRAM, copy the content from the flash memory to the DRAM, and when all DRAMs are completed, update the "mode" byte with the value stored in the flash configuration (at the "mode" value Read-only system "mode" value) and make the DRAM enter self-re-operation; if the recovery function is interrupted by NVDIMM_PG negating the indicated power loss, then switch to the "power off" state; change the controller into Tri-state and reconnect the DDR bus to the drami2〇; determine the RAM—AVAILABLE; and when the NVCACHE-ENABLE transitions from the high level to the low level (falling edge), transition to the “erase” state to erase the flash content. : Two-flash memory devices require that the memory be erased to achieve maximum bandwidth performance during large start-up operations. In these embodiments, at least the clearing of the portion of the copy or image is present in the flash memory 1 flag flag 1 except that the operation cannot occur until the system has instructed the dram 120 to read any of the data in the DRAM 12 (ie, 30) 201106371 data or part of the backup data). Module .1 〇〇 enters the “erase” state and: if the erase cycle is interrupted by another power loss, the erase cycle is first restarted; the controller 110 is tri-stated and the DDR bus is reconnected To DRAM 120; determine DRAM_AVAILABLE; if necessary, write the flash configuration to clear any flags indicating potential spare or backup image files within the flash memory and mark an erase cycle has begun; If the register is determined, the flash memory module is erased; if the erase function is interrupted by the NVDIMM_PG negating the indicated power loss, the mode is switched to the "power off" state; when the erase cycle is completed normally The flash configuration is updated; when the erase operation is completed, it transitions to the "idle" state. The I2C interface FPGA controller has two separate slave I2C interfaces that are controlled using the same protocol, such as the industry standard two-wire I2C serial EEPROM (ie, the SPD I2C interface and the NVDIMM I2C interface). The base address for the SPD I2C interface is set to standard OxAO, and the base address for the NVDIMM I2C interface is set to OxBO. A 1-bit address offset is applied to the two base addresses to allow the two interfaces to be joined together and interoperate with other modules as needed. That is, the SPD I2C interface and the NVDIMM I2C interface can be implemented as a single physical interface using different address ranges. Controller 110 uses the first 512th byte block in the flash memory that is attached to the first SD/MMC+ interface. The first half of the block is for SPD data and the second half of the block is for flash configuration. Figure 5 shows the functional operation using I2C interface read. Figure 6 shows the work of writing using the I2C interface. 31 201106371 Operation. The debug, maintenance, test and scan module 100 also includes functionality for debugging, maintenance, testing, and scanning. For example, if the controller is implemented using an Altera processor, the Altera JTAG UART interface is a full-featured debug and monitoring interface that allows the user to access firmware functions. With the Altera tool suite, firmware can be monitored and/or overwritten with new firmware for research purposes. Using the built-in UART function, the JTAG interface can be used to emulate a serial interface that allows low speed custom communication. Similarly, for larger FPGA configurations, the firmware can be incorporated into the test user interface to perform diagnostic tests on DRAM and flash memory for testing purposes. The test user interface is also accessed via the UART built into the Altera JTAG interface. During production testing, controller 11A can be reset to allow testing of DRAM 120 and SD/MMC+ flash 130. Therefore, when the controller 110 is held in reset, the FET switch 163 and the FET switch 164 on the DDR interface are maintained in an appropriate state. At the same time, controller 110 tristates the SD/MMC+ interface to allow needle bed testing of flash memory.

The controller 110 has a production test control that controls the firmware to perform production tests on the DDR interface and the SD/MMC+ interface to ensure proper connectivity. The controller 110 reads and writes to the DDR memory device to utilize the address, data, and control signals of the DDR. Similarly, controller 110 passes sufficient data to utilize all signals via SD/MMC+ commands and data busses. As an end-user production test, the NVDIMM I2C 提供 提供 interface provides a mechanism to control standby and restore operations and direct access to flash 32 201106371 and DDR memory. FPGA Architecture Figure 7 shows an example architecture of controller 110 that uses an embedded NIOS processor with an Avalon bus to connect IP blocks together (e.g., if the controller uses Altera) Processor (Altera JTAG) to implement). Changes to Altera's design include another I2C interface (NVDIMM I2C interface) for the new feature structure' updated GPIO and modified firmware. Power Description Module 1 00 power performs many system operations. It produces the voltage rails required by controller 110 and isolates module 110 from the system rail during a power failure. Figure 8 shows the structure of the power supply. During normal operation, transistor Q3 and diode D1 direct system power VDD and V3P3_AUX to the device on module 100. V3P3_AUX is an additional edge connector pin that powers the non-standard device on module 100. VDD is a standard modular power source that includes many edge connector pins. The VMEM is a power rail that supplies power to the module 100 device. The V3P3_AUX voltage rail is converted to the three additional power rails required by controller 110. In general, the V1P2 voltage rail and the VIP8 voltage rail supply most of the controller power, while the V2P5 rail powers the FPGA analog PLL and the V3P3 powers the FPGA digital I/O, oscillator, and SD/MMC+ card. The power loss is approached by the controller 110 via the edge connector signal or via the NVDIMM I2C interface. Once it occurs, controller 11() turns on Q1 and Q4 and turns off transistor Q3 to obtain 33 201106371 power from the EDL capacitor bank, which is connected to VBACK 171 and isolates the module from system power. This power switch has no contacts, such as, for example, the power conditioners ΙΠ, U2, U3, and U4 are configured in this condition to not cause the controller 110 to reset or cause the DRAM 120 to lose data. One way to switch between power supplies is to use a diode switch. Diode D1 prevents, for example, the EDL capacitor voltage from being fed back into the V3P3_AUX supply due to charge sharing between the "decoupled" capacitors on the two tracks. If a transistor is used, the EDL capacitor voltage can cause The power supply has a glitch (one of the capacitors is an EDL capacitor bank). Depending on the type of power loss event, controller 110 may be requested to stop using the EDL capacitor bank and be requested to return to system power. Again, this power switch has no contacts to prevent data loss or short-term pulse waveform interference on the power rail. Module 100 also charges with the VCHRG power supply and monitors the EDL capacitor bank. This voltage rail is specified for charging purposes only, and the module continues to operate normally even when VCHRG is not connected. In order to improve the power efficiency of the EDL capacitor bank, the minimum input power of U3 and U4 can be as low as possible. Because the standby operation must be completed before U3 or U4 reaches its specification limit, the minimum input specification limits the low end of the Fox Capacitor discharge curve. For this reason, the V3p3 regulator (1) is a boost regulator for the self-powered “power supply”, allowing the minimum ship discharge level to be as low as possible.

When the cascading regulator affects the efficiency of the power supply, the V milk and V2P5 are relatively lower power than the power supply. The power loss due to the lower minimum discharge S 34 201106371 level 'cascade V3P3 regulator m is significantly lower than the improved EDL capacitor bank efficiency. Decreasing iv in the minimum EDL capacitor bank voltage yields an improvement of 1 〇〇/0 in total system power, while cascading V3P3 regulator U1 represents a roughly 3% reduction in efficiency of the V3P3 power rail only (which is roughly total) 5% - 〇% of system power). The system in Figure 1 supports a different number of SD/MMC+ memories.

Four configurations of the DRAM device of the device. Each configuration has a different pCB layout that allows the power supply design to be adjusted to support different loads. The power supply is designed to handle 7 (cb) temperatures without forced airflow. The components used for power supply design are located on one side of the PCB and have a maximum squareness of 4 mm. The power supply uses only 3 吋χ 1 板 of board space. The space includes any heat sink. The VDD system rail is excessively high so that the voltage drop at the transistor Q3 does not cause the VMEM supply to exceed the downstream device range. The voltage drop of the Q3 transistor voltage drop is already at any percentage. Select the value to choose 'but better performance is needed. The regulators shown in the figure are functional and can be combined into a multi-output regulator device. All voltage rails have monitors ("pG" signals), etc. The monitor can be combined with the regulator or combined into a single device. The monitor is separate, because the v3p3 monitor monitors the V3P3 rail when ν3Ρ3—the rail is the power source. If the VCHRG is not supplied, the V3P3 regulator does not operate. But this is not an error, because the module must still be held and operated only (see Figure 2 and Figure 3). In order to increase the storage efficiency of the EDL capacitor, the most regulator The small allowable input voltage should be ▲ 35 201106371 may be low. The following table provides additional information about the regulator. Regulator minimum input maximum input note U1 V3P3 1.8V VBACK 1 &gt; 2 &gt; 3 U2 V2P5 2.8 V VBACK 3 U3 V1P8 2.8 V VBACK 3 U4V1P2 2.8 V VBACK 3 Notes: 1. The closest headroom of all regulators and limits the performance of the EDL capacitor bank. 2. Low quiescent current requirement when the regulator is idle during normal operation (capacitive load). Based on the configuration specifications. See the section on voltage rails for specifications. Since the power consumption is still an estimate, devices that are close to the current specifications should be studied. The power transistor is responsible for moving the DRAM device to the standby power and making the standby power System power VDD and V3P3_AUX are isolated. Capacitor charger U6 handles power loss and prevents EDL capacitor bank from being discharged back through the charger. Transistor Q3 and transistor Q4 are η-channel MOSFETs and are controlled by FPGA, which uses 3.3V control signal shift In addition to the need for high-side drivers, transistor Q1 is a ρ-channel MOSFET directly controlled by the FPGA or has a high-side drive Η-channel MOSFET (VCHRG power supply or VCΑΡ power supply cannot be used normally, Γ

Unless the module continues to operate without such power supplies). In the table below, the current from A 36 201106371 has a certain over-spec design tolerance, so a transistor close to this specification can also be used in this example design. During the power loss event, the transistors operate only until the EDL capacitor bank is discharged (e.g., a maximum of about 2 minutes). Transistor Maximum VDS Maximum IDD On Resistor Q1 12 V 2700 mA 0.020 ohm 1 Q3 1.8 V 4000 mA 0.009 ohm 2 Q4 1.8 650 mA 0.056 ohm 2 Notes: 1. Low power supply specification and supply voltage based on VCAP (2.8v) 2% tolerance. 2. Based on the low power supply current specification of the power supply and the 2% tolerance of the power supply voltage. EDL Capacitor Thunder Returning to Figures 2 and 3, the EDL capacitor 210 or backup battery 31 connected to VBACK 171 is external to the module ι because it is physically large and temperature sensitive. The long-term life of EDL capacitors and batteries is sensitive to ambient temperature and the operating voltage of the capacitor. For this purpose, the operating voltage has been chosen such that the capacitor will withstand less than 5 〇. The surrounding area/m degree is at least 1 year. In general, the backup power is located near the air intake or near another relatively cool location within the chassis. The standby controller 220 performs a periodic health check on the alternate power source to determine if the power is no longer sustainable and reports status via the NVDIMM I2C interface. Long-term life of EDL capacitors shows the relationship between temperature and operating voltage. 2 201106371 For aluminum capacitors, the temperature is usually reduced by 10 times per 10 °C. Also like an aluminum capacitor, this capacitor is sensitive to the operating voltage index. Maxwell Technologies uses a thermal-non-thermal (T-NT) model to model the life of a PC 10 capacitor in hours. L(V,T) 4.89015-06 F79838 exp(- 9385.8, T ' where T It is the Kay temperature and V is the operating voltage in volts. This model assumes that the capacitor has been reduced by 20% from its initial value at the end of the capacitor life. Many different operating environments are presented in the table below to demonstrate the expected PC 10 capacitance is Destiny. Description Temperature °c Voltage Operating Life Year Room Temperature 25 2.50 18 Surrounding (High Voltage) 40 2.50 3.9 Surrounding (Reducing Voltage) 40 2.20 11 Operation (High Voltage) 50 2.50 1.6 Operation (Reducing Voltage) 50 1.95 11 Server ( High voltage) 60 2.50 0.7 Servo (lower voltage) 60 1.75 11 Servo (high voltage) 70 2.50 0.3 Servo (reduced voltage) 70 1.60 10 As shown in the figure, these capacitors operate at low operating voltage, the effect Structure of the voltage regulator. In a parallel configuration, the total capacitance is the sum of all * 38 201106371 containers. However, the discharge current is large for a small voltage swing during use. The voltage regulator requires a boost switch mode power supply architecture with a current inductor. In a series configuration, 'total capacitance is the reciprocal of the sum of the reciprocals of the capacitance' but the total operating voltage has increased. The problem involves making the capacitance between The operating voltage is balanced and the number of capacitors is kept reasonable. For the purpose of design exploration, 5 (TC operating temperature is selected, which allows a ten to use 75% of the electric barn operating voltage for a life of 10 years. This allows Exceeding the common external temperature of the enterprise computer in the server room, the external temperature of 15 °c rises at a temperature of 15 ° C. The other target environment will be a telecommunications NEBS standard with a maximum ambient temperature of 4 ° C, the maximum ambient temperature can be During the short-term HVAC failure, it is added within the equipment frame to an ambient temperature of 50 ° C with a temperature of 5. The temperature of each short-term temperature failure is defined by two to 96 hours 'but not more than one day per year. The figure shows an external ED capacitor back-up power architecture, which is a more detailed version of Figure 2. Some embodiments provide a capacitor charger, for example, to implement constant current, constant current Designed capacitor bank charger. The charger applies a constant current to the capacitor bank until the capacitor bank reaches its final full charge voltage. At that time, the charger applies a constant voltage to float the capacitor bank. This floating voltage is due to the fact that the EDL capacitor has a relatively large leakage current that requires the balancing resistor within the capacitor bank to be biased to ensure that all capacitors within the capacitor bank have equivalent charging voltages. Since the size of the capacitor bank can be optimized for each configuration, the floating voltage can be programmed by the 'resistor and accurate i丄0/. . The float voltage can be set from vCHRG (minus 39 201106371 to a headroom) to 6 volts. The design can utilize LiOn battery charger technology (usually a single-ended primary inductor converter or SEPIC architecture), but other techniques can be used. Some chargers require a small processor to monitor the charge cycle and switch the charger from constant current operation to constant voltage operation. For these designs, the processor within controller 11 can be used depending on the complexity of the algorithm and the hardware connectivity to the charger design. The following table provides information related to VCHRG and VCAP. Power Supply Name Rated Voltage Accuracy Annotation VCHRG 12 V +/- 5% 1 VCAP 11.5 V +/-1% 2 Notes: 1. Depending on the system, for example, in some embodiments, a wider power range may have advantage. 2. The nominal floating voltage of the capacitor bank. During the discharge cycle, the regulator continues to operate until the capacitor bank discharges to 2.8V or lower. Power Name Minimum Current Maximum Current Note VCHRG 500 mA 1 VCAP 100 mA 2700 mA 2 Notes: 1. Based on an example customer specification, the charger will not exceed the maximum specifications under all conditions. 2. Based on U1 operating at 70% efficiency, U3 operating at 80% efficiency, and U4 operating at 90% efficiency, VCAP operating at 2.8V (lower operating range 40 201106371) has a 2% Loss. The described embodiments also include a health status monitor for the backup power source. EDL capacitors have a limited lifetime. This lifetime is sensitive to the number of operating voltages, ambient or storage temperatures, and charge/discharge cycles (wear). In some applications, 'only the operating voltage and ambient temperature are important. For example, if the number of prediction cycles is 100 times smaller than the specification, the EDL capacitor's life is based on the capacitance reduced to a specified threshold (in most Under conditions, 'from a 30% drop in initial capacitance' or an increase in the ESR of a specified threshold (depending on the manufacturer, from 30% to 100% of the initial ESR). Assuming the sensitivity of the EDL capacitor to stress, the controller monitors the health of the capacitor. The health status monitor Uu (Fig. 9) can be combined with the charger U6 depending on the implementation. If the capacitor bank is charged enough to handle power loss, the health monitor will notify FPGa. In general, the charger U6 must be able to "break" during the test. In the embodiment with many series capacitors, the voltage at each capacitor can be monitored and sent to the signal. The backup power supply I2C busbar is checked. This allows identification of the specific capacitor that has failed and indicates that the backup power source has all failed. Measurement self-energization (applying VCHRG power) to provide an estimated capacitor when VCAP reaches full charge state One of the health status of the group. The controller 110 can report whether the module 1 can handle the power loss event. If the capacitor bank never reaches a fully charged state, the system detects the situation and announces an error. To measure the valley, fully charge the battery. First, turn off the charger 41 201106371 and apply a known load (resistor) to the capacitor bank for a certain period of time to slightly discharge the capacitor. In general, The load current is too small to prevent the ESR impact measurement. If the VCAp power supply falls below a fixed voltage, then the measurement method can be The voltage comparator that triggers the interrupt on control $11〇 is simple. If the interrupt is triggered during the test, the capacitor is too low and the capacitor bank fails the test. One problem is that the power^ event may be just right (4) This happens later, so partially discharge the capacitor, which must be considered within the energy budget. To minimize the cost of the EDL grid power supply, self-test intelligence is located on the module 110. To control the logic in the power supply, Using an I2Ce to a GPIO expander device, therefore, the controller can control and monitor the signal on the standby power module (eg, 2 or). As discussed, in some cases, it may be preferable to select a battery. EDL capacitors are chosen because batteries have a higher energy density than EDL capacitors and therefore require less volume and quality. For example, a single A123 battery has a current rating of 23 Ah at 3.3 V, weighs 7 gram and requires 2 cubic pairs. If the module 100 requires 5 watts for 2 minutes, the required energy is only 〇-〇5Ah, which exceeds the order of magnitude of the battery capacity. For portable laptops Most battery chargers in the brain have all the necessary functions required for backup power. In addition, most of these devices have an integrated I2C interface for monitoring, configuration, and control that can be used by the module.格戎. In a single SD/MMC + card operation, the first block of the SD card (bytes to the current group 511) is used for SPD and flash configuration purposes. sd_^ 42 201106371 remaining area The block is for alternate data. During the standby operation, the spare data is streamed from the first DRAM device in a continuous byte stream and written into a single flash memory. The standby controller then repeats the other DRAM device. The process continues until the standby of all other devices is completed. During the restore operation, the data is streamed from a single flash memory in a continuous byte and written to the first DRAM device. The standby controller then repeats the process for the other DRAM devices until all other devices have completed. The standby controller stream uses a single continuous read/write operation = reads and writes data to the flash memory. This mechanism allows the sd card to be executed at the maximum bandwidth, but it has a side effect, that is, if the length of each (10) Zhao backup video broadcast is not a multiple of the 512-bit S group, the per-dram backup video file arrangement It may exceed the boundaries of the SE) card block. For dual SD/MMC + card operations, the first block of the card in the slot (bytes to bytes) is used for SPD and flash configuration purposes. Not used in the slot! The other block in the card is the first block of the card and is ignored. During the standby operation, the data is streamed from the first DRAM device in a continuous byte stream and simultaneously written to the two flash memories. The data stream is split into two flash write data streams by sending all even bytes to slot G and sending all odd bytes to the slot: The standby controller then repeats the process for the other devices until all DRAM devices have finished. During the restore operation, data is read from the two flash memories, which are interleaved by the tuples to form a stream of data that is written to (10). The controller repeats the process with the controller until all devices are completed at 43 201106371. The standby controller stream reads and writes data to the flash memory for each SD card using a single continuous read/write operation. This mechanism allows the SD card to execute at the maximum bandwidth', but it has the side effect that if the length of each DRAM backup image file is not a multiple of i, then the arrangement of each dram backup image file may exceed the SD. The boundary of the card block. For four-wire SD/MMC + card operation, the first block of the sd card (bit group to byte 511) in the slot is used for SPD and flash configuration purposes. The first block of another SD card in slot 1 is not used and is ignored. During the standby operation, the data is streamed from the first DRAM device in a continuous byte group and simultaneously written to all of the flash memory. The data stream is divided into four flash write data streams by sending every 4 bytes to an interface. The standby controller then repeats the process for other devices until all DRAM devices are completed. During the restore operation, data is read from two flash memories that are serially interleaved via a byte to form a single stream of data written into the first DRAM for combination. The standby controller then repeats the process for the other dram devices until all devices are completed. The standby controller stream reads and writes data to the flash memory for each SD card using an early one continuous read/write operation. This mechanism allows the SD card to be executed at the maximum bandwidth, but it has the side effect that if the length of each DRAM backup image file is not a multiple of 2 kilobits and 70 groups, the arrangement of each DRAM backup image file may be Exceeds the boundary of the SD card block.

The table below provides the worst case write/read frequency for each SD/MMC card and for each MMC + +^S 44 201106371 using 20 megabytes/second and 40 megabytes/second Width calculated instance backup time. This calculation also includes the worst case SD/MMC+ write interval used to update the flash configuration. NYDIMM size total data one SD/MMC effective interface (20 megabytes/sec) Two SD/MMC effective interfaces (40 megabytes/sec) Four MMC+ effective interfaces (160 megabytes/ Seconds) 256 million bytes 288 million bytes 15 seconds 8 seconds 2 seconds 512 million bytes 576 million bytes 30 seconds 15 seconds 4 seconds 1 billion bytes 1152 million bytes 58 seconds 30 seconds 8 seconds 2 billion bytes 2304 million bytes 116 seconds 59 seconds 16 seconds pre-burning self-test operation DIMM 100 also includes self-test functionality. The self-test can be triggered by using the PRODTEST input on the FPGA and via the NV I2C interface. The results of the self-test are stored permanently until the flash memory is erased via another self-test sequence. In one example, self-test: receive DDR interface (FET switch off); set the SELFTEST test bit high in progress; fill DRAM memory with 0xA5; fill flash memory with 0x00; turn on progress LED; The DRAM memory is spared to the flash memory; the DRAM memory is filled with 0x00. ^ 45 201106371 The DRAM memory is restored from the flash memory; the content of the DRAM memory is tested; and if an error is detected, an error LED is set and Store the results in a flash. If no errors are found, the process returns to fill the flash memory with 0x00. The self-test method can be defined by various users of the system of Figure 1, for example, the methods can be defined by the customer. Visual Indicators Especially when multiple modules are used within a system, the visual indication on the board allows for the diagnosis of system problems with the memory module. Under the following conditions, the slow flash of an LED is 0.2 5 seconds on and 1 second off, and the fast flash of one LED is 0.5 second on and 0.5 second off. The memory module has LEDs to indicate that alternate operations are occurring. Assuming that some configurations take many minutes to complete the standby operation, the LED indicates to the service technician that the module 100 or capacitor bank must be undisturbed after the power loss event. Red LED Description Disconnect System power and capacitor power are disconnected or the memory module is operating normally ("Power On" or "Idle" state). If the system power is off, the memory module and/or the capacitor bank can be disconnected. Slow flash The "Reset" operation (flash to DRAM) operation is in progress. Fast flash "The standby j operation (DRAM to flash) operation is in progress. On The restore operation is completed, waiting for the DRAM to be cleared before switching to "idle j"

A visual indication is provided to the backup power source to indicate that the backup power is properly connected, charged, fully charged, or disabled. For example, this may be useful in systems having multiple modules 100, and it is possible that a service technician must physically identify a failed module or capacitor for replacement. Green LED Description Disconnect No backup power is connected or the module is turned on. Slow flash Backup power is charging" Fast flash Backup power fails self-test" On The backup power is fully charged. Vision is also used during the burn-in test. JLtU 〇 If any of the self-defense brothers fails during the burn-in test, the red LED is locked. To demonstrate that the self-test is in progress, the green LED will flash during the self-test. When the test is in progress, the green LED triggers at the end of each test cycle (write/read DRAM and resume flash memory). • For example, external systems can include various types of systems, such as hosts, servers, clients, and networks of various systems. The volatile memory 120 may include, for example, dynamic random access memory (DRAM), Z-RAM®, static random access memory (sr R: TTRAM), and the like. The idiosyncratic '«1 material includes (for example, only a memory (ROM), a flash memory, a ferroelectric programmable metallization unit (ρΜΓ, 疋 疋 [PMC], etc.). In some embodiments, The backup power supply 200 can include a DIMM, and in other embodiments, the backup power supply 2〇〇TA fjvon, for example, an external device. Non-volatile memory 130 and volatile r&gt; The hidden body 120 can be of various sizes and does not have to be ': 47 201106371 is the same size. During the standby operation, various embodiments can move all the data stored in the volatile memory 120 to the non-volatile memory 13 or store it in A subset of the data in the volatile memory 120. The same is true during the recovery operation from the non-volatile memory uo to the volatile memory 12〇. Some embodiments of Figure 1 do not include the i-th image. Each component and/or function. For example, some embodiments do not include isolation logic 140. Some embodiments do not store SPD information in volatile memory 120, and some embodiments store volatile memory. Simultaneous shift of all data in volume 12〇 To non-volatile memory 〇3〇 (eg, all DRAM devices at the same time)' and some embodiments move the data stored in volatile memory 120 to non-volatile memory 13〇, eg, ' The next DRAM device. The controller 11 can be implemented, for example, using various FPGAs, controllers, processors, and/or memories. In another embodiment, the non-volatile controller 11 is a special application integrated body. An integrated circuit (ASIC) that includes a flash chip interface inside the controller. By incorporating the flash die interface into the controller, the external SD/MMC+ controller will not be used and the save/restore performance can be improved. In an embodiment, the volatile memory i2 can be divided into various segments by using various start addresses and end addresses. The addresses can be set by the NVDIMMI2C bus set controller 11 To configure, which segments (and in what order) of the address definitions should be spared and/or restored can also be controlled by setting the register in the controller 11" although the invention has been In the above illustrative embodiment, T. The description and illustrations are to be understood as being limited to the details of the details of the embodiments of the present invention, and the spirit of the present invention may be made without departing from the spirit and scope of the invention. The scope is only limited by the scope of the following patent application. [Simple diagram of the diagram] Figure 1 is a block diagram of a two-line memory module (DIMM). Figure 2 is a block diagram of a capacitor-based backup power supply. It can be used to power the components of Figure 1 in the event of a power failure. Figure 3 is a block diagram of a battery-based backup power supply that can be used to power the components of Figure 1 in the event of a power failure. Figure 4 is a block diagram showing an example state and transition of the mMM illustrated in Figure i. Fig. 5 is a timing chart showing various read operations of the internal integrated circuit (I2C) interface of the mMM illustrated in Fig. i. Fig. 6 is a timing chart showing various write operations of the internal integrated circuit (I2C) interface illustrated in Fig. 1. Figure 7 shows the architecture of the DIMM illustrated in Figure 1. The 8th exhibition does not need to be powered in the first! The architecture of the power source for reading as illustrated in the figure is a more detailed illustration of the backup power supply of Figure 2. [Main component symbol description] 100 dual-line memory module (DIMM) Γ 49 201106371 105 interface 110 controller 115 FPGA programmable read-only memory 120 volatile memory 121 DRAM chip 122 DRAM chip 130 non-volatile memory 131 Flash chip/flash device 132 flash device 140 isolation logic 150 signal

161 PLL 162 Register 163 FET Bus Switch / FET Multiplexer 164 FET Switch / FET Multiplexer 170 Interface Line / Signal

171 VBACK 200 Backup Power / Standby Power Source / Standby Power Module 210 EDL Capacitor 220 Standby Controller / Charger & Monitor 300 Backup Power Module 310 Backup Battery 201106371 Q3 Transistor Q4 Transistor U1 Power Regulator Ull Health Status Monitoring U2 Power Regulator U3 Power Regulator U4 Power Regulator U6 Charger 51

Claims (1)

201106371 VII. Patent application scope: ι_ A memory device used together with a main power source, the memory device comprising: a volatile 14 3 memory, comprising a plurality of memory portions, wherein the plurality of memory portions Each having a normal operating state and a low power state; an interface for connecting to a standby power source configured to temporarily supply power after a power loss from one of the primary power sources occurs The volatile memory; a non-volatile memory; and a controller that communicates with the volatile memory and the non-volatile memory and is programmed to detect a power loss of the primary power source and responds For the power loss, the data is moved from the volatile memory to the non-volatile memory in at least one memory portion at a time, and when the data is moved from the volatile memory to the non-volatile memory, Putting the portions of the memory that are being removed from the data into a normal operating state' and placing the portions of the memory that are not being removed from the data Power state. 2. The memory device of claim 1, further comprising a device ready output and wherein the controller is further programmed to: (a) determine whether the alternate power source is from the volatile memory Moving to the non-volatile memory during the movement has sufficient power to supply power to the memory device; [52 201106371 (b) determining whether the non-volatile memory is ready to receive the data stored in the volatile memory; Based on (a) and (b), the device ready output is driven. 3. The memory device of claim 1, wherein the movement of the data from the volatile memory to the non-volatile memory and the control of the state of the portion are based on moving the data to One of the rates in the non-volatile memory. 4. The memory device of claim 1, wherein the volatile memory is a dynamic random access memory, the portions are dynamic random access memory chips, and the low power state is self-renewed. . 5. The memory device of claim 1, wherein the non-volatile memory comprises electronic erasable programmable read only memory (EEPROMs). 6. The memory device of claim 3, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 7. The memory device of claim 1, wherein the power from the alternate power source is derived primarily from a capacitor. 53 201106371 8. The memory device of claim 1 wherein the power from the alternate power source is primarily from a supercapacitor. 9. The memory device of claim 1, further comprising an output health signal and a health status monitor, the monitor monitoring a health status of the standby power source, and the standby power source does not have sufficient power The output health signal is driven in the case of providing standby power. 10. If you apply for a patent scope! The memory device of the item, wherein the controller is further programmed to detect power restoration of one of the primary power sources, and in response to the power restoration, moving data from the non-volatile memory to the volatile memory. 11. The memory device of claim 3, wherein the non-volatile 3 memory is comprised of four flash memory chips. 1 Δ detecting a power failure of one of the main power sources of a volatile memory, the active memory comprising a plurality of memory portions, each of the plurality of memory segments having a normal operating state and a low Power state; in response to detecting the power failure and when the volatile memory is powered by a spare rate source: moving the data stored in the volatile memory to at least one memory portion at a time Volatile memory; and 54 201106371 Although the data is moved from the volatile memory to the non-volatile memory, the memory portion of the data being removed is placed in a normal operation state t and the memory that is not being removed from the data is stored. Part is placed in a low power state. 13. The method of claim 12, further comprising the steps of: (a) determining whether the alternate power source has sufficient power during the movement of the data from the volatile memory to the non-volatile memory Powering to the volatile memory; (M determining whether the non-volatile memory is ready to receive the data stored in the volatile memory; and driving a device ready output based on (a) and (b). The method of claim 12, wherein the step of controlling the movement of the volatile memory from the volatile memory to the non-volatile memory and the controlling of the states of the portions are based on moving the data to the non- The method of claim 12, wherein the volatile memory is a dynamic random access memory, and the portion is a dynamic random access memory chip. 'And the low power state is self-renewed. 16. The method of claim 2, wherein the non-volatile record 55 201106371 contains an electronic erasable program The method of claim 12, wherein the power from the backup power source is mainly from a capacitor. 18. The power of the backup power source is mainly from a supercapacitor. The steps include the following 19. The method of claim 12, wherein the method further improves: monitoring the health status of the standby power source; and having insufficient power to provide backup in the standby power source In the case of power, an output health signal is driven. 2〇. The method of claim 12G further includes the steps of: detecting power recovery of one of the primary power sources; and responding to the power recovery from the non-volatile material The memory moves to the volatile memory. 21. A memory device for use with a primary power source, the memory device comprising: a volatile memory comprising a plurality of memory segments, the plurality of The memory segment is defined by at least one start address and a corresponding at least one end bit 56 201106371; an interface, Connected to an alternate power source configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; a non-volatile memory; and a controller, Communicating with the volatile memory and the non-volatile memory and programming to detect a power loss of the primary power source, and responding to the at least one start address and the at least one end address The data device is moved from the volatile memory to the non-volatile memory. 22. The memory device of claim 21, wherein there is only one at least one start address and only one at least one end a location, wherein the movement of the data from the volatile memory to the non-volatile memory comprises moving only the volatile memory stored at an address between the start address and an end address Information. 23. The memory device of claim 22, wherein the information stored in the volatile memory at the address between the start address and an end address is at least in the key data and the directory data. One. 24. The memory device of claim 22, wherein the data in the volatile memory that is not stored at the address between the start address and an end address is executable data. [57201106371 25. The memory device of claim 22, wherein the controller is further programmed to detect one of the primary power sources and respond to the power restoration: the erasure is not at the start address a segment of the volatile memory with an end address; and moving the data from the non-volatile memory to a region of the volatile memory between the start address and an end address segment. 26. The memory device of claim 25, wherein the erasing comprises zeroing. This movement was performed before. 28. The scope of the patent application includes: - address memory, which uses the memory device of the item 2!, which further includes an end address; and it is used to store the at least one start address and the The at least one ending address. 29. The memory device of claim 28, wherein the address 58 201106371 memory comprises a register, the configuration data bus comprising an inter-integrated circuit (I2C) bus bar and This access contains both read and write. 30. The memory device of claim 21, wherein the non-volatile memory comprises electronic erasable programmable read only memory (EEPROMs). 3. The memory device of claim 21, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 32. The memory device of claim 2, wherein the power from the alternate power source is primarily from a capacitor. 33. The memory device of claim 21, wherein the power from the alternate power source is primarily from a supercapacitor. 34. A method comprising the steps of: detecting a power failure of a primary power source of a volatile memory, the volatile memory comprising a plurality of memory segments, the plurality of memory segments being at least one a start address and a corresponding at least one end address definition; and 回应 in response to the Russian test of the power failure and when powered by a backup power source to the 59 201106371 hair memory: based on the at least one start address And storing at least one end address to move the data stored in the volatile memory to a non-volatile memory. 35. The method of claim 34, wherein there is only one at least one start address and only one at least one end address exists, and wherein data is moved from the volatile memory to the non-volatile memory The step of moving includes moving only the data in the volatile memory stored at the address between the start address and an end address. 36. The method of claim 35, further comprising the steps of: (d) power recovery of the primary power source and in response to the power restoration: the erasure is not between the start address and an end address And a segment of the volatile memory; and moving the data from the non-volatile memory to the segment of the volatile memory between the start address and an end address. ^ 37. The method of claim 36, the method of claim 36, wherein the erase includes at least one of the volatile memory stored in the same location, and wherein Non-^ 38. If the information between the starting address and the ending address of Article 35 of the patent application scope is the key information and catalogue information 60 201106371 is stored in the initial position III- a method of volatilizing 34 items at an address between the bundle addresses, which further comprises the following 39. The first step of the patent application scope is based on the method of receiving an input from a master system, i.e., from the host system I2C busbar. 41. A device comprising: a non-volatile memory; a controller communicating with the non-volatile memory, wherein one of the main power sources of the controller is programmed to be one of a volatile memory After the loss occurs, the data is moved from the volatile memory to the non-volatile memory; and a backup power source is temporarily supplied to the controller and the volatile memory after the power loss of the main power source occurs. The backup power supply includes: a capacitor bank having an output terminal; a voltage source connected to the voltage source to charge the capacitor bank to a normal operating voltage; and a health status monitor programmed to be based on the A voltage at the output terminal of the capacitor bank generates a fault signal. 61 201106371 42. The memory device of claim 41, wherein the health monitor is further programmed to: interrupt the voltage source to charge the capacitor bank; when the charging is interrupted, the capacitor Applying a predetermined resistance to all of the output terminals of the group for a predetermined period of time; monitoring the wheel terminal of the capacitor bank during the predetermined period to determine whether the voltage at the output terminal falls below a predetermined threshold voltage; The fault signal is generated if the voltage at the output terminal falls below the predetermined threshold voltage within the predetermined time period. 43. The memory device of claim 42, wherein the predetermined resistance and the predetermined time are determined to maintain the electrical dust of the output terminals of all of the capacitors to a necessary operating voltage. 44. The memory device of claim 41, wherein the capacitor bank comprises a plurality of capacitors in parallel. 45. The memory device of claim 44, further comprising a capacitor level terminal at each of the plurality of capacitors, and wherein the health monitor is further programmed to be based on the The voltage at one of the capacitor level terminals generates the fault signal. 62 201106371 46. The memory device of claim 4, further comprising: a processor that communicates with the volatile memory and a permanent storage system, wherein if the controller generates the fault signal, The processor is programmed to move the data from the volatile memory to the permanent storage system. 47. The memory device of claim 46, wherein a hard disk is included in the permanent storage system. 48. The memory device of claim 41, wherein the volatile memory comprises a dynamic random access memory. 49. The memory device of claim 41, wherein the non-volatile memory comprises an electronic erasable programmable read only memory (EEPR 〇 Ms) 〇 5 〇. The memory of claim 41 The device, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable inter-array (FPGA). 5I. The memory device of claim 41, wherein the controller is further programmed to move data from the non-volatile memory to the volatile memory after power recovery of one of the primary power sources occurs: 63 201106371 52. The memory device of claim 41, wherein the controller communicates with the backup power source via a configuration data bus. 5: The memory device of claim 41, wherein the configuration data bus is an I2C bus. 54. A method comprising the steps of: interrupting a voltage source to charge a capacitor bank, the capacitor bank being configured to provide temporary power to a controller, the controller being programmed to be in a volatile memory After a power loss occurs in one of the main power sources, the data is moved from the volatile memory to a non-volatile memory, and the power is supplied to a volatile memory after the power loss of the main power source occurs; When the charging is interrupted, applying a predetermined resistance to all output terminals of the capacitor bank for a predetermined period of time; monitoring the output terminal of the capacitor bank during the predetermined period to determine whether the voltage at the output terminal falls to a predetermined period Below the voltage limit; and if the voltage at the output terminal falls below the predetermined threshold voltage within the predetermined time period, a fault signal is generated. 5. The method of claim 54, wherein the predetermined resistance and the predetermined time are determined to maintain the voltage of all of the output terminals of the capacitor above a necessary operating voltage. The method of claim 54, wherein the capacitor bank comprises a plurality of parallel capacitors. 57. The method of claim 54, wherein a capacitor level terminal is present at each capacitor of the plurality of capacitors, and the method further comprises the step of: based on any one of the capacitor level terminals One of the voltages generates the fault signal. 58. The method of claim 57, wherein the fault signal indicates which of the plurality of capacitors has failed. 59. The method of claim 54, wherein the non-volatile memory comprises an electronic erasable programmable read only memory (EEpR〇Ms). 60. The method of claim 54, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a field programmable closed array (FPGA). 61. A device comprising: a volatile memory; or a plurality of non-volatile simon memory wafers, each of which is for storing data transferred from the volatile memory; an interface for connecting To the standby power source, the standby power rate source passes. 65 201106371 configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; the controller communicates with the volatile memory and the non-volatile memory, wherein: the controller Stylizing to move data from the volatile memory to the non-volatile memory wafer after a power loss of the primary power source of the volatile memory occurs; and storing the parameter describing the volatile memory In at least one of the non-volatile memory chips, the non-volatile memory chips store the data moved from the volatile memory. 62. The memory device of claim 61, wherein the parameter comprises sequence presence detection information. 63. The memory device of claim 61, wherein the parameter describes a size of the volatile memory. 64. The memory device of claim 61, wherein the parameters describe a velocity of the volatile memory. 65. The memory device of claim 61, wherein the control comprises a cache memory for storing one of the parameters. 66 201106371 66. The memory device of claim 61, further comprising a configuration data bus for accessing one of the parameters. 67. The memory device of claim 61, further comprising a configuration data bus for accessing one of the parameters, wherein the controller further comprises a cache memory for storing the one of the parameters And wherein the controller is further programmed to read the parameters from the cache memory in response to receiving a request for one of the parameters via the configuration data bus. 68. The memory device of claim 61, wherein the volatile memory comprises a dynamic random access memory. 69. The memory device of claim 61, wherein the non-volatile simon memory wafer comprises an electronic erasable programmable read only memory. 70. The memory device of claim 61, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 71. The memory device of claim 61, wherein the controller is further programmed to generate power recovery at one of the primary power sources _ moving data from the non-volatile memory wafer to the volatile memory. 67 201106371 72. The memory device of claim 61, wherein the power from the alternate power source is derived primarily from a capacitor. 73. The memory device of claim 61, wherein the power from the alternate power source is primarily from a supercapacitor. 74. A method comprising the steps of: after a power loss of a volatile memory-main power source occurs, ie, when the volatile memory is temporarily powered by the backup power source, the base 2 is stored in a parameter of the at least one of the non-volatile memory chips, the non-volatile body W is stored from the volatile memory, and the data is moved from the volatile memory to the And other non-volatile memory a + hidden corpus, each of which is used to store the movement from the volatile memory, wherein the parameters include therein Parameter Description 75. The detection sequence exists in the method sequence as set forth in claim 74. 76. The method of claim 74, wherein the volatile memory is one of a size. 68 201106371 The method of claim 74, wherein the parameters describe the velocity of the volatile memory. 78. The method of claim 74, further comprising the step of moving data from the non-volatile simon memory wafer to the volatile memory after power recovery of one of the primary power sources occurs. 79. The method of claim 74, wherein the power from the backup power source is derived primarily from a capacitor. 80. The method of claim 74, wherein the non-volatile memory chips comprise electronic erasable programmable read-only memory. a memory device comprising: a volatile memory; ........... τhe, 咏 dual-use nascent huahua is not configured to supply power after a power loss occurs in one of the main power sources To a speech memory; a non-volatile memory; a first configuration data bus 'which is used to access parameters describing the primary permanent characteristics of the volatile gas; a second configuration data bus' Accessing the alternate power source. At least one of the status information of the state information and the state information of the memory device, the first configuration data bus and the second configuration data bus $69 201106371, a same busbar protocol; the controller, and the first a configuration data bus, the second configuration data bus, the volatile memory, and the non-volatile memory communication, • the control is programmed to detect a power loss of the primary power source and respond to the Power loss moves data from the volatile memory to the non-volatile memory, wherein the first configuration of the controller is at least readable or at least writable via the first configuration data bus; At least one of the health status information and the status information is at least readable or at least writable via the first configuration data bus. 82. The memory device of claim 8, wherein the health status information includes a state of the power source. The status indicates that the standby power source is at least one of a charged state, a discharged state, and a charged state. 83. The memory device of claim 81, wherein the health status information indicates whether any capacitor including the backup power source has failed. 84. The memory device of claim 83, wherein the health status is The information indicates which of the capacitors containing the alternate power source has failed. 85. The memory device of claim 81, wherein the health 70 201106371 status information indicates one of the alternate power sources. 86. The memory device of claim 85, which may be a capacitor or a battery. 87. In the memory device of claim 81, the status information indicates that the non-volatile memory is at least one of a write state, an erased state, a positive erase state, and a bad state. 88. The memory device of claim 8 wherein the status information includes header information of the non-volatile memory. 89. The memory device of claim 81, wherein the status information includes a number of bad memory blocks, a number of spare memory blocks, a number of completed download cycles, and a last download. At least one of an error correction code (ECC) error, a number of ECC errors in a final restoration, a state of a last download, and a state of a final restoration. 90. The memory device of claim 81, wherein the volatile memory comprises a dynamic random access memory. 91. The memory device of claim 81, wherein the non-volatile memory comprises an electronic erasable 玎 stylized read only memory 71 201106371 (EEPROMs). 92. The memory device of claim 81, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 93. The memory device of claim 81, wherein the controller is further programmed to move data from the non-volatile memory to the volatile memory when power recovery of one of the primary power sources occurs. 94. The memory device of claim 81, wherein the same busbar agreement is an I2C busbar agreement. 95. The memory device of claim 81, wherein the first configuration data bus and the second configuration data bus include an entity I2C bus bar and wherein the first configuration data bus and the first The second configuration data bus uses different address ranges. 96. The memory device of claim 8, wherein the parameter comprises sequence presence detection information. 97. A memory device for use with a primary power source and a standby power source, the memory device comprising: ^ a volatile memory; [; 72 201106371 an interface for connecting to an alternate power source The standby power source is configured to temporarily supply power to the volatile memory after a power loss from one of the primary power sources occurs; ^ a plurality of turns, each of which is adapted to receive a corresponding different non-volatile a memory chip; a plurality of interfaces, each of which is configured to communicate with any non-volatile memory connected to the other via a different one of the plurality of turns; a controller programmed to Selecting an optional set of the plurality of interfaces based on which ones will receive the non-volatile memory chip, wherein the controller is also programmed to move data from the volatile memory to the connection via the selected interfaces Any non-volatile 隹5 memory of the optional set of interfaces to react to power loss from one of the primary power sources. 98. Memory device as claimed in claim 97. Wherein the volatile memory "size of a one billion and the 4-tuple (iv) Li is programmable to activate via four ports. 99. The memory device of claim 97, wherein the plurality of interfaces comprise four interfaces, wherein two of the four interfaces are connected to a non-volatile memory chip, and wherein the controller is programmed To initiate the connection to the two interfaces of the non-volatile memory chip. 1〇°. The memory device of claim 97, wherein the 73 201106371 volatile memory comprises electronic erasable programmable read only memory (EEPROMs). 101. The memory device of claim 97, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 102. The memory device of claim 97, wherein the power from the alternate power source is derived primarily from a capacitor number. 103. The memory device of claim 97, wherein the power from the alternate power source is primarily from a supercapacitor. 104. The memory device of claim 97, wherein the controller is further programmed to self-link any non-volatile material of the selectable set of interfaces to the interface after power recovery of the primary power source occurs. The memory moves to the volatile memory. 105. The memory device of claim 97, wherein each of the plurality of turns comprises a hole, pad or terminal area of a printed circuit board. 106. The memory device of claim 97, wherein the control device further comprises a configuration memory for storing one of the data, whereby j 74 201106371 identifies the B-soil of the plurality of defects _t that is connected to a non-volatile memory device, and the memory device further includes/contains a configuration data bus for reading and writing the data. 107. A method comprising the steps of: detecting a volatile memory —-士A#, one of the main power sources of the power failure; and responding to detecting the power failure and the apricot supply field E W When the standby power source is used to supply the volatile memory: the data stored in the volatile memory is moved to one of the optional non-volatile open evaluation Volatile memory, wherein the step of moving the sand is based on the optional number of non-volatile memory wafers. The method of claim 10, wherein the volatile memory has a size of one billion bytes and the optional number is four. The method of claim 5, wherein the non-volatile memory comprises an electronic erasable programmable read only memory (EEPROMS). 110. The method of claim 109, further comprising the step of: moving the non-volatile memory from the non-volatile memory to the volatile memory after the power recovery of the primary power source occurs. (1).* The method of patent scope 帛11(), wherein the power from the power source of the 75 201106371 is mainly from a capacitor. 112. As claimed in the patent application, the power from the backup power source is primarily from a supercapacitor. 113. A memory device for use with a host processor and a main power source, the memory device comprising: non-volatile memory; volatile memory; an interface m connected to a standby power source, the standby power The source is configured to temporarily supply power to the volatile memory after the __ power loss from the primary power source occurs; isolation logic for controlling access by the host processor to the volatile memory The logic has a first mode and a second mode during which the isolation logic provides the host processor with access to the volatile record (4) for storing or reading, and the isolation logic is Separating the volatile memory from the host processor during the second mode; and - the controller 'which controls the isolation logic' is programmed to be when the volatile memory is being powered by the main power When the source is powered, the isolation logic is placed in the first mode' and when the power from the main power source to the volatile memory is interrupted, the isolation logic is set (4) in the second mode and the data is The volatile memory is transferred to the non-volatile memory. η 76 201106371 114. The memory device of claim 113, wherein the controller is further programmed to: restore data from the non-volatile memory to the volatilization after one of the primary power sources is restored Sexual memory; and when the data is restored, the isolation logic is placed in the first mode. 115. The memory device of claim 113, wherein the controller is further programmed to drive a transition between the controller and the isolation logic to when the isolation logic is in the first mode Impedance state. 116. The memory device of claim 113, wherein at least one multiplexer is included in the isolation logic. 117. The memory device of claim 113, &amp; + &amp; the isolation logic includes a first multiplexer and a second multiplex cry _ _ less 丄 15, the first multiplexer The multiplexer address and the control signal are configured and the first-to-be-worker is configured with a multiplexed data signal. 118. The memory device of claim 113, wherein the + gastric volatile memory comprises a dynamic random access memory. 119. The memory device of claim U3, wherein the non-volatile memory comprises an electronic erasable programmable read-only barrier y 77 201106371 (EEPROMs). 120. The memory device of claim 113, wherein the controller comprises at least one of a special application integrated circuit (ASIC) and a programmable gate array (FPGA). 121. The memory device of claim 113, wherein the power from the alternate power source is primarily from a capacitor. 122. The memory device of claim 113, wherein the power from the alternate power source is primarily from a supercapacitor. 123. A method comprising the steps of: detecting a power failure of one of a primary power source of a volatile memory and responding to detecting the power failure and when the volatile memory is powered by an alternate power source: Changing one mode of the isolation logic from a first mode to a second mode. The first mode provides a host processor for storing or reading while the volatile memory is being powered by the primary power source: Accessing the privileged memory of the data, the first chrome is isolated from the access of the host memory by the first mode of volatilization; and stored in the volatile memory Data in the body of mobile memory. Non-volatile 78 201106371 124. The method of claim 123, further comprising the steps of: restoring data from the non-volatile memory to the volatile memory after one of the primary power sources is restored; and When the data is restored, the isolation logic is placed in the first mode. 125. The method of claim 123, further comprising the step of: driving a coupling between the controller and the isolation logic to a high impedance state when the isolation logic is in the first mode. 126. The method of claim 123, wherein at least one multiplexer is included in the isolation logic. 127. The method of claim 123, wherein the isolation logic includes a first multiplexer and a second multiplexer, the first multiplexer configured to multiplex address and control signals and The second multiplexer is configured to multiplex data signals. 128. The method of claim 123, wherein the volatile memory comprises a dynamic random access memory. 129. The method of claim 123, wherein the non-volatile memory comprises an electronic erasable programmable read only memory $1 (EEPROMs). The method of claim 123, wherein the power from the alternate power source is primarily from a capacitor. 131. The method of claim 123, wherein the power from the alternate power source is derived primarily from a supercapacitor. 80