TWI529399B - Test system, phase detection device and method of the same - Google Patents

Test system, phase detection device and method of the same Download PDF

Info

Publication number
TWI529399B
TWI529399B TW103139790A TW103139790A TWI529399B TW I529399 B TWI529399 B TW I529399B TW 103139790 A TW103139790 A TW 103139790A TW 103139790 A TW103139790 A TW 103139790A TW I529399 B TWI529399 B TW I529399B
Authority
TW
Taiwan
Prior art keywords
phase
voltage signal
offset
module
signal
Prior art date
Application number
TW103139790A
Other languages
Chinese (zh)
Other versions
TW201619616A (en
Inventor
蔡蘇威
高政宏
Original Assignee
德律科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 德律科技股份有限公司 filed Critical 德律科技股份有限公司
Priority to TW103139790A priority Critical patent/TWI529399B/en
Application granted granted Critical
Publication of TWI529399B publication Critical patent/TWI529399B/en
Publication of TW201619616A publication Critical patent/TW201619616A/en

Links

Landscapes

  • Measuring Phase Differences (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

測試系統及其相位檢測裝置及方法 Test system and phase detecting device and method thereof

本發明是有關於一種相位檢測技術,且特別是有關於一種測試系統及其相位檢測裝置及方法。 The present invention relates to a phase detection technique, and more particularly to a test system and a phase detection apparatus and method thereof.

基本交流電路組成之元件有電阻(resistor)、電感(inductor)及電容(capacitor)等。此些電路元件因交流弦波之響應,在電流及電壓會產生相位的差距。部份測試系統中配備有相位檢測裝置,以檢測待測電路元件的電壓訊號的相位。其中,相位可由電壓訊號的實部與虛部檢測得知。然而,在電壓訊號的相位過於接近0度或90度時,容易由於相位檢測裝置內部元件的影響而產生極大的誤差。舉例來說,在量測到實部為1且虛部為0.001的情形下,如產生1毫伏特的誤差,則所計算得的角度誤差將為100%。 The components of the basic AC circuit include a resistor, an inductor, and a capacitor. These circuit components have a phase difference in current and voltage due to the response of the AC sine wave. Some test systems are equipped with phase detection devices to detect the phase of the voltage signal of the circuit component under test. Among them, the phase can be detected by the real part and the imaginary part of the voltage signal. However, when the phase of the voltage signal is too close to 0 or 90 degrees, it is easy to cause a great error due to the influence of the internal components of the phase detecting device. For example, in the case where the real part is measured and the imaginary part is 0.001, if an error of 1 millivolt is generated, the calculated angular error will be 100%.

因此,如何設計一個新的相位檢測裝置及方法,以改善上述的缺點,乃為此一業界亟待解決的問題。 Therefore, how to design a new phase detecting device and method to improve the above disadvantages is an urgent problem to be solved in the industry.

因此,本發明之一態樣是在提供一種相位檢測裝置,包含:訊號產生模組、類比乘法模組以及處理模組。訊號產生模組產生驅動電壓訊號至待測模組,俾使待測模組產生具有待測相位之輸出電壓訊號。類比乘法模組接收輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生直流偏移電壓訊號。處理模組根據直流偏移電壓訊號以及參考電壓訊號計算待測相位,以判斷待測相位是否與相位最小值以及相位最大值其中之一的差值小於臨界值。當待測相位與相位最小值以及相位最大值其中之一的差值小於臨界值,處理模組控制訊號產生模組對驅動電壓訊號進行相位偏移,俾使輸出電壓訊號之待測相位根據相位偏移量偏移至相位最小值以及相位最大值間之中間範圍後,由類比乘法模組接收相位偏移後之輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生相位偏移後之直流偏移電壓訊號,處理模組根據相位偏移後之直流偏移電壓訊號、參考電壓訊號以及相位偏移量計算待測相位。 Therefore, an aspect of the present invention provides a phase detecting device including: a signal generating module, an analog multiplication module, and a processing module. The signal generating module generates a driving voltage signal to the module to be tested, so that the module to be tested generates an output voltage signal having a phase to be tested. The analog multiplication module receives the output voltage signal to multiply with the reference voltage signal to generate a DC offset voltage signal. The processing module calculates the phase to be measured according to the DC offset voltage signal and the reference voltage signal to determine whether the difference between the phase to be measured and one of the phase minimum and the phase maximum is less than a critical value. When the difference between the phase to be measured and the phase minimum and the phase maximum is less than the threshold, the processing module controls the signal generating module to phase shift the driving voltage signal, so that the phase of the output voltage signal is phased according to the phase After the offset is offset to the middle range between the phase minimum and the phase maximum, the phase-shifted output voltage signal is received by the analog multiplication module to multiply with the reference voltage signal to generate a phase offset. The DC offset voltage signal, the processing module calculates the phase to be measured according to the DC offset voltage signal, the reference voltage signal, and the phase offset after the phase offset.

依據本發明一實施例,其中中間範圍為相位最小值以及相位最大值間之相位中間值的正負十度之範圍。 According to an embodiment of the invention, the intermediate range is a range of plus or minus ten degrees of the phase intermediate value between the phase minimum and the phase maximum.

依據本發明另一實施例,其中相位最小值為0度,相位最大值90度且相位中間值為45度。 According to another embodiment of the invention, the phase minimum is 0 degrees, the phase maximum is 90 degrees and the phase intermediate value is 45 degrees.

依據本發明又一實施例,其中類比乘法模組更包含:類比乘法器以及低通濾波器。類比乘法器接收輸出電壓訊號,以與參考電壓訊號相乘,俾產生乘積電壓訊號。低 通濾波器對乘積電壓訊號進行濾波,以產生直流偏移電壓訊號。 According to still another embodiment of the present invention, the analog multiplication module further includes: an analog multiplier and a low pass filter. The analog multiplier receives the output voltage signal to multiply the reference voltage signal to generate a product voltage signal. low The pass filter filters the product voltage signal to generate a DC offset voltage signal.

依據本發明再一實施例,其中訊號產生模組包含:訊號產生器以及驅動電路。訊號產生器產生控制訊號。驅動電路根據控制訊號產生驅動電壓訊號。 According to still another embodiment of the present invention, the signal generating module comprises: a signal generator and a driving circuit. The signal generator generates a control signal. The driving circuit generates a driving voltage signal according to the control signal.

本發明之另一目的在於提供一種測試系統,包含:治具、多通道切換器以及相位檢測裝置。治具電性連接於待測模組。相位檢測裝置包含:訊號產生模組、類比乘法模組以及處理模組。訊號產生模組電性連接於多通道切換器,並用以產生驅動電壓訊號透過多通道切換器及治具傳送至待測模組,俾使待測模組產生具有待測相位之輸出電壓訊號。類比乘法模組電性連接於多通道切換器,並透過治具以及多通道切換器接收輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生直流偏移電壓訊號。處理模組根據直流偏移電壓訊號以及參考電壓訊號計算待測相位,以判斷待測相位是否與相位最小值以及相位最大值其中之一的差值小於臨界值。當待測相位與相位最小值以及相位最大值其中之一的差值小於臨界值,處理模組控制訊號產生模組對驅動電壓訊號進行相位偏移,俾使輸出電壓訊號之待測相位根據相位偏移量偏移至相位最小值以及相位最大值間之中間範圍後,由類比乘法模組接收輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生直流偏移電壓訊號,處理模組根據直流偏移電壓訊號、參考電壓訊號以及相位偏移量計算待測相位。 Another object of the present invention is to provide a test system comprising: a jig, a multi-channel switcher, and a phase detecting device. The fixture is electrically connected to the module to be tested. The phase detecting device comprises: a signal generating module, an analog multiplication module and a processing module. The signal generating module is electrically connected to the multi-channel switcher, and is configured to generate a driving voltage signal to be transmitted to the module to be tested through the multi-channel switcher and the jig, so that the module to be tested generates an output voltage signal having a phase to be tested. The analog multiplication module is electrically connected to the multi-channel switcher, and receives the output voltage signal through the fixture and the multi-channel switcher to multiply with the reference voltage signal to generate a DC offset voltage signal. The processing module calculates the phase to be measured according to the DC offset voltage signal and the reference voltage signal to determine whether the difference between the phase to be measured and one of the phase minimum and the phase maximum is less than a critical value. When the difference between the phase to be measured and the phase minimum and the phase maximum is less than the threshold, the processing module controls the signal generating module to phase shift the driving voltage signal, so that the phase of the output voltage signal is phased according to the phase After the offset is offset to the middle range between the phase minimum and the phase maximum, the analog multiplication module receives the output voltage signal to multiply with the reference voltage signal to generate a DC offset voltage signal, and the processing module is configured according to The DC offset voltage signal, the reference voltage signal, and the phase offset calculate the phase to be measured.

依據本發明一實施例,其中中間範圍為相位最小值以及相位最大值間之相位中間值的正負十度之範圍。 According to an embodiment of the invention, the intermediate range is a range of plus or minus ten degrees of the phase intermediate value between the phase minimum and the phase maximum.

依據本發明另一實施例,其中相位最小值為0度,相位最大值90度且相位中間值為45度。 According to another embodiment of the invention, the phase minimum is 0 degrees, the phase maximum is 90 degrees and the phase intermediate value is 45 degrees.

依據本發明又一實施例,其中類比乘法模組更包含:類比乘法器以及低通濾波器。類比乘法器接收輸出電壓訊號,以與參考電壓訊號相乘,俾產生乘積電壓訊號。低通濾波器對乘積電壓訊號進行濾波,以產生直流偏移電壓訊號。 According to still another embodiment of the present invention, the analog multiplication module further includes: an analog multiplier and a low pass filter. The analog multiplier receives the output voltage signal to multiply the reference voltage signal to generate a product voltage signal. The low pass filter filters the product voltage signal to produce a DC offset voltage signal.

依據本發明再一實施例,其中訊號產生模組包含:訊號產生器以及驅動電路。訊號產生器產生控制訊號。驅動電路根據控制訊號產生驅動電壓訊號。 According to still another embodiment of the present invention, the signal generating module comprises: a signal generator and a driving circuit. The signal generator generates a control signal. The driving circuit generates a driving voltage signal according to the control signal.

本發明之又一目的在於提供一種相位檢測方法,應用於相位檢測裝置中。相位檢測方法包含下列步驟。藉由訊號產生模組產生驅動電壓訊號至待測模組,俾使待測模組產生具有待測相位之輸出電壓訊號;藉由類比乘法模組接收輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生直流偏移電壓訊號;藉由處理模組根據直流偏移電壓訊號以及參考電壓訊號計算待測相位,以判斷待測相位是否與相位最小值以及相位最大值其中之一的差值小於臨界值;當待測相位與相位最小值以及相位最大值其中之一的差值小於臨界值,處理模組控制訊號產生模組對驅動電壓訊號進行相位偏移,俾使輸出電壓訊號之待測相位根據相位偏移量偏移至相位最小值以及相位最大值間之中間範圍;藉由類比乘法模組 接收相位偏移後之輸出電壓訊號,以與參考電壓訊號進行相乘,俾產生相位偏移後之直流偏移電壓訊號;以及藉由處理模組根據相位偏移後之直流偏移電壓訊號、參考電壓訊號以及相位偏移量計算待測相位。 It is still another object of the present invention to provide a phase detecting method for use in a phase detecting device. The phase detection method includes the following steps. The signal generating module generates a driving voltage signal to the module to be tested, so that the module to be tested generates an output voltage signal having a phase to be tested; and the analog multiplication module receives the output voltage signal to perform phase response with the reference voltage signal. Multiply, generate a DC offset voltage signal; the processing module calculates the phase to be measured according to the DC offset voltage signal and the reference voltage signal to determine whether the phase to be measured is different from the phase minimum and the phase maximum value. Less than the critical value; when the difference between the phase to be measured and the phase minimum and the phase maximum is less than the critical value, the processing module controls the signal generation module to phase shift the driving voltage signal, so that the output voltage signal is waiting The phase is shifted according to the phase offset to the intermediate range between the phase minimum and the phase maximum; by analogy multiplication module Receiving the phase offset output voltage signal to multiply with the reference voltage signal, generating a phase offset DC offset voltage signal; and processing the module according to the phase offset DC offset voltage signal, The reference voltage signal and the phase offset are used to calculate the phase to be measured.

依據本發明一實施例,其中中間範圍為相位最小值以及相位最大值間之相位中間值的正負十度之範圍。 According to an embodiment of the invention, the intermediate range is a range of plus or minus ten degrees of the phase intermediate value between the phase minimum and the phase maximum.

依據本發明另一實施例,其中相位最小值為0度,相位最大值90度且相位中間值為45度。 According to another embodiment of the invention, the phase minimum is 0 degrees, the phase maximum is 90 degrees and the phase intermediate value is 45 degrees.

依據本發明又一實施例,其中類比乘法模組更包含類比乘法器以及低通濾波器,相位檢測方法更包含:藉由類比乘法器接收輸出電壓訊號,以與參考電壓訊號相乘,俾產生乘積電壓訊號;以及藉由低通濾波器對乘積電壓訊號進行濾波,以產生直流偏移電壓訊號。 According to still another embodiment of the present invention, the analog multiplication module further includes an analog multiplier and a low pass filter, and the phase detection method further comprises: receiving the output voltage signal by the analog multiplier to multiply with the reference voltage signal, and generating a product voltage signal; and filtering the product voltage signal by a low pass filter to generate a DC offset voltage signal.

依據本發明再一實施例,其中訊號產生模組包含訊號產生器以及驅動電路,相位檢測方法更包含:藉由訊號產生器產生控制訊號;以及藉由驅動電路根據控制訊號產生驅動電壓訊號。 According to still another embodiment of the present invention, the signal generating module includes a signal generator and a driving circuit. The phase detecting method further includes: generating a control signal by the signal generator; and generating a driving voltage signal according to the control signal by the driving circuit.

應用本發明之優點在於,本發明的相位檢測裝置可先藉由檢測判斷待測相位的大小後,進一步在待測相位過於接近相位最小值或相位最大值時,對具有待測相位的輸出電壓訊號進行相位偏移,以獲得更精確的檢測結果,而輕易地達到上述之目的。 An advantage of the present invention is that the phase detecting device of the present invention can first determine the phase of the phase to be measured by detecting, and further output the voltage having the phase to be tested when the phase to be measured is too close to the phase minimum or the phase maximum. The signal is phase shifted to obtain a more accurate detection result, and the above purpose is easily achieved.

1‧‧‧相位檢測裝置 1‧‧‧ phase detection device

10‧‧‧訊號產生模組 10‧‧‧Signal Generation Module

100‧‧‧訊號產生器 100‧‧‧Signal Generator

102‧‧‧驅動電路 102‧‧‧ drive circuit

12‧‧‧類比乘法模組 12‧‧‧ analog multiplication module

120‧‧‧類比乘法器 120‧‧‧ analog multiplier

122‧‧‧低通濾波器 122‧‧‧Low-pass filter

14‧‧‧處理模組 14‧‧‧Processing module

16‧‧‧類比數位轉換模組 16‧‧‧ analog digital conversion module

2‧‧‧待測模組 2‧‧‧ modules to be tested

3‧‧‧測試系統 3‧‧‧Test system

30‧‧‧治具 30‧‧‧ fixture

32‧‧‧多通道切換器 32‧‧‧Multichannel switcher

400‧‧‧相位檢測方法 400‧‧‧ Phase detection method

401-408‧‧‧步驟 401-408‧‧‧Steps

第1圖為本發明一實施例中,一種相位檢測裝置之方塊圖;第2圖為本發明一實施例中,輸出電壓訊號的示意圖;第3圖為本發明一實施例中,一種測試系統的方塊圖;以及第4圖為本發明一實施例中,一種相位檢測方法的流程圖。 1 is a block diagram of a phase detecting device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of an output voltage signal according to an embodiment of the present invention; and FIG. 3 is a test system according to an embodiment of the present invention; FIG. 4 is a flow chart of a phase detecting method according to an embodiment of the present invention.

請參照第1圖。第1圖為本發明一實施例中,一種相位檢測裝置1之方塊圖。相位檢測裝置1包含:訊號產生模組10、類比乘法模組12以及處理模組14。 Please refer to Figure 1. 1 is a block diagram of a phase detecting device 1 according to an embodiment of the present invention. The phase detecting device 1 includes a signal generating module 10, an analog multiplication module 12, and a processing module 14.

於一實施例中,訊號產生模組10包含訊號產生器100以及驅動電路102。訊號產生器100產生控制訊號CTL,以使驅動電路102根據控制訊號CTL產生驅動電壓訊號Vdrive至待測模組2。待測模組2根據驅動電壓訊號Vdrive產生具有待測相位θ之輸出電壓訊號Vout。於不同實施例中,待測模組2可包含不同類型的電路,例如但不限於一容阻電路。 In one embodiment, the signal generation module 10 includes a signal generator 100 and a drive circuit 102. The signal generator 100 generates the control signal CTL to enable the driving circuit 102 to generate the driving voltage signal Vdrive to the module under test 2 according to the control signal CTL. The module under test 2 generates an output voltage signal Vout having a phase θ to be measured according to the driving voltage signal Vdrive. In various embodiments, the module under test 2 may include different types of circuits such as, but not limited to, a capacitive circuit.

於一實施例中,類比乘法模組12包含類比乘法器120以及低通濾波器122。類比乘法器120接收輸出電壓訊號Vout,以與參考電壓訊號Vref相乘,俾產生乘積電壓 訊號Vm。低通濾波器122進一步對乘積電壓訊號Vm進行濾波,以濾除交流成份並產生直流偏移電壓訊號Vdc。 In an embodiment, the analog multiplication module 12 includes an analog multiplier 120 and a low pass filter 122. The analog multiplier 120 receives the output voltage signal Vout to be multiplied by the reference voltage signal Vref to generate a product voltage. Signal Vm. The low pass filter 122 further filters the product voltage signal Vm to filter out the AC component and generate a DC offset voltage signal Vdc.

於一實施例中,待測相位θ是輸出電壓訊號Vout的電壓與電流間的相位差,並由產生輸出電壓訊號Vout的待測模組2中的電路決定。舉例來說,當待測模組2包含相並聯的電容及電阻所形成的容阻電路時,電阻將決定整體阻抗的實部,而電容將決定整體阻抗的虛部。電阻相對電容愈大時將使輸出電壓訊號Vout的待測相位θ愈小,而電阻相對電容愈小時將使輸出電壓訊號Vout的待測相位θ愈大。 In one embodiment, the phase to be measured θ is the phase difference between the voltage and the current of the output voltage signal Vout, and is determined by the circuit in the module 2 to be tested that generates the output voltage signal Vout. For example, when the module to be tested 2 includes a capacitance circuit formed by parallel capacitors and resistors, the resistor will determine the real part of the overall impedance, and the capacitance will determine the imaginary part of the overall impedance. The larger the relative resistance of the resistor, the smaller the phase θ of the output voltage signal Vout to be measured, and the smaller the relative capacitance of the resistor, the larger the phase θ of the output voltage signal Vout to be measured.

於一實施例中,輸出電壓訊號Vout的待測相位θ是位於0度至90度的範圍內,其中0度為相位最小值,90度為相位最大值。當電阻相對電容愈大時將使輸出電壓訊號Vout的待測相位θ愈接近0度,而電阻相對電容愈小時將使輸出電壓訊號Vout的待測相位θ愈接近90度。 In one embodiment, the measured phase θ of the output voltage signal Vout is in the range of 0 degrees to 90 degrees, wherein 0 degrees is the phase minimum value and 90 degrees is the phase maximum value. When the relative capacitance of the resistor is larger, the phase θ of the output voltage signal Vout is closer to 0 degree, and the smaller the relative capacitance of the resistor is, the closer the phase θ of the output voltage signal Vout is to 90 degrees.

其中,當參考電壓訊號Vref的相位為0度時,和輸出電壓訊號Vout相乘產生的直流偏移電壓訊號Vdc將為輸出電壓訊號Vout的實部。而當參考電壓訊號Vref的相位為90度時,和輸出電壓訊號Vout相乘產生的直流偏移電壓訊號Vdc將為輸出電壓訊號Vout的虛部。 When the phase of the reference voltage signal Vref is 0 degrees, the DC offset voltage signal Vdc generated by multiplying the output voltage signal Vout will be the real part of the output voltage signal Vout. When the phase of the reference voltage signal Vref is 90 degrees, the DC offset voltage signal Vdc generated by multiplying the output voltage signal Vout will be the imaginary part of the output voltage signal Vout.

處理模組14將從類比乘法模組12接收直流偏移電壓訊號Vdc。於一實施例中,相位檢測裝置1可包含類比數位轉換模組16(於第1圖係以ADC標識),以將直流偏 移電壓訊號Vdc由類比形式轉為數位形式。因此,處理模組14將接收到數位形式的直流偏移電壓訊號Vdc。 The processing module 14 receives the DC offset voltage signal Vdc from the analog multiplication module 12. In an embodiment, the phase detecting device 1 may include an analog digital conversion module 16 (identified by the ADC in FIG. 1) to bias the DC The shift voltage signal Vdc is converted from an analog form to a digital form. Therefore, the processing module 14 will receive the DC offset voltage signal Vdc in digital form.

處理模組14進一步根據直流偏移電壓訊號Vdc以及參考電壓訊號Vref計算待測相位θ。於一實施例中,當待測相位為θ,所檢測的實部為Real且虛部為Imag時,待測相位θ將可以下式表示:θ=tan-1(Imag/Real) The processing module 14 further calculates the phase θ to be measured according to the DC offset voltage signal Vdc and the reference voltage signal Vref. In an embodiment, when the phase to be measured is θ, the real part detected is Real, and the imaginary part is Imag, the phase θ to be measured can be expressed by: θ=tan -1 (Imag/Real)

處理模組14進一步判斷待測相位θ是否與相位最小值以及相位最大值其中之一的差值小於臨界值。 The processing module 14 further determines whether the difference between the phase θ to be measured and one of the phase minimum and the phase maximum is less than a critical value.

於一實施例中,當處理模組14判斷待測相位θ並未與相位最小值及相位最大值其中之一的差值小於臨界值時,表示此待測相位θ不容易受到進行檢測的元件如類比乘法模組12及/或類比數位轉換模組16包含的元件所影響,所測得的相位值較精準。處理模組14將直接以此階段測得的待測相位θ作為檢測結果。 In an embodiment, when the processing module 14 determines that the difference between the phase θ to be measured and one of the phase minimum and the phase maximum is less than a threshold, the component that is to be measured is not susceptible to detection. If the components included in the analog multiplication module 12 and/or the analog digital conversion module 16 are affected, the measured phase values are more accurate. The processing module 14 takes the phase θ to be measured measured directly at this stage as the detection result.

於一實施例中,以上述相位最小值為0度以及相位最大值為90度為例,此臨界值可為10度。因此,當待測相位θ在不小於10度及不大於80度時,處理模組14將直接以此階段測得的待測相位θ作為檢測結果。於另一實施例中,此臨界值可為20度。因此,當待測相位θ在不小於20度及不大於70度時,處理模組14將直接以此階段測得的待測相位θ作為檢測結果。 In one embodiment, taking the above-mentioned phase minimum value as 0 degrees and the phase maximum value as 90 degrees as an example, the threshold value may be 10 degrees. Therefore, when the phase θ to be measured is not less than 10 degrees and not more than 80 degrees, the processing module 14 directly uses the phase θ to be measured measured at this stage as the detection result. In another embodiment, the threshold can be 20 degrees. Therefore, when the phase θ to be measured is not less than 20 degrees and not more than 70 degrees, the processing module 14 directly uses the phase θ to be measured measured at this stage as the detection result.

然而,當處理模組14判斷待測相位θ與相位最小值及相位最大值其中之一的差值小於臨界值時,表示此待 測相位θ容易受到進行檢測的元件如類比乘法模組12包含的元件所影響,精確度將大幅下降。 However, when the processing module 14 determines that the difference between the phase θ to be measured and one of the phase minimum and the phase maximum is less than a critical value, it indicates that the The measured phase θ is susceptible to the components being detected, such as the components included in the analog multiplication module 12, and the accuracy is greatly reduced.

此時,處理模組14控制訊號產生模組10對驅動電壓訊號Vdrive進行相位偏移。待測模組2將根據相位偏移後的驅動電壓訊號Vdrive’,使原本的輸出電壓訊號Vout之待測相位θ根據相位偏移量△θ偏移至相位最小值以及相位最大值間之中間範圍。 At this time, the processing module 14 controls the signal generating module 10 to phase shift the driving voltage signal Vdrive. The module 2 to be tested will shift the phase θ of the original output voltage signal Vout according to the phase offset Δθ to the middle of the phase minimum value and the phase maximum value according to the phase-shifted driving voltage signal Vdrive'. range.

於一實施例中,中間範圍為相位最小值以及相位最大值間之相位中間值的正負十度之範圍。以上述相位最小值為0度以及相位最大值為90度為例,其相位中間值將為45度。因此,中間範圍將為45度的正負十度。亦即,輸出電壓訊號Vout之待測相位θ根據相位偏移量△θ偏移至45度的正負十度的範圍內,即35度至55度之間。 In one embodiment, the intermediate range is the range of positive and negative ten degrees of the phase intermediate value between the phase minimum and the phase maximum. Taking the above-mentioned phase minimum value as 0 degree and the phase maximum value as 90 degrees as an example, the phase intermediate value will be 45 degrees. Therefore, the intermediate range will be plus or minus ten degrees of 45 degrees. That is, the phase θ to be measured of the output voltage signal Vout is shifted to a range of plus or minus ten degrees of 45 degrees, that is, between 35 degrees and 55 degrees, according to the phase shift amount Δθ.

類比乘法模組12接收相位偏移後之輸出電壓訊號Vout’,以與及該參考電壓訊號以進行相乘,俾產生相位偏移後之直流偏移電壓訊號Vdc’。如前所述,類比乘法模組12中的類比乘法器120將接收輸出電壓訊號Vout’,以與參考電壓訊號Vref相乘產生乘積電壓訊號Vm’後,由低通濾波器122進一步對乘積電壓訊號Vm’進行濾波並產生直流偏移電壓訊號Vdc’。 The analog multiplication module 12 receives the phase-shifted output voltage signal Vout' to multiply the reference voltage signal to generate a phase-shifted DC offset voltage signal Vdc'. As described above, the analog multiplier 120 in the analog multiplication module 12 will receive the output voltage signal Vout' to multiply the reference voltage signal Vref to generate the product voltage signal Vm', and then further the product voltage by the low pass filter 122. The signal Vm' is filtered and generates a DC offset voltage signal Vdc'.

處理模組14根據相位偏移後之直流偏移電壓訊號Vdc’、參考電壓訊號Vref以及相位偏移量△θ計算待測相位θ。於一實施例中,於一實施例中,當待測相位為θ, 所檢測的實部為Real且虛部為Imag,且相位偏移量為△θ時,待測相位θ將可以下式表示:θ=tan-1(Imag/Real)-△θ The processing module 14 calculates the phase θ to be measured according to the DC offset voltage signal Vdc′ after the phase shift, the reference voltage signal Vref, and the phase shift amount Δθ. In an embodiment, in an embodiment, when the measured phase is θ, the detected real part is Real, and the imaginary part is Imag, and the phase offset is Δθ, the phase to be measured θ can be Representation: θ=tan -1 (Imag/Real)-△θ

於一實施例中,以上述相位最小值為0度以及相位最大值為90度為例,此臨界值可為10度。因此,當待測相位θ在小於10度及大於80度時,處理模組14將控制訊號產生模組10對驅動電壓訊號Vdrive進行相位偏移,並以相位偏移後的檢測作為檢測結果。於另一實施例中,此臨界值可為20度。因此,當待測相位θ在小於20度及大於70度時,處理模組14將控制訊號產生模組10對驅動電壓訊號Vdrive進行相位偏移,並以相位偏移後的檢測作為檢測結果。 In one embodiment, taking the above-mentioned phase minimum value as 0 degrees and the phase maximum value as 90 degrees as an example, the threshold value may be 10 degrees. Therefore, when the phase θ to be measured is less than 10 degrees and greater than 80 degrees, the processing module 14 performs phase shifting on the driving voltage signal Vdrive by the control signal generating module 10, and detects the phase offset as the detection result. In another embodiment, the threshold can be 20 degrees. Therefore, when the phase θ to be measured is less than 20 degrees and greater than 70 degrees, the processing module 14 performs phase shifting on the driving voltage signal Vdrive by the control signal generating module 10, and detects the phase offset as the detection result.

請參照第2圖。第2圖為本發明一實施例中,輸出電壓訊號Vout及Vout’的示意圖。其中,輸出電壓訊號Vout在實部軸上的分量為其實部Real,在虛部軸上的分量為其虛部Imag。 Please refer to Figure 2. Fig. 2 is a schematic diagram showing output voltage signals Vout and Vout' in an embodiment of the invention. The component of the output voltage signal Vout on the real axis is the real part Real, and the component on the imaginary part axis is the imaginary part Imag.

如第2圖所示,在本實施例中,由於輸出電壓訊號Vout的實部Real遠大於虛部Imag而使得待測相位θ過於接近0度。因此,藉由上述的相位偏移機制,將可產生具有相位偏移量△θ的輸出電壓訊號Vout’。此時,相位偏移後的輸出電壓訊號Vout’的相位θ+△θ將不容易受到進行檢測的元件如類比乘法模組12包含的元件所影響,而可先測得相位θ+△θ後,再減去相位偏移量△θ獲得待測相位θ。 As shown in FIG. 2, in the present embodiment, since the real part Real of the output voltage signal Vout is much larger than the imaginary part Imag, the phase θ to be measured is too close to 0 degree. Therefore, by the phase shifting mechanism described above, the output voltage signal Vout' having the phase shift amount Δθ can be generated. At this time, the phase θ+Δθ of the phase-shifted output voltage signal Vout′ will not be easily affected by the component to be detected, such as the component included in the analog multiplication module 12, but the phase θ+Δθ may be measured first. Then, the phase offset Δθ is subtracted to obtain the phase θ to be measured.

因此,本發明的相位檢測裝置1可先藉由檢測判斷待測相位θ的大小後,進一步在待測相位θ過於接近相位 最小值或相位最大值時,對具有待測相位θ的輸出電壓訊號進行相位偏移,以獲得更精確的檢測結果。 Therefore, the phase detecting device 1 of the present invention can first determine the phase θ to be measured by detecting, and further the phase θ to be measured is too close to the phase. At the minimum or phase maximum, the output voltage signal with the phase θ to be measured is phase shifted to obtain a more accurate detection result.

請參照第3圖。第3圖為本發明一實施例中,一種測試系統3的方塊圖。測試系統3包含:治具30、多通道切換器32以及相位檢測裝置1。 Please refer to Figure 3. Figure 3 is a block diagram of a test system 3 in accordance with one embodiment of the present invention. The test system 3 includes a jig 30, a multi-channel switch 32, and a phase detecting device 1.

於本實施例中,治具30電性連接於待測模組2。而相位檢測裝置1則透過電性連接於治具30的多通道切換器32以及治具30傳送驅動電壓訊號Vdrive及Vdrive’至待測模組2,以及從待測模組2接收輸出電壓訊號Vout及Vout’。 In the embodiment, the fixture 30 is electrically connected to the module 2 to be tested. The phase detecting device 1 transmits the driving voltage signals Vdrive and Vdrive' to the module 2 to be tested through the multi-channel switch 32 and the fixture 30 electrically connected to the jig 30, and receives the output voltage signal from the module 2 to be tested. Vout and Vout'.

請參照第4圖。第4圖為本發明一實施例中,一種相位檢測方法400的流程圖。相位檢測方法400可應用於如第1圖所示的相位檢測裝置1中。相位檢測方法400包含下列步驟。 Please refer to Figure 4. 4 is a flow chart of a phase detection method 400 in accordance with an embodiment of the present invention. The phase detecting method 400 can be applied to the phase detecting device 1 as shown in Fig. 1. Phase detection method 400 includes the following steps.

於步驟401,藉由訊號產生模組10產生驅動電壓訊號Vdrive至待測模組2,俾使待測模組2產生具有待測相位θ之輸出電壓訊號Vout。 In step 401, the signal generating module 10 generates a driving voltage signal Vdrive to the module 2 to be tested, and causes the module under test 2 to generate an output voltage signal Vout having a phase θ to be measured.

於步驟402,藉由類比乘法模組12接收輸出電壓訊號Vout,以與參考電壓訊號Vref進行相乘,俾產生直流偏移電壓訊號Vdc。 In step 402, the analog voltage signal Vout is received by the analog multiplication module 12 to multiply the reference voltage signal Vref to generate a DC offset voltage signal Vdc.

於步驟403,藉由處理模組14根據直流偏移電壓訊號Vdc以及參考電壓訊號Vref計算待測相位,以於步驟404判斷待測相位θ是否與相位最小值以及相位最大值其中之一的差值小於臨界值。 In step 403, the processing module 14 calculates the phase to be measured according to the DC offset voltage signal Vdc and the reference voltage signal Vref, so as to determine, in step 404, whether the phase to be measured θ is different from one of the phase minimum and the phase maximum. The value is less than the critical value.

當待測相位與相位最小值以及相位最大值其中之一的差值不小於臨界值,處理模組14於步驟405判斷此待測相位θ為精確。 When the difference between the phase to be measured and the phase minimum and the phase maximum is not less than the threshold, the processing module 14 determines in step 405 that the phase θ to be measured is accurate.

而當待測相位與相位最小值以及相位最大值其中之一的差值小於臨界值,處理模組14於步驟406控制訊號產生模組10對驅動電壓訊號Vdrive進行相位偏移,俾使待測模組2產生相位偏移後之輸出電壓訊號Vout’。 When the difference between the phase to be measured and the phase minimum and the phase maximum is less than the threshold, the processing module 14 controls the signal generating module 10 to phase shift the driving voltage signal Vdrive in step 406, so that the test is to be tested. Module 2 produces an output voltage signal Vout' after phase shift.

於步驟407,藉由類比乘法模組12接收輸出電壓訊號Vout’,以與參考電壓訊號Vref進行相乘,俾產生直流偏移電壓訊號Vdc’。 In step 407, the analog voltage signal Vout' is received by the analog multiplication module 12 to multiply the reference voltage signal Vref to generate a DC offset voltage signal Vdc'.

於步驟408,藉由處理模組14根據直流偏移電壓訊號Vdc、參考電壓訊號Vref以及相位偏移量△θ計算待測相位θ。 In step 408, the processing module 14 calculates the phase θ to be measured according to the DC offset voltage signal Vdc, the reference voltage signal Vref, and the phase shift amount Δθ.

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種之更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。 The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

1‧‧‧相位檢測裝置 1‧‧‧ phase detection device

10‧‧‧訊號產生模組 10‧‧‧Signal Generation Module

100‧‧‧訊號產生器 100‧‧‧Signal Generator

102‧‧‧驅動電路 102‧‧‧ drive circuit

12‧‧‧類比乘法模組 12‧‧‧ analog multiplication module

120‧‧‧類比乘法器 120‧‧‧ analog multiplier

122‧‧‧低通濾波器 122‧‧‧Low-pass filter

14‧‧‧處理模組 14‧‧‧Processing module

16‧‧‧類比數位轉換模組 16‧‧‧ analog digital conversion module

2‧‧‧待測模組 2‧‧‧ modules to be tested

Claims (15)

一種相位檢測裝置,包含:一訊號產生模組,用以產生一驅動電壓訊號至一待測模組,俾使該待測模組產生具有一待測相位之一輸出電壓訊號;一類比乘法模組,用以接收該輸出電壓訊號,以與一參考電壓訊號進行相乘,俾產生一直流偏移電壓訊號;以及一處理模組,用以根據該直流偏移電壓訊號以及該參考電壓訊號計算該待測相位,以判斷該待測相位是否與一相位最小值以及一相位最大值其中之一的一差值小於一臨界值;當該待測相位與該相位最小值以及該相位最大值其中之一的該差值小於該臨界值,該處理模組控制該訊號產生模組對該驅動電壓訊號進行相位偏移,俾使該輸出電壓訊號之該待測相位根據一相位偏移量偏移至該相位最小值以及該相位最大值間之一中間範圍後,由該類比乘法模組接收相位偏移後之該輸出電壓訊號,以與該參考電壓訊號進行相乘,俾產生相位偏移後之該直流偏移電壓訊號,該處理模組根據相位偏移後之該直流偏移電壓訊號、該參考電壓訊號以及該相位偏移量計算該待測相位。 A phase detecting device includes: a signal generating module for generating a driving voltage signal to a module to be tested, and causing the module to be tested to generate an output voltage signal having a phase to be measured; an analog multiplication mode The group is configured to receive the output voltage signal for multiplication with a reference voltage signal to generate a DC offset voltage signal, and a processing module for calculating the DC offset voltage signal and the reference voltage signal The phase to be measured is used to determine whether the difference between the phase to be measured and one of the phase minimum and one phase maximum is less than a threshold; when the phase to be measured and the phase minimum and the phase maximum are The difference between the one of the thresholds is less than the threshold value, and the processing module controls the signal generating module to phase shift the driving voltage signal, so that the phase to be measured of the output voltage signal is offset according to a phase offset After the intermediate range between the minimum value of the phase and the maximum value of the phase, the analog multiplication module receives the output voltage signal after the phase offset, and the reference voltage The multiplication is performed to generate the DC offset voltage signal after the phase shift, and the processing module calculates the to-be-tested according to the DC offset voltage signal after the phase offset, the reference voltage signal, and the phase offset Phase. 如請求項1所述之相位檢測裝置,其中該中間範圍為該相位最小值以及該相位最大值間之一相位中間值的正負十度之範圍。 The phase detecting device of claim 1, wherein the intermediate range is a range of plus or minus ten degrees of the phase intermediate value and the phase intermediate value between the phase maximum values. 如請求項2所述之相位檢測裝置,其中該相位最小值為0度,該相位最大值90度且該相位中間值為45度。 The phase detecting device according to claim 2, wherein the phase minimum value is 0 degrees, the phase maximum value is 90 degrees, and the phase intermediate value is 45 degrees. 如請求項1所述之相位檢測裝置,其中該類比乘法模組更包含:一類比乘法器,用以接收該輸出電壓訊號,以與該參考電壓訊號相乘,俾產生一乘積電壓訊號;以及一低通濾波器,用以對該乘積電壓訊號進行濾波,以產生該直流偏移電壓訊號。 The phase detecting device of claim 1, wherein the analog multiplication module further comprises: an analog multiplier for receiving the output voltage signal to multiply the reference voltage signal to generate a product voltage signal; A low pass filter is used to filter the product voltage signal to generate the DC offset voltage signal. 如請求項1所述之相位檢測裝置,其中該訊號產生模組包含:一訊號產生器,用以產生一控制訊號;以及一驅動電路,用以根據該控制訊號產生該驅動電壓訊號。 The phase detecting device of claim 1, wherein the signal generating module comprises: a signal generator for generating a control signal; and a driving circuit for generating the driving voltage signal according to the control signal. 一種測試系統,包含:一治具,用以電性連接於一待測模組;一多通道切換器;以及一相位檢測裝置,包含:一訊號產生模組,電性連接於該多通道切換器,並用以產生一驅動電壓訊號透過該多通道切換器及 該治具傳送至該待測模組,俾使該待測模組產生具有一待測相位之一輸出電壓訊號;一類比乘法模組,電性連接於該多通道切換器,並透過該治具以及該多通道切換器接收該輸出電壓訊號,以與一參考電壓訊號進行相乘,俾產生一直流偏移電壓訊號;以及一處理模組,用以根據該直流偏移電壓訊號以及該參考電壓訊號計算該待測相位,以判斷該待測相位是否與一相位最小值以及一相位最大值其中之一的一差值小於一臨界值;當該待測相位與該相位最小值以及該相位最大值其中之一的該差值小於該臨界值,該處理模組控制該訊號產生模組對該驅動電壓訊號進行相位偏移,俾使該輸出電壓訊號之該待測相位根據一相位偏移量偏移至該相位最小值以及該相位最大值間之一中間範圍後,由該類比乘法模組接收該輸出電壓訊號,以與該參考電壓訊號進行相乘,俾產生該直流偏移電壓訊號,該處理模組根據該直流偏移電壓訊號、該參考電壓訊號以及該相位偏移量計算該待測相位。 A test system comprising: a fixture for electrically connecting to a module to be tested; a multi-channel switch; and a phase detecting device comprising: a signal generating module electrically connected to the multi-channel switching And generating a driving voltage signal through the multi-channel switch and The fixture is transmitted to the module to be tested, so that the module to be tested generates an output voltage signal having a phase to be tested; an analog multiplication module is electrically connected to the multichannel switch and passes through the treatment And the multi-channel switch receives the output voltage signal for multiplying with a reference voltage signal to generate a DC offset voltage signal; and a processing module for determining the DC offset voltage signal and the reference Calculating the phase to be measured by the voltage signal to determine whether the difference between the phase to be measured and one of the phase minimum and one phase maximum is less than a threshold; when the phase to be measured and the phase minimum and the phase The difference between one of the maximum values is less than the threshold value, and the processing module controls the signal generating module to phase shift the driving voltage signal, so that the phase to be measured of the output voltage signal is offset according to a phase After the amount is offset to an intermediate range between the minimum value of the phase and the maximum value of the phase, the analog multiplication module receives the output voltage signal for multiplication with the reference voltage signal. Serve to generate the DC offset voltage signal, the processing module based on the DC offset voltage signal, the reference voltage signal and calculating the phase shift amount of the test phase. 如請求項6所述之測試系統,其中該中間範圍為該相位最小值以及該相位最大值間之一相位中間值的正負十度之範圍。 The test system of claim 6, wherein the intermediate range is a range of plus or minus ten degrees of the phase minimum value and one of the phase intermediate values. 如請求項7所述之測試系統,其中該相位最小值為0度,該相位最大值90度且該相位中間值為45度。 The test system of claim 7, wherein the phase minimum is 0 degrees, the phase maximum is 90 degrees and the phase intermediate value is 45 degrees. 如請求項6所述之測試系統,其中該類比乘法模組更包含:一類比乘法器,用以接收該輸出電壓訊號,以與該參考電壓訊號相乘,俾產生一乘積電壓訊號;以及一低通濾波器,用以對該乘積電壓訊號進行濾波,以產生該直流偏移電壓訊號。 The test system of claim 6, wherein the analog multiplication module further comprises: an analog multiplier for receiving the output voltage signal for multiplying the reference voltage signal to generate a product voltage signal; and And a low pass filter for filtering the product voltage signal to generate the DC offset voltage signal. 如請求項6所述之測試系統,其中該訊號產生模組包含:一訊號產生器,用以產生一控制訊號;以及一驅動電路,用以根據該控制訊號產生該驅動電壓訊號。 The test system of claim 6, wherein the signal generating module comprises: a signal generator for generating a control signal; and a driving circuit for generating the driving voltage signal according to the control signal. 一種相位檢測方法,應用於一相位檢測裝置中,包含:藉由一訊號產生模組產生一驅動電壓訊號至一待測模組,俾使該待測模組產生具有一待測相位之一輸出電壓訊號;藉由一類比乘法模組接收該輸出電壓訊號,以與一參考電壓訊號進行相乘,俾產生一直流偏移電壓訊號;藉由一處理模組根據該直流偏移電壓訊號以及該參考電壓訊號計算該待測相位,以判斷該待測相位是否與一相位最小值以及一相位最大值其中之一的一差值小於一臨界值;當該待測相位與該相位最小值以及該相位最大值其中之一的該差值小於該臨界值,該處理模組控制該訊號產 生模組對該驅動電壓訊號進行相位偏移,俾使該輸出電壓訊號之該待測相位根據一相位偏移量偏移至該相位最小值以及該相位最大值間之一中間範圍;藉由該類比乘法模組接收相位偏移後之該輸出電壓訊號,以與該參考電壓訊號進行相乘,俾產生相位偏移後之該直流偏移電壓訊號;以及藉由該處理模組根據相位偏移後之該直流偏移電壓訊號、該參考電壓訊號以及該相位偏移量計算該待測相位。 A phase detecting method is applied to a phase detecting device, comprising: generating a driving voltage signal to a module to be tested by a signal generating module, and causing the module to be tested to generate an output having a phase to be tested a voltage signal; receiving the output voltage signal by a analog multiplication module to multiply with a reference voltage signal to generate a DC offset voltage signal; and a processing module according to the DC offset voltage signal and the Calculating the phase to be measured by the reference voltage signal to determine whether the difference between the phase to be measured and one of the phase minimum and one phase maximum is less than a threshold; when the phase to be measured and the phase minimum are The difference between one of the phase maximum values is less than the threshold value, and the processing module controls the signal production The generating module phase shifts the driving voltage signal, so that the phase to be measured of the output voltage signal is offset according to a phase offset to an intermediate range between the phase minimum and the phase maximum value; The analog multiplication module receives the phase offset signal of the output voltage signal to multiply the reference voltage signal to generate the phase offset signal after the phase offset; and the phase shift by the processing module The shifted DC offset voltage signal, the reference voltage signal, and the phase offset calculate the phase to be tested. 如請求項11所述之相位檢測方法,其中該中間範圍為該相位最小值以及該相位最大值間之一相位中間值的正負十度之範圍。 The phase detecting method according to claim 11, wherein the intermediate range is a range of plus or minus ten degrees of the phase minimum value and the phase intermediate value between the phase maximum values. 如請求項12所述之相位檢測方法,其中該相位最小值為0度,該相位最大值90度且該相位中間值為45度。 The phase detecting method according to claim 12, wherein the phase minimum value is 0 degrees, the phase maximum value is 90 degrees, and the phase intermediate value is 45 degrees. 如請求項11所述之相位檢測方法,其中該類比乘法模組更包含一類比乘法器以及一低通濾波器,該相位檢測方法更包含:藉由該類比乘法器接收該輸出電壓訊號,以與該參考電壓訊號相乘,俾產生一乘積電壓訊號;以及藉由一低通濾波器對該乘積電壓訊號進行濾波,以產生該直流偏移電壓訊號。 The phase detecting method of claim 11, wherein the analog multiplication module further comprises an analog multiplier and a low pass filter, the phase detecting method further comprising: receiving the output voltage signal by the analog multiplier, Multiplying the reference voltage signal to generate a product voltage signal; and filtering the product voltage signal by a low pass filter to generate the DC offset voltage signal. 如請求項11所述之相位檢測方法,其中該訊號產生模組包含一訊號產生器以及一驅動電路,該相位檢測方法更包含:藉由該訊號產生器產生一控制訊號;以及藉由該驅動電路根據該控制訊號產生該驅動電壓訊號。 The phase detecting method of claim 11, wherein the signal generating module comprises a signal generator and a driving circuit, the phase detecting method further comprises: generating a control signal by the signal generator; and by using the driving The circuit generates the driving voltage signal according to the control signal.
TW103139790A 2014-11-17 2014-11-17 Test system, phase detection device and method of the same TWI529399B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW103139790A TWI529399B (en) 2014-11-17 2014-11-17 Test system, phase detection device and method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103139790A TWI529399B (en) 2014-11-17 2014-11-17 Test system, phase detection device and method of the same

Publications (2)

Publication Number Publication Date
TWI529399B true TWI529399B (en) 2016-04-11
TW201619616A TW201619616A (en) 2016-06-01

Family

ID=56361435

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103139790A TWI529399B (en) 2014-11-17 2014-11-17 Test system, phase detection device and method of the same

Country Status (1)

Country Link
TW (1) TWI529399B (en)

Also Published As

Publication number Publication date
TW201619616A (en) 2016-06-01

Similar Documents

Publication Publication Date Title
JP6204504B2 (en) RF pulse synchronization, processing, and control with RF metrology
JP2010015262A (en) Electrostatic detection device and electrostatic detection method
JP5940389B2 (en) AC resistance measuring device and AC resistance measuring method
CN109061314A (en) A kind of method and device for the filter capacitor capacitance detecting inverter
JP2016099344A (en) Ground resistance measurement device and operation method thereof
CN107037255A (en) Voltage ripple detection circuit
RU2014153145A (en) CHECK THE CURRENT CONTROL OF THE PROCESS
US10521045B2 (en) Reference noise rejection improvement based on sample and hold circuitry
JP2017161240A (en) Ark detector
TWI529399B (en) Test system, phase detection device and method of the same
JP2017083379A (en) Impedance measuring device and impedance measuring method
JP6570981B2 (en) Measuring apparatus and measuring method
JP7009025B2 (en) Voltage measuring device, voltage measuring method
JP2007089277A (en) Leak detector for electric car
CN108574474B (en) Circuit for correcting influence of pulse signal on detection of instrument and meter
JP6315273B2 (en) Insulation state measuring device
KR20150108133A (en) Digital logic signal generating circuit for frequency measurement
JP3545886B2 (en) Insulation resistance measuring device
JP2011075507A (en) Capacitor capacitance determination method of power converter
CN109073691B (en) Method and device for measuring at least one characteristic of a coil, method and device for measuring the position of an operating member, and motor vehicle
JP4425648B2 (en) Ground fault detection device
CN204613287U (en) The current sampling circuit of hall device under periodically strong variation magnetic field
CN103777058A (en) Peak detection system and method for Hall gear sensor chip
CN105675987B (en) Test system and its phase detection device and method
CN115372847B (en) Control device and method of battery test equipment