CN103777058A - Peak detection system and method for Hall gear sensor chip - Google Patents
Peak detection system and method for Hall gear sensor chip Download PDFInfo
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- CN103777058A CN103777058A CN201410062309.3A CN201410062309A CN103777058A CN 103777058 A CN103777058 A CN 103777058A CN 201410062309 A CN201410062309 A CN 201410062309A CN 103777058 A CN103777058 A CN 103777058A
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Abstract
The invention discloses a peak detection system and method for a Hall gear sensor chip. The peak detection system comprises an analog peak detector, an analog-digital converter, a digital peak detector, a control unit and a digital-analog converter, wherein the analog peak detector is used for receiving a Hall signal and detecting the peak of the Hall signal according to the clock frequency of the analog peak detector, the analog-digital converter is used for converting an analog peak signal output by the analog peak detector into a digital signal and inputting the digital signal into the digital peak detector, the digital peak detector is used for detecting a digital peak according to the clock frequency of the digital peak detector, and the digital-analog converter is used for converting the digital peak signal into the analog peak signal again and outputting the analog peak signal into a next-stage procedure for processing. By using the basic structure of two stages of peak detectors and adopting a corresponding timing sequence matched with the basic structure, voltage peak signal attenuation caused by electric leakage of a compositor can be effectively avoided for the analog peak detector, and voltage peak signals can be accurately kept by the digital peak detector for a long time.
Description
Technical field
The invention belongs to peak detection technology field, relate to a kind of peak detection system, relate in particular to a kind of peak detection system that is applied to Hall gear sensor chip; Meanwhile, the invention still further relates to a kind of peak-value detection method that is applied to Hall gear sensor chip.
Background technology
Hall gear sensor be utilize Hall effect principle by hall sensing element, amplifier, compensating circuit and other electronic circuits, utilize integrated circuit processing technique to be integrated on a chip and make, it has, and volume is little, the life-span long, non-contact inductive and frequency advantages of higher are widely used in the fields such as automotive electronics, Weaving device, Industry Control.Hall gear sensor is the important member of Hall element family, and it exports the digital signal with certain window according to the variable quantity of external magnetic field, can be used to the fields such as camshaft sensing, position transducer and speed measurement of angle.
Current many application need Hall gear sensor to have extremely wide in range speed sensing range, as application such as automobile camshaft sensing, the accurate measurement of angle of industry.In low-speed applications, a part of Hall gear sensor is owing to there is no zero-speed measuring ability, thereby has lower limit cannot reach application requirements to the rotating speed of testee.And the Hall gear sensor with zero-speed measuring ability there is no minimum speed requirement to testee, thereby can detect motion change very slowly.Realize zero-speed measuring ability at chip internal, a difficult point is accurately to detect peak value long-time preservation of hall signal.This is the emphasis point of this patent.
Refer to Fig. 1, Fig. 1 discloses a kind of common voltage peak detection method.High frequency clutter the output reference signal of low-pass filter a1 filtering hall signal.Totalizer a2 adds that on the basis of reference signal a voltage constant a3 produces reference signal.Last comparer a4 compares hall signal and reference signal and exports peak signal.
Conventionally hall signal can be subject to being permitted multifactorial interference, comprises the fluctuation of power supply, interference, the small shake of testee etc. of high frequency magnetic field.Therefore,, if reference signal is to be produced by reference signal making alive constant, the amplitude variations of peak signal may cause that testing result is inaccurate.
Refer to Fig. 2, Fig. 2 discloses another kind of common voltage peak detection method.Peak detctor b1 detects the crest voltage of hall signal and produces initial spike signal, simultaneously by high frequency clutter the output reference signal of low-pass filter b2 filtering hall signal.Voltage computing unit b3 uses totalizer b4 that peak signal and reference signal phase adduction are produced to reference signal by b5 rectification.Last comparer b6 compares hall signal and reference signal and exports peak signal.
In the method, long if peak detctor stores time to peak, due to the electric leakage of electric capacity, will the signal storing be decayed.If electric capacity is strengthened to reduce the impact that electric leakage brings, the response time of peak detctor will be elongated, may produce undetected in the situation that of high-frequency work.
In view of this, nowadays in the urgent need to designing a kind of peak value long-time mode of preserving that detects hall signal, to overcome the above-mentioned defect of prior art.
Summary of the invention
Technical matters to be solved by this invention is: provide a kind of peak detection system that is applied to Hall gear sensor chip, for a long time stored voltage peak value avoid the detection error causing due to leaky condenser.
In addition, the present invention also provides a kind of peak-value detection method that is applied to Hall gear sensor chip, for a long time stored voltage peak value avoid the detection error causing due to leaky condenser.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
Be applied to a peak detection system for Hall gear sensor chip, described peak detection system comprises: simulated peak detecting device, analog to digital converter, digital peak value detector, control module, digital to analog converter; Described control module is connecting analog peak detctor, analog to digital converter, digital peak value detector respectively;
Described simulated peak detecting device is in order to receive hall signal and to detect the peak value of hall signal according to the clock frequency of himself;
Described analog to digital converter is in order to be converted into the simulated peak signal of simulated peak detecting device output digital signal and to input to digital peak value detector;
Described digital peak value detector detects digital peak according to the clock frequency of himself;
Described control module produces all kinds of control signals;
Described digital to analog converter is again converted into digital peak signal simulated peak signal and exports next stage processing to.
As a preferred embodiment of the present invention, described simulated peak detecting device comprises the first detecting unit, the second detecting unit and multiplexer; The first detecting unit, the second detecting unit adopt identical structure but work in different time;
Using two groups of detecting units is for mating die number converter; In the time that one group of detecting unit is exported simulated peak signal to analog to digital converter, another group detecting unit continues detection peak signal and prevents undetected; The first detecting unit is by the first reset signal control, and the second detecting unit is by the second reset signal control;
Multiplexer receives the output signal of the first detecting unit and the second detecting unit and exports corresponding signal by selection signal controlling.
As a preferred embodiment of the present invention, in the time that the first reset signal is low level, the first detecting unit detects hall signal peak value, in the time that the first reset signal A is high level, capacitor discharge is resetted;
In the time that the second reset signal is low level, the second detecting unit detects hall signal peak value, in the time that the second reset signal is high level, capacitor discharge is resetted;
At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state;
At the negative edge of each ADC sampling clock very first time t1 in advance, the first reset signal and the second reset signal become low level and at the negative edge of next ADC pulse and delay the second time t2 and become high level.
As a preferred embodiment of the present invention, the clock frequency of the clock frequency ratio simulated peak detecting device of described digital peak value detector is low.
As a preferred embodiment of the present invention, the control signal that described control module produces comprises: the clock signal of selecting signal, the first reset signal, the second reset signal, analog to digital converter sampling clock and digital peak value detector.
Be applied to a peak-value detection method for Hall gear sensor chip, described peak-value detection method comprises:
Simulated peak detecting device receives hall signal and detects the peak value of hall signal according to the clock frequency of himself;
Analog to digital converter is converted into the simulated peak signal of simulated peak detecting device output digital signal and inputs to digital peak value detector;
Digital peak value detector detects digital peak according to the clock frequency of himself;
Control module produces all kinds of control signals;
Digital to analog converter is again converted into digital peak signal simulated peak signal and exports next stage processing to.
As a preferred embodiment of the present invention, described simulated peak detecting device comprises the first detecting unit, the second detecting unit and multiplexer; The first detecting unit, the second detecting unit adopt identical structure but work in different time;
Using two groups of detecting units is for mating die number converter;
Described peak-value detection method comprises:
In the time that one group of detecting unit is exported simulated peak signal to analog to digital converter, another group detecting unit continues detection peak signal and prevents undetected; The first detecting unit is by the first reset signal control, and the second detecting unit is by the second reset signal control;
Multiplexer receives the output signal of the first detecting unit and the second detecting unit and exports corresponding signal by selection signal controlling.
As a preferred embodiment of the present invention, described method further comprises:
In the time that the first reset signal is low level, the first detecting unit detects hall signal peak value, in the time that the first reset signal A is high level, capacitor discharge is resetted;
In the time that the second reset signal is low level, the second detecting unit detects hall signal peak value, in the time that the second reset signal B is high level, capacitor discharge is resetted;
At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state;
At the negative edge of each ADC sampling clock very first time t1 in advance, the first reset signal and the second reset signal become low level and at the negative edge of next ADC pulse and delay the second time t2 and become high level.
As a preferred embodiment of the present invention, the clock frequency of the clock frequency ratio simulated peak detecting device of described digital peak value detector is low.
As a preferred embodiment of the present invention, the control signal that described control module produces comprises: the clock signal of selecting signal, the first reset signal, the second reset signal, analog to digital converter sampling clock and digital peak value detector.
Beneficial effect of the present invention is: the peak detection system that is applied to Hall gear sensor chip and method that the present invention proposes, by using the basic structure of two-stage peak detctor and coordinating corresponding time sequence, simulated peak detecting device can effectively be avoided the voltage peak signal attenuation causing due to the electric leakage of capacitor, and digital peak value detector can be preserved voltage peak signal for a long time exactly.
In addition, simulated peak detecting device is worked under high sample frequency, can detect in real time, exactly hall signal.Compare and adopt simulated peak detecting device to preserve peak signal, digital peak value detector can be avoided the peak-data mistake causing due to capacity fall off, can preserve for a long time.
Accompanying drawing explanation
Fig. 1 is a kind of common voltage peak detection method.
Fig. 2 is another kind of common voltage peak detection method.
Fig. 3 is the composition schematic diagram of peak detection system of the present invention.
Fig. 4 is the composition schematic diagram of simulated peak detecting device in peak detection system of the present invention.
Fig. 5 is some work sequential chart of the present invention.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment mono-
Refer to Fig. 3, the present invention has disclosed a kind of peak detection system that is applied to Hall gear sensor chip, and described peak detection system comprises: simulated peak detecting device c1, analog to digital converter c2, digital peak value detector c3, control module c4 and digital to analog converter c5.
Simulated peak detecting device c1 receives hall signal and detects the peak value of hall signal according to the clock frequency of himself.Because the clock frequency of simulated peak detecting device c1 is very fast, there is no need to avoid the long-time voltage attenuation causing that stores with large electric capacity, simulated peak detecting device c1 can have response frequency fast thus.
Analog to digital converter c2 is converted into the simulated peak signal of simulated peak detecting device c1 output digital signal and inputs to digital peak value detector c3, and digital peak value detector c3 detects digital peak according to the clock frequency of himself (clock frequency than simulated peak detecting device c1 is low).
Control module c4 produces all kinds of control signal examples, as selected the clock signal of signal, reset signal A, reset signal B, analog to digital converter sampling clock and digital peak value detector.Digital to analog converter c5 is again converted into digital peak signal simulated peak signal and exports next stage processing to.
Refer to Fig. 4, Fig. 4 is the functional schematic of simulated peak detecting device c1 in the present invention.Simulated peak detecting device c1 comprises two groups of detecting units and multiplexer c13, and two groups of detecting units are respectively the first detecting unit c11 and the second detecting unit c12.The first detecting unit c11 adopts identical structure but works in different time with the second detecting unit c12.
Using two groups of detecting units is for mating die number converter c2.In the time that one group of detecting unit is exported simulated peak signal to analog to digital converter c2, another group detecting unit continues detection peak signal and prevents undetected.The first detecting unit c11 is controlled by reset signal A, and the second detecting unit c12 is controlled by reset signal B.Multiplexer c13 receives the output signal of the first detecting unit c11 and the second detecting unit c12 and exports corresponding signal by selection signal controlling.
Refer to Fig. 5, Fig. 5 is some work sequential chart of the present invention.In the time that reset signal A is low level, the first detecting unit c11 detects hall signal peak value, in the time that reset signal A is high level, capacitor discharge is resetted.Similarly, in the time that reset signal B is low level, the second detecting unit c12 detects hall signal peak value, in the time that reset signal B is high level, capacitor discharge is resetted.At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state.At the negative edge of each ADC sampling clock very first time t1 in advance, reset signal A and reset signal B become low level and at the negative edge of next ADC pulse and delay the second time t2 and become high level.
Embodiment bis-
The present invention also discloses a kind of peak-value detection method that is applied to Hall gear sensor chip, can be in conjunction with Fig. 3, and described peak-value detection method comprises (execution sequence between each step can be adjusted or intert):
Simulated peak detecting device c1 receives hall signal and detects the peak value of hall signal according to the clock frequency of himself.Because the clock frequency of simulated peak detecting device c1 is very fast, there is no need to avoid the long-time voltage attenuation causing that stores with large electric capacity, simulated peak detecting device c1 can have response frequency fast thus;
Analog to digital converter c2 is converted into the simulated peak signal of simulated peak detecting device c1 output digital signal and inputs to digital peak value detector c3, and digital peak value detector c3 detects digital peak according to the clock frequency of himself (clock frequency than simulated peak detecting device c1 is low);
Control module c4 produces all kinds of control signals, for example, select the clock signal of signal, reset signal A, reset signal B, analog to digital converter sampling clock and digital peak value detector.Digital to analog converter c5 is again converted into digital peak signal simulated peak signal and exports next stage processing to.
In the present embodiment, as shown in Figure 4, simulated peak detecting device c1 comprises two groups of detecting units and multiplexer c13, and two groups of detecting units are respectively the first detecting unit c11 and the second detecting unit c12.The first detecting unit c11 adopts identical structure but works in different time with the second detecting unit c12.
Using two groups of detecting units is for mating die number converter c2.Described peak-value detection method comprises: in the time that one group of detecting unit is exported simulated peak signal to analog to digital converter c2, another group detecting unit continues detection peak signal and prevents undetected.The first detecting unit c11 is controlled by reset signal A, and the second detecting unit c12 is controlled by reset signal B.Multiplexer c13 receives the output signal of the first detecting unit c11 and the second detecting unit c12 and exports corresponding signal by selection signal controlling.
As shown in Figure 5, described method further comprises:
In the time that the first reset signal A is low level, the first detecting unit detects hall signal peak value, in the time that the first reset signal A is high level, capacitor discharge is resetted;
In the time that the second reset signal B is low level, the second detecting unit detects hall signal peak value, in the time that the second reset signal B is high level, capacitor discharge is resetted;
At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state;
At the negative edge of each ADC sampling clock very first time t1 in advance, the first reset signal and the second reset signal become low level and at the negative edge of next ADC pulse and delay the second time t2 and become high level.
In sum, the peak detection system that is applied to Hall gear sensor chip and method that the present invention proposes, by using the basic structure of two-stage peak detctor and coordinating corresponding time sequence, simulated peak detecting device can effectively be avoided the voltage peak signal attenuation causing due to the electric leakage of capacitor, and digital peak value detector can be preserved voltage peak signal for a long time exactly.
In addition, simulated peak detecting device is worked under high sample frequency, can detect in real time, exactly hall signal.Compare and adopt simulated peak detecting device to preserve peak signal, digital peak value detector can be avoided the peak-data mistake causing due to capacity fall off, can preserve for a long time.
Here description of the invention and application is illustrative, not wants scope of the present invention to limit in the above-described embodiments.Here the distortion of disclosed embodiment and change is possible, and for those those of ordinary skill in the art, the various parts of the replacement of embodiment and equivalence are known.Those skilled in the art are noted that in the situation that not departing from spirit of the present invention or essential characteristic, and the present invention can be with other form, structure, layout, ratio, and realize with other assembly, material and parts.In the situation that not departing from the scope of the invention and spirit, can carry out other distortion and change to disclosed embodiment here.
Claims (10)
1. a peak detection system that is applied to Hall gear sensor chip, is characterized in that, described peak detection system comprises: simulated peak detecting device, analog to digital converter, digital peak value detector, control module, digital to analog converter; Described control module is connecting analog peak detctor, analog to digital converter, digital peak value detector respectively;
Described simulated peak detecting device is in order to receive hall signal and to detect the peak value of hall signal according to the clock frequency of himself;
Described analog to digital converter is in order to be converted into the simulated peak signal of simulated peak detecting device output digital signal and to input to digital peak value detector;
Described digital peak value detector detects digital peak according to the clock frequency of himself;
Described control module produces all kinds of control signals;
Described digital to analog converter is again converted into digital peak signal simulated peak signal and exports next stage processing to.
2. the peak detection system that is applied to Hall gear sensor chip according to claim 1, is characterized in that:
Described simulated peak detecting device comprises the first detecting unit, the second detecting unit and multiplexer; The first detecting unit, the second detecting unit adopt identical structure but work in different time;
Using two groups of detecting units is for mating die number converter; In the time that one group of detecting unit is exported simulated peak signal to analog to digital converter, another group detecting unit continues detection peak signal and prevents undetected; The first detecting unit is by the first reset signal control, and the second detecting unit is by the second reset signal control;
Multiplexer receives the output signal of the first detecting unit and the second detecting unit and exports corresponding signal by selection signal controlling.
3. the peak detection system that is applied to Hall gear sensor chip according to claim 2, is characterized in that:
In the time that the first reset signal is low level, the first detecting unit detects hall signal peak value, in the time that the first reset signal is high level, capacitor discharge is resetted;
In the time that the second reset signal is low level, the second detecting unit detects hall signal peak value, in the time that the second reset signal is high level, capacitor discharge is resetted;
At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state;
At the negative edge of each ADC sampling clock very first time t1 in advance, the first reset signal and the second reset signal become low level and at the negative edge of next ADC pulse and delay time the 2nd t2 and become high level.
4. the peak detection system that is applied to Hall gear sensor chip according to claim 1, is characterized in that:
The clock frequency of the clock frequency ratio simulated peak detecting device of described digital peak value detector is low.
5. the peak detection system that is applied to Hall gear sensor chip according to claim 1, is characterized in that:
The control signal that described control module produces comprises: the clock signal of selecting signal, the first reset signal, the second reset signal, analog to digital converter sampling clock and digital peak value detector.
6. a peak-value detection method that is applied to Hall gear sensor chip, is characterized in that, described peak-value detection method comprises:
Simulated peak detecting device receives hall signal and detects the peak value of hall signal according to the clock frequency of himself;
Analog to digital converter is converted into the simulated peak signal of simulated peak detecting device output digital signal and inputs to digital peak value detector;
Digital peak value detector detects digital peak according to the clock frequency of himself;
Control module produces all kinds of control signals;
Digital to analog converter is again converted into digital peak signal simulated peak signal and exports next stage processing to.
7. the peak-value detection method that is applied to Hall gear sensor chip according to claim 6, is characterized in that:
Described simulated peak detecting device comprises the first detecting unit, the second detecting unit and multiplexer; The first detecting unit, the second detecting unit adopt identical structure but work in different time;
Using two groups of detecting units is for mating die number converter;
Described peak-value detection method comprises:
In the time that one group of detecting unit is exported simulated peak signal to analog to digital converter, another group detecting unit continues detection peak signal and prevents undetected; The first detecting unit is by the first reset signal control, and the second detecting unit is by the second reset signal control;
Multiplexer receives the output signal of the first detecting unit and the second detecting unit and exports corresponding signal by selection signal controlling.
8. the peak-value detection method that is applied to Hall gear sensor chip according to claim 7, is characterized in that:
Described method further comprises:
In the time that the first reset signal is low level, the first detecting unit detects hall signal peak value, in the time that the first reset signal is high level, capacitor discharge is resetted;
In the time that the second reset signal is low level, the second detecting unit detects hall signal peak value, in the time that the second reset signal is high level, capacitor discharge is resetted;
At the negative edge of each ADC sampling clock and delay the 3rd time t3, select signal to change its level state;
At the negative edge of each ADC sampling clock very first time t1 in advance, the first reset signal and the second reset signal become low level and at the negative edge of next ADC pulse and delay the second time t2 and become high level.
9. the peak-value detection method that is applied to Hall gear sensor chip according to claim 6, is characterized in that:
The clock frequency of the clock frequency ratio simulated peak detecting device of described digital peak value detector is low.
10. the peak-value detection method that is applied to Hall gear sensor chip according to claim 6, is characterized in that:
The control signal that described control module produces comprises: the clock signal of selecting signal, the first reset signal, the second reset signal, analog to digital converter sampling clock and digital peak value detector.
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| CN201410062309.3A CN103777058A (en) | 2014-02-24 | 2014-02-24 | Peak detection system and method for Hall gear sensor chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
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| JPS63209099A (en) * | 1987-02-25 | 1988-08-30 | Teru Saamuko Kk | Peak value detection circuit |
| US20020008505A1 (en) * | 2000-06-07 | 2002-01-24 | Chi-Ming Chen | Peak detector |
| CN1516118A (en) * | 2003-01-07 | 2004-07-28 | 联发科技股份有限公司 | Double-stage peak value detector |
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2014
- 2014-02-24 CN CN201410062309.3A patent/CN103777058A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63209099A (en) * | 1987-02-25 | 1988-08-30 | Teru Saamuko Kk | Peak value detection circuit |
| US20020008505A1 (en) * | 2000-06-07 | 2002-01-24 | Chi-Ming Chen | Peak detector |
| CN1516118A (en) * | 2003-01-07 | 2004-07-28 | 联发科技股份有限公司 | Double-stage peak value detector |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
| CN108761310B (en) * | 2018-05-25 | 2021-03-12 | 合肥本源量子计算科技有限责任公司 | Quantum chip test method |
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