TWI527214B - Silicon-controlled rectifier for esd protection and method for manufacturing silicon-controlled rectifier for esd protection - Google Patents

Description

Remotely controlled rectifier with ESD protection, and method of manufacturing a controlled rectifier for use as an ESD protection circuit

The present invention relates to electrostatic discharge protection technology.

Electrostatic discharge (ESD) pulses are accidental, abruptly transferred to the electronic device by the outside world (approx. using a mannequin or machine model), or moved to the outside by an electronic device (approximated using a charging device model) energy of. ESD events can cause damage to the electronic device. For example, high voltage will cause the gate of the transistor to oxidize, and high current will cause the active region of the device to melt, which is the cause of the failure of the junction. When an electronic device is damaged due to an ESD event, it may become unworkable or even completely paralyzed.

The present invention provides a silicon controlled rectifier (SCR) including a current path for directing current from an SCR anode to an SCR cathode; wherein the current path includes: a first vertical current path portion coupled to the An SCR anode; a second vertical current path portion coupled to the SCR cathode; a horizontal current path portion below the first and second vertical current path portions, wherein the horizontal current path portion includes a first well region With one a second well region, the first well region and the second well region are joined to a junction surface, and the junction surface is stacked on a first plane, wherein the first well region and the second well region cooperate with each other And a distance between the first vertical current path portion and the second vertical current path portion.

The present invention further provides a susceptor-controlled rectifier (SCR) formed on a substrate, including an SCR anode, an SCR cathode, and a current path for directing current from the SCR anode to the SCR cathode; wherein the current path includes a first vertical current path portion coupled to the SCR anode and having a first conductivity type; a second vertical current path portion coupled to the SCR cathode and having a reverse polarity to the first conductivity type a second conductivity type, wherein the second vertical current path portion and the first vertical current path portion are horizontally disposed in the same plane, and the two are horizontally spaced apart by a distance; and a horizontal current path portion is disposed in the first a vertical current path portion and the second vertical current path portion, and spanning a distance between the first vertical current path portion and the second vertical current path portion, the horizontal current path portion comprising: a first a well region coupled to the first vertical current path portion and disposed under the first vertical current path portion, wherein the first well has the second conductivity And a second well region coupled to the second vertical current path portion and disposed under the second vertical current path portion, wherein the first well and the second well meet at a junction, and the connection The faces are aligned with a first plane, wherein the second well has the first conductivity type.

The present invention further provides a method of fabricating a silicon controlled rectifier (SCR) for use as an ESD protection circuit, comprising: forming an n-well having a first n-doping concentration in a semiconductor substrate; forming A p-well has a first p-doping concentration in a semiconductor substrate, wherein the p-well and the n-well meet at a junction; forming an anode region above the n-well.

100‧‧‧ integrated circuit

102‧‧‧ESD sensitive circuit

104‧‧‧IC pin

106‧‧‧ESD protection circuit

108‧‧‧ESD pulse

110‧‧‧ coupling points

112‧‧‧First power rail

114‧‧‧Second power rail

116‧‧‧First SCR

118‧‧‧Second SCR

120‧‧‧Arrow

122‧‧‧Arrow

124‧‧‧PNPN structure

126‧‧‧Double carrier junction transistor

128‧‧‧Double carrier junction transistor

200‧‧‧SCR

202‧‧‧Semiconductor matrix

204‧‧‧SCR anode

206‧‧‧SCR cathode

208‧‧‧ Current path

208a‧‧‧First vertical current path section

208b‧‧‧second vertical current path section

208c‧‧‧Horizontal current path section

210‧‧‧First Well Area

212‧‧‧Second well area

214‧‧‧Connected

218‧‧‧First w-shaped projections

220‧‧‧Upper

222‧‧‧Under

224‧‧‧First vertical current path recess

224a‧‧‧First vertical current path recess

224b‧‧‧First vertical current path recess

226a‧‧‧First well zone contact point

226b‧‧‧First well zone contact point

228‧‧‧Second w-shaped projections

230‧‧‧Upper

232‧‧‧Under

234‧‧‧second vertical current path recess

234b‧‧‧second vertical current path recess

236a‧‧‧Second well zone contact point

236b‧‧‧Second well zone contact point

600‧‧‧SCR

602‧‧U type projections

604‧‧‧u type projections

606‧‧‧Internal u-shaped surface

608‧‧‧External u-shaped surface

610‧‧‧ Well contact points

612‧‧‧ recesses

614‧‧‧ first plane

616‧‧‧ second plane

618‧‧‧SCR

620‧‧‧First vertical current path section

622‧‧‧First u-shaped projection

624‧‧‧Second u-shaped projections

626‧‧‧ Third u-shaped projection

628‧‧‧Longitudinal components

630, 632, 634, 636‧‧ ‧ cross members

700‧‧‧ESD protection device

702‧‧‧First SCR device

704‧‧‧Second SCR device

706‧‧‧ Third SCR device

708‧‧‧4th SCR device

710‧‧‧First I/O pin

712‧‧‧Second I/O pin

714‧‧‧Power rail ESD clamp circuit

716‧‧‧ positive value for VSS type ESD pulse

718‧‧‧ Negative value for VSS type ESD pulse

720‧‧‧ positive value for VSS type ESD pulse

722‧‧‧ Negative value for VSS type ESD pulse

724‧‧‧Pin to Pin Type ESD Pulse

1002~1012‧‧‧Steps

FIG. 1A is a schematic diagram of an integrated circuit having an ESD sensitive circuit and an ESD protection circuit in an embodiment.

Figure 1B is another perspective view of the SCR used in the ESD protection circuit of Figure 1A in some embodiments.

Figure 2A is a schematic illustration of an SCR with w-type protection in certain embodiments.

Figure 2B is a first and second plane symmetric on the SCR in Figure 2A.

Figure 3 is a top view of the insulating region in Figure 2A.

Figure 4 is a cross-sectional side view of the SCR of Figure 3 in an embodiment.

Figure 5 is a cross-sectional side view of the SCR of Figure 3 in an embodiment.

Fig. 6A is a schematic view of an SCR having u-type protection in other embodiments.

Figure 6B is a schematic diagram of an SCR with multiple u-type guards in other embodiments.

Figures 7A through 7B are circuits including four SCRs that can shunt ESC pulses.

Figure 8 is a top view of the corresponding SCR of Figure 7A.

Figure 9 is a schematic illustration of how current passes through the SCR in certain embodiments.

Figure 10 is a flow diagram of a method of fabricating an SCR for use as an ESD protection circuit.

Various embodiments of the present invention will be described below with reference to the accompanying drawings, in which The same symbols are used to denote the same elements, and the illustrations are not presented in actual dimensions.

1A is an embodiment of an integrated circuit (IC) 100 that includes an ESD-sensitive circuit 102. In some embodiments, the integrated circuit also includes an ESD-sensitive circuit 102 coupled to the external IC pin 104 of a circuit component (not shown). In some embodiments, the IC pins are pads, solder bumps, or various structures capable of electrically connecting the ESD sensitive circuit 102 and other circuits; the interface between the IC 100 and an external circuit, or the internal circuit of the IC 100 The interface between components. For example, in some embodiments IC pin 104 is a power supply pin for supplying a DC supply voltage (eg, VDD or VSS) to ESD sensitive circuit 102; or an input/output (I/O) A pin that provides an input or output signal.

In order to protect the ESD sensitive circuit 102 from damage by the ESD pulse 108, an ESD protection circuit 106 is included in the IC 100. In particular, the ESD protection circuit 106 can adjust the voltage at the coupling point 110 such that the voltage does not rise to the point where the semiconductor device in the ESD sensitive circuit 102 is damaged. In some embodiments, the ESD protection circuit 106 can limit the circuit on the coupling contact 110 to an extreme operational configuration. In some embodiments, the highest voltage across the coupling contact 110 is clamped to a generally normal rail voltage slightly above the first supply rail 112 (eg, VDD), while the lowest voltage is clamped at a slightly lower voltage. A zero volt line of the second power rail 114 (eg, VSS or ground voltage).

In the embodiment of FIG. 1A, ESD protection circuit 106 uses a first SCR and a second SCR 116, 118. The first SCR 116 is disposed between the node 110 and the first power rail 112 , and the second SCR 118 is disposed between the node 110 and the second power rail 114 . As shown in FIG. 1B, the first and second SCRs 116 and 118 respectively have There is an anode and a cathode, and a PNPN structure 124 is formed between the two poles, which in some embodiments represents a pair of cross-coupled bi-carrier junction transistors (BJT) 126 or 128.

When the 1A map is in a normal operating state (i.e., no ESD pulses are present), the first and second SCRs 116, 118 are reverse biased. Thus, under normal operating conditions, the first and second SCRs 116, 118 are not conducting, and the power flow is not diverted by the ESD sensitive circuit 102 to the IC pin 104 (or vice versa). However, when a large positive ESD pulse occurs on the IC pin 104, the pulse causes the input voltage of the node 110 to rise above the voltage of the first power rail 112; and the first SCR 116 becomes a forward voltage transformer and will The energy of the ESD pulse 108 is split across it (see arrow 120). Similarly, when a large negative ESD pulse occurs on the IC pin 104, the pulse causes the input voltage of the node 110 to drop below the ground voltage; and the second SCR 118 becomes a forward voltage transformer and the ESD pulse 108 Energy is split on it (see arrow 122). Thus, the first and second SCRs 116, 118 can selectively shunt and consume the energy of the ESD pulse, but do not have a significant impact on the normal operation of the circuit without the ESD pulse. Unfortunately, the clamp voltage or trigger voltage of conventional ESD protection techniques is higher than the ideal voltage value. In view of these disadvantages, the present invention provides a technical solution for reducing the clamping voltage and the trigger voltage.

Returning now to Figures 2A-2B through 5, it can be seen from the figure that the exemplary SCR 200 provides a lower clamping voltage and trigger voltage than conventional SCR devices. Thus, when the SCR 200 is integrated with an ESD protection circuit (as shown by the circuit in IC 100 in Figure 1A), the resulting circuit has more enhanced ESD protection.

Referring to FIG. 2A, the SCR 200 is formed on a semiconductor substrate 202. The semiconductor substrate 202 can be a germanium matrix, a germanium on an insulating substrate, or various other semiconductor substrates. The SCR 200 includes an SCR anode 204, an SCR cathode 206, and a current path 208 that directs current from the SCR anode 204 to the SCR cathode 206. Current path 208 includes a first vertical current path portion 208a; a second vertical current path portion 208b spaced a distance from first vertical current path portion 208a; and a horizontal current path portion 208c extending from the first Below the second vertical current path portion, the first and second vertical current path portions may be coupled to each other. For clarity of illustration, the dielectric regions are removed from Figures 2A through 2B (compare Figures 3 through 5, which illustrate SCR 200 with dielectric region 250).

The horizontal current path portion 208c includes a first well region 210 and a second well region 212, which are joined to the junction 214. The first well region 210 has a first conductivity type (eg, n-type) and the second well region 212 has an opposite second conductivity type (eg, p-type). As shown in FIG. 2B, the junction 214 is at least partially flat along the first plane 216.

Referring to FIG. 2A, a first vertical current path portion 208a is coupled to the SCR anode 204 and includes a first elongated semiconductor body having opposing sidewalls. Vertical current path portion 208a includes a first w-shaped protrusion 218 that extends vertically upward from the substrate 202. The first w-shaped protrusion 218 includes an upper layer 220 having a second conductivity type (e.g., P+) and optionally a lower layer 222, which in the illustrated embodiment is identical to the first well region 210 Doping (eg, N). In this embodiment, the first w-shaped projection 218 includes a pair of first vertical current path recesses (224a, 224b), the recesses being inwardly from one of the sidewalls of the first w-shaped projection 218, respectively. extend. The first well region contact points (226a, 226b) are respectively assigned Placed in the first vertical current path recess (224a, 224b). The first well region contact points 226a, 226b have the same doping profile as the first well region 210. However, in some embodiments, the first well region contact points 226a, 226b have a higher doping concentration (eg, N+).

The second vertical current path portion 208b is coupled to the cathode 206 and includes a second elongated semiconductor body having opposing sidewalls. Vertical current path portion 208b includes a second w-shaped protrusion 228 that extends vertically upward from substrate 202. The second w-shaped protrusion 228 includes an upper layer 230 having a first conductivity type (eg, N+), and optionally a lower layer 232 having the same dopant as the second well region 212 (eg, P ). In this embodiment, the second w-shaped projection 228 includes a pair of second vertical current path recesses 234a, 234b that extend inwardly from one of the sidewalls of the second w-shaped projection 228, respectively. The second well region contact points (236a, 236b) are respectively disposed in the second vertical current path recesses (234a, 234b). In some embodiments, the second well region contact points 236a, 236b have the same doping profile as the second well region 212. In some embodiments, the second well region contact points 236a, 236b have a higher doping concentration (eg, P+) than the second well region 212. In some embodiments, the second well contact points 236a, 236b are shorted to the first well contact point 226a 226b, respectively, as shown.

As shown in FIG. 2B, the first vertical current path portion 208a and the second vertical current path portion 208b are mirror-symmetrical to each other with the first plane 216. The first and second vertical current path portions 208a, 208b are also mirror symmetrical with respect to the second plane 240 and perpendicular to the first plane 216. In some embodiments, the second plane 240 is disposed at the center of the w-shaped projections 218, 228 and is equidistantly spaced between the first and second well region contact points 226a, 226b.

Figures 3 through 5 are additional views of the SCR 200 with an exemplary doping configuration. The SCRs 200 in FIGS. 3 to 5 have the same partitions and the same reference numerals as shown in FIGS. 2A to 2B, but the insulating layers in FIGS. 2A to 2B are shown for convenience of explanation. 250 removed. For example, FIG. 3 illustrates the anode 204; the cathode 206; the n-well 210 and the p-well 212 meet a junction 214; and the first and second w-shaped projections 218, 228. 4 is a cross-sectional view of FIG. 3, showing a substrate 202; an anode 204; a cathode 206; a current path (208a, 208b, 208c); a first well region 210; and a second well region 212. 5 is a cross-sectional view of FIG. 3; the substrate 202; the anode 204; the cathode 206; and the current paths (208a, 208b, 208c); the first well region 210; and the second well region 212. Although the first conductivity type is represented by an n-type doping type and the second conductivity type is represented by a p-type impurity type in these embodiments, it is understood that in other embodiments, the first conductivity type It may also be p-type, and the second conductivity type may also be n-type. In other words, in other embodiments not described, the conductivity indications in Figures 3 through 5 can be exchanged.

Although the first and second vertical current path portions 208a, 208b are depicted as w-shaped projections in FIGS. 2A-2B and 3D through 5, in other embodiments, the first and the first The two vertical current path portions may have other shapes and are not necessarily limited to the foregoing embodiments. For example, in the SCR 600 described in FIG. 6A, the first and second vertical current path portions are u-shaped protrusions (602, 604) that extend vertically upward from the substrate. Each u-shaped protrusion (e.g., 602) includes an inner u-shaped surface (e.g., 606) and an outer u-shaped surface (e.g., 608) concentric therewith. The well contact (e.g., 610) is then fabricated into a recess (e.g., 612) defined by the inner u-shaped surface. Similar to the w-shaped projections of FIG. 2A and FIG. 2B, the u-shaped projections in FIG. 6A are mirror-symmetrical to each other in the first plane 614. Thus, it is also symmetrical to each other in the second plane 616. In other embodiments, F-shaped protrusions or π-type protrusions may also be employed.

Further, as shown in the embodiment of Fig. 6B, the multiple u-shaped projections (or/and multiple w-shaped projections) are adjacent to each other. For example, FIG. 6B illustrates an example SCR 618 in which the first and second vertical current path portions are each composed of three u-shaped protrusions. For example, the first vertical current path portion 620 includes first, second, and third u-shaped protrusions (622, 624, and 626). In the embodiment of Figure 6B, the sidewalls of adjacent u-shaped, or w-shaped projections are compacted or merged with each other. The structure of Figure 6B (and other similar structures described herein) can also be a longitudinal member (e.g., 628) that extends perpendicularly relative to the first plane 614, wherein the cross members (e.g., 630, 632, 634, 636) Vertically span the longitudinal members at regular intervals. Although in the implementation side of FIG. 6B, the cross members (eg, the sides or feet of the u-shaped or w-shaped projections) extend in the same direction by the longitudinal members 628, in other embodiments, The cross members may extend in different directions from the longitudinal members and may have the same or different lengths from each other. Moreover, although the number of cross members extending from the longitudinal members 628 in FIG. 6B is four, it will be appreciated that in other embodiments, the number of cross members is not necessarily limited thereto.

While this embodiment occupies a relatively large area relative to the previously described embodiments, embodiments employing such u-shaped or w-shaped projections are advantageous depending on device parameters and the energy of the ESD pulse. . In addition, although the described w-type and u-shaped protrusions exhibit a square shape at the corners of the intersection of the vertical faces, in many process technologies, the corners can be made more rounded and the sides thereof can be slightly less vertical. For example, the sidewalls can be inclined relative to the surface of the substrate such that the two intersect at a less perpendicular intersection angle.

7A is an embodiment of an ESD protection device 700 that includes four SCRs (702, 704, 706, 708) disposed between first and second IC pins (710, 712) . The four SCR devices each have a PNPN structure that collectively dissipates the energy of the ESD pulses. As shown in Figure 7B, each pin-to-pin path includes a diode string from the first I/O pin to the second I/O pin. For example, in some ESD situations, current flows from the first I/O pin 710 to the second SCR device 704, through the third SCR device 706, and finally from the second I/O pin 712. In other ESD situations, current flows from the second I/O pin 712 to the fourth SCR device 708, through the first SCR device 702, and finally from the first I/O pin 710.

The ESD protection device of Figure 7 is modified in Figure 8. The ESD protection device 800 includes four SCRs (SCR1, SCR2, SCR3, SCR4) each including a PNPN structure that is comprised of one or more w-shaped protrusions and extends vertically from the semiconductor substrate in which the ESD device is located. There are special arrangements between the four SCRs and the two I/O pins 802, 804. The cathode of the first SCR (cathode 1) is coupled to the first I/O pin 802, and the first I/O pin 802 is the anode of the second SCR (anode 2). The cathode of the third SCR (cathode 3) is coupled to the second I/O pin 804, and the second I/O pin is the anode of the fourth SCR (anode 4). In the embodiment of Fig. 8, the SCR is symmetrical to each other with the first and second planes 806, 808.

Each SCR includes: a cathode (or anode) that is a single w-type; each SCR also includes an anode (or cathode) that is double w-shaped and that is opposite to each other and mirror symmetrical. For example, the first SCR (SCR1) includes an anode having a first single w-shape with a back parallel to the second plane 806. The first SCR also includes a cathode having a pair of w-shaped projections. The single w type of the first SCR is configured in the first n- Above the well (N well 1), the pair of w-shaped projections of the first SCR are disposed above the first p-well (P-well 1). The N+ doped n well contact point is disposed in the recess of the w-type anode (anode 1); and the P+ doped p well contact point is disposed in the recess of the pair of w-shaped protrusions of the cathode of the SCR1 . Other SCRs also use a similar configuration.

Figure 9 shows the protection mechanisms provided by the ESD protection devices of Figures 7A and 7B in certain different ESD situations. As shown, when a positive pair of VDD type ESD pulses 716 occurs, ESD protection device 700 can transfer the pulses through second SCR 704 to the upper VDD rail. When a negative pair of VSS type ESD pulses 718 occurs, ESD protection device 700 can transfer the pulses through first SCR 702 to first I/O pin 710 to the lower VSS rail. When a positive VSS type ESD pulse 720 occurs, the ESD protection device 700 can transfer the pulse 720 through the second SCR 704 to the upper portion (the VDD rail, and then to the power rail ESD clamp circuit 714. If a negative pair When the VSS type ESD pulse 722 occurs, the ESD protection device 700 can transfer the pulse 722 over the power rail ESD clamp circuit 714 and then along the lower VSS rail to the first SCR 702 and the first I/O reference. Finally, if the pin-to-pin type ESD pulse 724 occurs, the ESD protection device 700 can transfer the pulse 724 to one of the second SCR 704 and the other of the third SCR 706. The energy of the pulse 724 is then derived by the second IC pin 712.

Figure 10 illustrates a method of fabricating an SCR for use as an ESD protection circuit in certain embodiments. Although this method is illustrated in a series of steps, it will be appreciated that some of the steps can be performed simultaneously and split into multiple sub-steps. Moreover, in other embodiments, the steps of the method can be in a different order.

The method of FIG. 10 begins in step 1002, in which there is a first n A doping concentration (eg, N)-n well is formed in a semiconductor matrix.

In step 1004, a p-well having a first p-doping concentration (eg, P) is formed in the semiconductor matrix. The p-well and the n-well will merge with the junction, and the junction is aligned with the first plane.

In step 1006, an anode region is formed over the n-well. The anode region has a second p-doping concentration (P+) that is greater than the first p-doping concentration. The anode region includes one or more u-type, w-type, F-type, or π-type protrusions, which in some embodiments extend upward from the semiconductor substrate.

In step 1008, one or more n well contact points having a second n-doping concentration (eg, N+) are formed in the recesses of the u-type, w-type, F-type, or π-type protrusions in the anode region. .

In step 1010, a cathode region having a second n-doping concentration (eg, N+) is formed over the p-well. The cathode region comprises one or more u-type, w-type, F-type or π-type protrusions, which are composed of a semiconductor substrate. Extend upwards.

In step 1012, one or more p-well contact points having a second p-doping concentration (eg, P+) are formed in the recesses of the u-type, w-type, F-type, or π-type protrusions of the cathode region. in.

Some embodiments of the invention relate to a silicon controlled rectifier (SCR) that directs current from an SCR anode to a current path of an SCR cathode. The current path includes a first vertical current path portion coupled to the SCR anode and a second vertical current path portion coupled to the SCR cathode. A horizontal current path portion includes a first well region and a second well region. The first well region and the second well region meet a junction surface, and the junction surface is stacked on a first plane. The first well region and the second well region cooperate to cross each other a distance between the first vertical current path portion and the second vertical current path portion. The first vertical current path portion and the second vertical current path portion are mirror symmetrical with the first plane.

Some embodiments of the invention relate to a controlled rectifier (SCR) formed on a substrate including an SCR anode, an SCR cathode, and a current path for directing current from the SCR anode to the SCR cathode. The current path includes a first vertical current path portion coupled to the SCR anode and having a first conductivity type. The current path also includes a second vertical current path portion coupled to the SCR cathode and having a second conductivity type opposite the first conductivity type. The second vertical current path portion and the first vertical current path portion are horizontally disposed on the same plane, and the two are horizontally spaced apart by a distance. The current path also includes a horizontal current path portion disposed under the first vertical current path portion and the second vertical current path portion and spanning the first vertical current path portion and the second vertical current path portion The distance between the spaces. The horizontal current path portion includes a first well region coupled to the first vertical current path portion and disposed under the first vertical current path portion, wherein the first well has the second conductivity type. The horizontal current path portion also includes a second well region coupled to the second vertical current path portion and disposed under the second vertical current path portion. The first well and the second well meet at a junction, and the first vertical current path portion and the second vertical current path portion are mirror symmetrical with the first plane.

It is to be noted that the words "first" and "second" are used merely as a general designation and are not intended to indicate any order or positional relationship of the various elements. Although the invention has been described above in a number of embodiments, the invention is not intended to be Various modifications and alterations of the present invention are possible in the spirit of the appended claims. In addition, although a particular feature may be described in a single embodiment, the features may be integrated with a plurality of features in other embodiments to achieve a superior performance.

202‧‧‧Semiconductor matrix

210‧‧‧First Well Area

208‧‧‧ Current path

208a‧‧‧First vertical current path section

208b‧‧‧second vertical current path section

208c‧‧‧Horizontal current path section

212‧‧‧Second well area

218‧‧‧First w-shaped projections

220‧‧‧Upper

222‧‧‧Under

224a‧‧‧First vertical current path recess

224b‧‧‧First vertical current path recess

226a‧‧‧First well zone contact point

226b‧‧‧First well zone contact point

228‧‧‧Second w-shaped projections

230‧‧‧Upper

232‧‧‧Under

234a‧‧‧second vertical current path recess

234b‧‧‧second vertical current path recess

236a‧‧‧Second well zone contact point

236b‧‧‧Second well zone contact point

Claims (10)

A silicon controlled rectifier (SCR) includes a current path for directing current from an SCR anode to an SCR cathode; wherein the current path includes: a first vertical current path portion coupled to the SCR anode; a second vertical current path portion coupled to the SCR cathode; and a horizontal current path portion located below the first and second vertical current path portions, wherein the horizontal current path portion includes a first well region and a first a second well region, the first well region and the second well region are joined to a junction surface, and the junction surface is stacked on a first plane, wherein the first well region and the second well region cooperate with each other A distance between the first vertical current path portion and the second vertical current path portion. The 矽-controlled rectifier of claim 1, wherein the first vertical current path portion and the second vertical current path portion are mirror-symmetrical with the first plane; wherein the step-controlled rectifier further comprises: at least one a vertical current path recess extending inwardly from a sidewall of the first vertical current path portion; and at least a second vertical current path recess extending inwardly from a sidewall of the second vertical current path portion Extending; wherein the at least one first vertical current path recess and the at least one second vertical current path recess are mirror symmetrical with the first plane; at least one first well contact point is disposed at the at least one first The vertical current path is recessed, and the at least one first well contact is electrically coupled to the first a well; at least one second well contact point disposed in the at least one second vertical current path recess, the at least one second well contact point being electrically coupled to a second well; wherein the at least a first well region contact point is shorted to the at least one second well region contact point; wherein a second plane intersects the first plane perpendicularly such that the first vertical current path portion and the second vertical current path portion The second plane is symmetrical to each other. The 矽-controlled rectifier of claim 1, wherein the first vertical current path portion is a u-type, f-type, π-type or w-type protrusion, which extends vertically upward from a substrate in which the SCR is located; Wherein the second vertical current path portion is a u-type, f-type, π-type or w-type protrusion, which extends vertically upward from the substrate, and the u-type, f-type, and the first vertical current path portion The π-type or w-shaped protrusion is mirror-symmetrical with the first plane; wherein the 矽-controlled rectifier further includes the u-type, the f-type, and the π disposed in the first vertical current path portion and the second vertical current path portion A plurality of contact points at the recess of the type or w-shaped projection. The 矽-controlled rectifier of claim 1, wherein the first vertical current path portion has a first conductivity type, and the first well has a second conductivity type opposite to the first conductivity type Wherein the first well region has the second conductivity type and the second well region has the first conductivity type. The 矽-controlled rectifier of claim 1, wherein the SCR anode comprises a plurality of u-type, f-type, π-type or w-type protrusions, wherein the protrusions are parallel to the second When the direction of the plane extends, the side walls of adjacent u-shaped, f-shaped, π-shaped or w-shaped projections abut or merge with each other. The 矽-controlled rectifier of claim 1, wherein the SCR anode comprises a plurality of u-type, f-type, π-type or w-type protrusions, wherein adjacent u-type, f-type, π-type or w The side walls of the projections abut or merge with each other. A voltage controlled rectifier (SCR) formed on a substrate includes an SCR anode, an SCR cathode, and a current path for directing current from the SCR anode to the SCR cathode; wherein the current path includes: a first vertical a current path portion coupled to the SCR anode and having a first conductivity type; a second vertical current path portion coupled to the SCR cathode and having a second conductivity opposite the first conductivity type a rate type, wherein the second vertical current path portion is horizontally disposed on the same plane as the first vertical current path portion, and the two are horizontally spaced apart by a distance; and a horizontal current path portion is disposed in the first vertical current path portion And a distance between the first vertical current path portion and the second vertical current path portion, the horizontal current path portion includes: a first well region, coupled Connecting to the first vertical current path portion and disposed under the first vertical current path portion, wherein the first well has the second conductivity type; and a second Region, coupled to the second current path portion and disposed perpendicular to the Below the second vertical current path portion, wherein the first well and the second well meet a junction, and the junction is aligned with a first plane, wherein the second well has the first conductivity type. The 整流-controlled rectifier of claim 7, wherein the first vertical current path portion and the second vertical current path portion are mirror-symmetrical with the first plane; wherein the first vertical current path portion is elongated a semiconductor body having opposite sidewalls; wherein the elongated semiconductor body includes an upper layer having the first conductivity type and a lower layer having the second conductivity type; the controlled rectifier further includes: a plurality of dielectric regions, Adjacent to the semiconductor body and located on the side of the two sidewalls; and at least one first well region contact point coupled to the first well region and shorted to at least one second well region contact point, wherein the second well The area contact point is coupled to the second well region; wherein a second plane is vertically staggered with the first plane such that the first vertical current path portion and the second vertical current path portion are symmetrical with each other in the second plane. The 矽-controlled rectifier of claim 7, wherein the first vertical current path portion is a u-type, f-type, π-type or w-type protrusion, and the substrate is vertically extended upward by a substrate in which the SCR is located; Wherein the second vertical current path portion is a u-type, f-type, π-type or w-type protrusion, extending vertically upward from the substrate, and the first vertical current path The u-shaped, f-type, π-type or w-shaped protrusion of the diameter portion is mirror-symmetrical with the first plane; wherein the controlled rectifier further comprises a first vertical current path portion and the second vertical current path Part of the plurality of contact points in the recess of the u-type, f-type, π-type or w-type protrusion. A method of fabricating a silicon controlled rectifier (SCR) for use as an ESD protection circuit, comprising: forming an n-well having a first n-doping concentration in a semiconductor substrate; forming a p-well Having a first p-doping concentration in a semiconductor substrate, wherein the p-well and the n-well meet at a junction; and forming an anode region over the n-well; wherein the anode region has a second p a doping concentration, the value of which is greater than the first p-doping concentration, the anode region comprising a u-type, f-type, π-type or w-type protrusion extending outward from the semiconductor substrate, further comprising: forming n- a well contact point having a second n-doping concentration at a recess of the u-type, f-type, π-type or w-type protrusion in the anode region; forming a cathode region having a p-well on the p-well a second n-doping concentration, wherein the cathode region comprises a u-type, f-type, π-type or w-type protrusion extending outward from the semiconductor substrate; and forming a p-well contact point in the cathode region a recess of the u-type, f-type, π-type or w-type protrusion has a second p-doping concentration; wherein the anode is formed And the cathode region comprising a plurality of u-type, f-type, [pi] w-type or projection type, wherein the anode region and the cathode region to the surface where one plane symmetrical to each other; Wherein the semiconductor substrate is a matrix.