TWI524649B - Polar switch circuit - Google Patents

Polar switch circuit Download PDF

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TWI524649B
TWI524649B TW102124141A TW102124141A TWI524649B TW I524649 B TWI524649 B TW I524649B TW 102124141 A TW102124141 A TW 102124141A TW 102124141 A TW102124141 A TW 102124141A TW I524649 B TWI524649 B TW I524649B
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Taiwan
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transistor switch
pulse width
modulation signal
width modulation
switching circuit
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TW102124141A
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Chinese (zh)
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TW201503570A (en
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陳世昌
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研能科技股份有限公司
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Priority to TW102124141A priority Critical patent/TWI524649B/en
Priority to US13/975,924 priority patent/US20140042872A1/en
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Publication of TWI524649B publication Critical patent/TWI524649B/en

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Description

極性切換電路Polarity switching circuit

    本案係關於一種極性切換電路,尤指一種可輸出平滑交流波形之輸出交流電壓來驅動壓電致動器之極性切換電路。

The present invention relates to a polarity switching circuit, and more particularly to a polarity switching circuit that can output an output AC voltage of a smooth AC waveform to drive a piezoelectric actuator.

隨著科技的進步,各類3C產品已被視為推動市場成長的重要力量。無庸置疑的,這樣的發展趨勢仍將持續下去,而且隨著微電子技術的進步,3C產品不但功能日趨複雜,其尺寸亦漸趨於小型化,且可攜性也隨之大幅提高,使用者因此可以方便輕鬆以3C產品處理各項事務。近來,亦已發展出壓電致動器來應用於3C產品中,壓電致動器具有電壓低、不受雜訊干擾、體積小、反應快、發熱少、精密度佳、轉換效率高和控制容易等多方面的優點。With the advancement of technology, various 3C products have been regarded as an important force to promote market growth. Undoubtedly, such development trend will continue, and with the advancement of microelectronics technology, 3C products are not only increasingly complex in function, but their size is also becoming smaller and the portability is greatly improved. Therefore, it is easy to handle various matters with 3C products. Recently, piezoelectric actuators have been developed for use in 3C products. Piezoelectric actuators have low voltage, no noise interference, small volume, fast response, low heat generation, high precision, high conversion efficiency, and Control is easy and many other advantages.

壓電致動器通常需要一個交流電壓來對其作用而驅使壓電致動器進行週期性高速運動,因此實際上壓電致動器需要一驅動系統來驅動,該驅動系統將所連接之直流電壓進行轉換,以輸出交流電壓來驅動致動器。請參閱第1圖,其係為習知用來驅動壓電致動器的驅動系統之的電路方塊圖。如第1圖所示,習知驅動系統1係用以將直流輸入電壓VDC 轉換,進而產生輸出交流電壓Vo1 及Vo2 來驅動壓電致動器9(如第2A圖所示),且包含一升壓電路10、一電壓倍增電路11及一極性切換電路12。其中升壓電路10係連接直流輸入電壓VDC ,並利用內部開關元件的切換運作以及內部電感、電容與二極體等元件的儲能與濾波而將直流輸入電壓VDC 升壓成一暫態電壓VT 。電壓倍增電路11則連接暫態電壓VT ,並將其倍增至例如4倍的一直流高電壓VB 。極性切換電路12則將直流高電壓VB 轉換成輸出交流電壓Vo1 及Vo2 ,以驅動壓電致動器9。Piezoelectric actuators typically require an alternating voltage to act to drive the piezoelectric actuator to perform periodic high-speed motion, so in practice the piezoelectric actuator requires a drive system that will drive the connected direct current. The voltage is converted to output an alternating voltage to drive the actuator. Please refer to FIG. 1, which is a circuit block diagram of a conventional drive system for driving a piezoelectric actuator. As shown in FIG. 1, the conventional driving system 1 is configured to convert a DC input voltage V DC to generate output AC voltages V o1 and V o2 to drive the piezoelectric actuator 9 (as shown in FIG. 2A). A booster circuit 10, a voltage multiplying circuit 11 and a polarity switching circuit 12 are included. The booster circuit 10 is connected to the DC input voltage V DC and boosts the DC input voltage V DC into a transient voltage by switching operation of internal switching elements and energy storage and filtering of components such as internal inductors, capacitors and diodes. V T . The voltage multiplying circuit 11 is connected to the transient voltage V T and is multiplied to, for example, four times the DC high voltage V B . The polarity switching circuit 12 converts the DC high voltage V B into the output AC voltages V o1 and V o2 to drive the piezoelectric actuator 9.

請參閱第2A、2B及3圖,並配合第1圖,其中第2A圖係為第1圖所示之極性切換電路之內部電路結構圖,第2B圖係為第2A圖所示之數位訊號fsw 為低準位時之電路運作示意圖,第3圖係為第2A或2B圖之電壓時序波形圖。如圖所示,習知極性切換電路12主要連接直流高電壓VB 、輸入直流低電壓Vin 及數位訊號fsw ,並轉換成輸出交流電壓Vo1 及Vo2 ,以驅動壓電致動器9反覆作動,其中,極性切換電路12可由第一限流電阻R21、第二限流電阻R22、第三限流電阻R23、第一電晶體開關Q21、第二電晶體開關Q22、第三電晶體開關Q23、第四電晶體開關Q24、第五電晶體開關Q25、第六電晶體開關Q26及第七電晶體開關Q27所組成。Please refer to Figures 2A, 2B and 3, together with Figure 1, where Figure 2A is the internal circuit structure diagram of the polarity switching circuit shown in Figure 1, and Figure 2B is the digital signal shown in Figure 2A. f sw is a schematic diagram of the operation of the circuit at a low level, and FIG. 3 is a voltage timing waveform diagram of the 2A or 2B diagram. As shown, the conventional polarity switching circuit 12 is mainly connected to a DC high voltage V B , an input DC low voltage V in and a digital signal f sw , and is converted into output AC voltages V o1 and V o2 to drive the piezoelectric actuator. 9 repeated operation, wherein the polarity switching circuit 12 can be a first current limiting resistor R21, a second current limiting resistor R22, a third current limiting resistor R23, a first transistor switch Q21, a second transistor switch Q22, a third transistor The switch Q23, the fourth transistor switch Q24, the fifth transistor switch Q25, the sixth transistor switch Q26, and the seventh transistor switch Q27 are formed.

藉此當數位控制訊號fsw 為高準位(High)並傳送至第一及第六電晶體開關Q21、Q26之控制端時,與接地端G連接之第一及第六電晶體開關Q21、Q26便導通,由於第一限流電阻R21係與第一電晶體開關Q21連接,因此第一限流電阻R21所在的支路便連接至接地端G,此時第二及第四電晶體開關Q22、Q24會因為本身的控制端與第一限流電阻R21所在的支路連接而對應截止,使第二限流電阻R22所在的支路因直流高電壓VB 而處於高準位,因此其控制端與第二限流電阻R22所在的支路連接之第三電晶體開關Q23便導通,同時,第七電晶體開關Q27之控制端亦連接到高準位之數位控制訊號fsw ,故第七電晶體開關Q27導通,因第三限流電阻R23係與第七電晶體開關Q27連接,故第三限流電阻R23所在的支路便連接至接地端G,又第五電晶體開關Q25之控制端係與第三限流電阻R23所在的支路連接,造成第五電晶體開關Q25截止,所以電流將沿箭頭方向進行,如第2A圖所示。Therefore, when the digital control signal f sw is at a high level and transmitted to the control terminals of the first and sixth transistor switches Q21 and Q26, the first and sixth transistor switches Q21 connected to the ground terminal G, Q26 is turned on. Since the first current limiting resistor R21 is connected to the first transistor switch Q21, the branch where the first current limiting resistor R21 is located is connected to the ground terminal G, and the second and fourth transistor switches Q22 at this time. Q24 will be correspondingly cut off because its control terminal is connected to the branch where the first current limiting resistor R21 is located, so that the branch where the second current limiting resistor R22 is located is at a high level due to the DC high voltage V B , so its control The third transistor switch Q23 connected to the branch where the second current limiting resistor R22 is connected is turned on, and the control terminal of the seventh transistor switch Q27 is also connected to the high level digital control signal f sw , so the seventh The transistor switch Q27 is turned on, because the third current limiting resistor R23 is connected to the seventh transistor switch Q27, so the branch where the third current limiting resistor R23 is located is connected to the ground terminal G, and the fifth transistor switch Q25 is controlled. The end system is connected to the branch where the third current limiting resistor R23 is located, resulting in the first Transistor switch Q25 is turned off, so that the current will be in the direction of the arrow, as shown in FIG. 2A.

當數位訊號fsw 為低準位(Low)時,如第2B圖所示,則所有電晶體開關動作與第2A圖相反,使電流行進方向如第2B圖所示之箭頭方向,如此一來,極性切換電路12所輸出之輸出交流電壓Vo1 及Vo2 於壓電致動器9上會形成交流方波,亦即第3圖所示之輸出交流電壓Vo1 與輸出交流電壓Vo2 相減值的波形。When the digital signal f sw is at a low level (Low), as shown in FIG. 2B, all the transistor switching operations are opposite to those of FIG. 2A, so that the current traveling direction is the direction of the arrow shown in FIG. 2B, thus The output AC voltages V o1 and V o2 outputted by the polarity switching circuit 12 form an AC square wave on the piezoelectric actuator 9, that is, the output AC voltage V o1 and the output AC voltage V o2 shown in FIG. Impaired waveform.

當習知極性切換電路12所輸出之輸出交流電壓Vo1 及Vo2 於壓電致動器9上形成交流方波時,由於其電壓快速上升及快速下降,故對壓電致動器9進行快速充電,雖然快速充電可以使得壓電致動器9快速達到振幅的頂端,但同時卻也增加電力的耗損。此外,由於習知極性切換電路12係以交流方波對壓電致動器9進行快速充電,因此壓電致動器9上會具有以自然共振頻率產生振動之情況發生,此自然振動會導致較大的噪音問題。更甚者,由於習知極性切換電路12需使用較多的電晶體開關來構成,亦即第2A圖所示之7個電晶體開關,不但導致習知極性切換電路12的生產成本提高,也增加極性切換電路12因多個電晶體開關在進行導通或截止切換所產生的開關損耗。When the output AC voltages V o1 and V o2 outputted by the conventional polarity switching circuit 12 form an AC square wave on the piezoelectric actuator 9, the piezoelectric actuator 9 is subjected to rapid rise and rapid drop. Fast charging, although fast charging can cause the piezoelectric actuator 9 to quickly reach the top of the amplitude, but at the same time it also increases the power consumption. In addition, since the conventional polarity switching circuit 12 rapidly charges the piezoelectric actuator 9 with an alternating current square wave, the piezoelectric actuator 9 has a vibration generated at a natural resonance frequency, which causes the natural vibration to cause Large noise problems. Moreover, since the conventional polarity switching circuit 12 is configured to use a large number of transistor switches, that is, the seven transistor switches shown in FIG. 2A, not only the production cost of the conventional polarity switching circuit 12 is increased, but also The switching loss caused by the polarity switching circuit 12 due to the on or off switching of the plurality of transistor switches is increased.

因此如何發展一種可改善上述習知技術缺失之極性切換電路,實為目前迫切需要解決之課題。

Therefore, how to develop a polarity switching circuit that can improve the above-mentioned conventional technology is an urgent problem to be solved.

本案之主要目的為提供一種極性切換電路,俾解決習知極性切換電路係輸出交流方波來驅動壓電致動器,導致具有電力損耗大,且壓電致動器在作動時會產生噪音,此外,因習知極性切換電路係需要較多的電晶體開關來構成,導致習知極性切換電路的生產成本提高、開關損耗亦較大等缺失。The main purpose of the present invention is to provide a polarity switching circuit that solves the problem that the conventional polarity switching circuit outputs an alternating square wave to drive the piezoelectric actuator, resulting in a large power loss, and the piezoelectric actuator generates noise when it is activated. In addition, since the conventional polarity switching circuit requires a large number of transistor switches, the production cost of the conventional polarity switching circuit is increased, and the switching loss is also large.

為達上述目的,本案之一較廣義實施態樣為提供一種極性切換電路,將直流高電壓轉換為輸出交流電壓,以驅動壓電致動器,包含:第一開關電路,接收第一脈衝寬度調變訊號及第二脈衝寬度調變訊號,其中第一脈衝寬度調變訊號與第二脈衝寬度調變訊號互為反相導通,且第一開關電路之一端與接地端連接,另一端連接直流高電壓;第二開關電路,接收第一脈衝寬度調變訊號及第二脈衝寬度調變訊號,其中第一脈衝寬度調變訊號與第二脈衝寬度調變訊號互為反相導通,且第二開關電路之一端與接地端連接,另一端連接直流高電壓;第一濾波電路,與第一開關電路、壓電致動器之接點及接地端連接;以及第二濾波電路,與第二開關電路、壓電致動器之另一接點及接地端連接;其中當第一脈衝寬度調變訊號以及第二脈衝寬度調變訊號交錯地進行高準位及低準位的切換時,促使輸出交流電壓能產生平滑交流波形之交流電壓輸入至壓電致動器之各接點。

In order to achieve the above object, a broader aspect of the present invention provides a polarity switching circuit for converting a DC high voltage into an output AC voltage to drive a piezoelectric actuator, comprising: a first switching circuit that receives a first pulse width The modulation signal and the second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are in anti-phase conduction, and one end of the first switching circuit is connected to the ground end, and the other end is connected to the DC a high voltage; the second switching circuit receives the first pulse width modulation signal and the second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are in anti-phase conduction, and the second One end of the switch circuit is connected to the ground end, and the other end is connected to a DC high voltage; the first filter circuit is connected with the first switch circuit, the contact of the piezoelectric actuator and the ground end; and the second filter circuit and the second switch The circuit and the other contact of the piezoelectric actuator are connected to the ground; wherein the first pulse width modulation signal and the second pulse width modulation signal are alternately high-leveled When the low level switch, causes the output AC voltage to produce an AC voltage smoothing each contact of the AC input waveform to the piezoelectric actuator.

1‧‧‧驅動系統
10‧‧‧升壓電路
11‧‧‧倍增電路
4、12‧‧‧極性切換電路
40‧‧‧第一濾波電路
41‧‧‧第二濾波電路
8‧‧‧流體輸送裝置
9‧‧‧壓電致動器
90‧‧‧致動片
91‧‧‧振動薄模
92‧‧‧壓力腔室
V‧‧‧直流高電壓
Vo1、Vo2、V1、V2‧‧‧輸出交流電壓
VDC‧‧‧直流輸入電壓
VT‧‧‧暫態電壓
Vmax‧‧‧最大電壓
fsw‧‧‧數位訊號
Vin‧‧‧輸入直流低電壓
Vs1‧‧‧第一切換電壓
Vs2‧‧‧第二切換電壓
R21‧‧‧第一限流電阻
R22‧‧‧第二限流電阻
R23‧‧‧第三限流電阻
Q21、Q41‧‧‧第一電晶體開關
Q22、Q42‧‧‧第二電晶體開關
Q23、Q43‧‧‧第三電晶體開關
Q24、Q44‧‧‧第四電晶體開關
Q25‧‧‧第五電晶體開關
Q26‧‧‧第六電晶體開關
Q27‧‧‧第七電晶體開關
G‧‧‧接地端
PWM1‧‧‧第一脈衝寬度調變訊號
PWM2‧‧‧第一脈衝寬度調變訊號
L1‧‧‧第一電感
L2‧‧‧第二電感
C1‧‧‧第一電容
C2‧‧‧第二電容
1‧‧‧Drive system
10‧‧‧Boost circuit
11‧‧‧ multiplier circuit
4, 12‧‧‧ polarity switching circuit
40‧‧‧First filter circuit
41‧‧‧Second filter circuit
8‧‧‧Fluid conveying device
9‧‧‧ Piezoelectric Actuator
90‧‧‧Acoustic film
91‧‧‧Vibration thin mold
92‧‧‧pressure chamber
V B ‧‧‧DC high voltage
V o1 , V o2 , V1 , V2‧‧‧ output AC voltage
V DC ‧‧‧DC input voltage
V T ‧‧‧Transient voltage
V max ‧‧‧max voltage
f sw ‧‧‧ digital signal
V in ‧‧‧Input DC low voltage
V s1 ‧‧‧ first switching voltage
V s2 ‧‧‧second switching voltage
R21‧‧‧First current limiting resistor
R22‧‧‧second current limiting resistor
R23‧‧‧ third current limiting resistor
Q21, Q41‧‧‧ first transistor switch
Q22, Q42‧‧‧Second transistor switch
Q23, Q43‧‧‧ Third transistor switch
Q24, Q44‧‧‧4th transistor switch
Q25‧‧‧ fifth transistor switch
Q26‧‧‧6th transistor switch
Q27‧‧‧ seventh transistor switch
G‧‧‧ Grounding terminal
PWM1‧‧‧ first pulse width modulation signal
PWM2‧‧‧ first pulse width modulation signal
L1‧‧‧first inductance
L2‧‧‧second inductance
C1‧‧‧first capacitor
C2‧‧‧second capacitor

第1圖:其係為習知用來驅動壓電致動器之驅動系統的電路方塊圖。
第2A圖:其係為第1圖所示之極性切換電路之內部電路結構圖。
第2B圖:其係為第2A圖所示之數位訊號fsw為低準位時之電路運作示意圖。
第3圖:其係為第2A或2B圖之電壓時序波形圖。
第4A圖:其係為本案較佳實施例之極性切換電路的內部電路結構圖。
第4B圖:其係為第4A圖所示之第一脈衝寬度調變訊號PWM1為低準位,而第二脈衝寬度調變訊號PWM2係處於高準位及低準位切換狀態時之電路運作示意圖。
第5A-5C圖:其係為第4A及4B圖之電壓時序圖。
第6圖:其係為第4A圖所示之第一濾波電路及第二濾波電路的一變化例。
第7A-7B圖:其係為第4A及4B圖所示之極性切換電路的一變化例。
第8圖:其係為第4A圖所示之壓電致動器應用於一機構本體之實施態樣示意圖。

Fig. 1 is a circuit block diagram of a conventional drive system for driving a piezoelectric actuator.
Fig. 2A is a diagram showing the internal circuit structure of the polarity switching circuit shown in Fig. 1.
Figure 2B: This is a schematic diagram of the operation of the circuit when the digital signal fsw shown in Figure 2A is at a low level.
Figure 3: This is a voltage timing waveform diagram of Figure 2A or 2B.
4A is a diagram showing the internal circuit structure of the polarity switching circuit of the preferred embodiment of the present invention.
Figure 4B: The first pulse width modulation signal PWM1 shown in Figure 4A is at a low level, and the second pulse width modulation signal PWM2 is in a high level and low level switching state. schematic diagram.
Figure 5A-5C: This is the voltage timing diagram for Figures 4A and 4B.
Fig. 6 is a modification of the first filter circuit and the second filter circuit shown in Fig. 4A.
7A-7B: This is a modification of the polarity switching circuit shown in Figs. 4A and 4B.
Fig. 8 is a schematic view showing an embodiment of a piezoelectric actuator shown in Fig. 4A applied to a mechanism body.

體現本案特徵與優點的一些典型實施例將在後段的說明中詳細敘述。應理解的是本案能夠在不同的態樣上具有各種的變化,然其皆不脫離本案的範圍,且其中的說明及圖式在本質上係當作說明之用,而非用以限制本案。Some exemplary embodiments embodying the features and advantages of the present invention are described in detail in the following description. It should be understood that the present invention is capable of various modifications in the various aspects of the present invention, and the description and drawings are intended to be illustrative and not limiting.

請參閱第4A及4B圖,其中第4A圖為本案較佳實施例之極性切換電路的內部電路結構圖,第4B圖為第4A圖所示之極性切換電路在第一脈衝寬度調變訊號PWM1為低準位,而第二脈衝寬度調變訊號PWM2係處於高準位及低準位切換狀態時之電路運作示意圖。如第4A及4B圖所示,極性切換電路4係連接一直流高電壓VB ,並依據一第一脈衝寬度調變訊號PWM1以及一第二脈衝寬度調變訊號PWM2而將直流高電壓VB 轉換為輸出交流電壓V1以及V2,以驅動一壓電致動器9反覆作動,其中直流高電壓VB 可例如由第1圖所示之電壓倍增電路11所輸出。極性切換電路4主要包含一第一電晶體開關Q41、一第二電晶體開關Q42、一第三電晶體開關Q43、一第四電晶體開關Q44、一第一濾波電路40、一第二濾波電路41。Please refer to FIG. 4A and FIG. 4B , wherein FIG. 4A is an internal circuit structure diagram of a polarity switching circuit according to a preferred embodiment of the present invention, and FIG. 4B is a polarity switching circuit shown in FIG. 4A in a first pulse width modulation signal PWM1. The circuit operation diagram is a low level, and the second pulse width modulation signal PWM2 is in a high level and low level switching state. As shown in FIG. 4A and FIG. 4B, the polarity switching circuit 4 is connected to a DC high voltage line V B, and according to a first pulse width modulation signal PWM1, and a second pulse width modulation signal PWM2 and the high DC voltage V B The output voltages V1 and V2 are converted to drive a piezoelectric actuator 9 to be repeatedly operated, wherein the DC high voltage V B can be output, for example, by the voltage multiplying circuit 11 shown in FIG. The polarity switching circuit 4 mainly includes a first transistor switch Q41, a second transistor switch Q42, a third transistor switch Q43, a fourth transistor switch Q44, a first filter circuit 40, and a second filter circuit. 41.

第一電晶體開關Q41之一控制端係連接第一脈衝寬度調變訊號PWM1,第一電晶體開關Q41之一電流輸入端係與第一濾波電路40連接,第一電晶體開關Q41之一電流輸出端係與接地端G連接。第二電晶體開關Q42之控制端係連接第二脈衝寬度調變訊號PWM2,第二電晶體開關Q42之一電流輸入端係連接直流高電壓VB 之電能,第二電晶體開關Q42之一電流輸出端則與第一濾波電路40以及第一電晶體開關Q41之電流輸入端連接。第一濾波電路40係與壓電致動器9之一接點(接收輸出交流電壓V2)及接地端G連接。One control end of the first transistor switch Q41 is connected to the first pulse width modulation signal PWM1, and one current input end of the first transistor switch Q41 is connected to the first filter circuit 40, and one current of the first transistor switch Q41 The output terminal is connected to the ground terminal G. The control end of the second transistor switch Q42 is connected to the second pulse width modulation signal PWM2, and the current input terminal of the second transistor switch Q42 is connected to the power of the DC high voltage V B , and the current of the second transistor switch Q42 The output terminal is connected to the first filter circuit 40 and the current input terminal of the first transistor switch Q41. The first filter circuit 40 is connected to one of the piezoelectric actuators 9 (receive output AC voltage V2) and the ground terminal G.

第三電晶體開關Q43之一控制端係連接第二脈衝寬度調變訊號PWM2,第三電晶體開關Q43之一電流輸入端係與第二濾波電路41連接,第三電晶體開關Q43之一電流輸出端係與接地端G連接。第四電晶體開關Q44之控制端係連接第一脈衝寬度調變訊號PWM1,第四電晶體開關Q44之一電流輸入端係連接直流高電壓VB 之電能,第四電晶體開關Q44之一電流輸出端則與第二濾波電路41以及第三電晶體開關Q43之電流輸入端連接。第二濾波電路41係與壓電致動器9之另一接點(接收輸出交流電壓V1)及接地端G連接。於上述實施例中,第一電晶體開關Q1及第一電晶體開關Q2係可構成第一開關電路,第三電晶體開關Q3及第一電晶體開關Q4係可構成第二開關電路。One control terminal of the third transistor switch Q43 is connected to the second pulse width modulation signal PWM2, and one current input terminal of the third transistor switch Q43 is connected to the second filter circuit 41, and one current of the third transistor switch Q43 The output terminal is connected to the ground terminal G. The control terminal of the fourth transistor switch Q44 is connected to the first pulse width modulation signal PWM1, and the current input terminal of the fourth transistor switch Q44 is connected to the power of the DC high voltage V B , and the current of the fourth transistor switch Q44 The output terminal is connected to the current input terminals of the second filter circuit 41 and the third transistor switch Q43. The second filter circuit 41 is connected to another contact (receive output AC voltage V1) of the piezoelectric actuator 9 and the ground terminal G. In the above embodiment, the first transistor switch Q1 and the first transistor switch Q2 may constitute a first switch circuit, and the third transistor switch Q3 and the first transistor switch Q4 may constitute a second switch circuit.

請參閱第5A、5B及5C圖,並配合第4A及4B圖,其中第5A、5B及5C圖係分別為第4A及4B圖之電壓時序圖。如第4A、4B、5A、5B及5C圖所示,第一脈衝寬度調變訊號PWM1以及第二脈衝寬度調變訊號PWM2係交錯地進行高準位及低準位的切換,亦即當第一脈衝寬度調變訊號PWM1在進行高準位及低準位的切換時,第二脈衝寬度調變訊號PWM2係為低準位,而當第二脈衝寬度調變訊號PWM2在進行高準位及低準位的切換時,第一脈衝寬度調變訊號PWM1係為低準位,換言之,即第一脈衝寬度調變訊號PWM1以及第二脈衝寬度調變訊號PWM2互為反相導通。Please refer to Figures 5A, 5B and 5C, and in conjunction with Figures 4A and 4B, wherein Figures 5A, 5B and 5C are voltage timing diagrams for Figures 4A and 4B, respectively. As shown in FIGS. 4A, 4B, 5A, 5B, and 5C, the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 alternately perform high-level and low-level switching, that is, when When the pulse width modulation signal PWM1 is switched between the high level and the low level, the second pulse width modulation signal PWM2 is low level, and when the second pulse width modulation signal PWM2 is at a high level When the low level is switched, the first pulse width modulation signal PWM1 is low level, in other words, the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 are mutually turned on.

當第一脈衝寬度調變訊號PWM1處於高準位與低準位之高頻切換,而第二脈衝寬度調變訊號PWM2處於低準位時,第二脈衝寬度調變訊號PWM2之低準位將使得第二電晶體開關Q42與第三電晶體開關Q43截止,同時,第一脈衝寬度調變訊號PWM1處於高準位與低準位之高頻切換的狀態係使第一電晶體開關Q41與第四電晶體開關Q44處於相同的導通或截止的切換狀態,即第一電晶體開關Q41與第四電晶體開關Q44係同時為導通狀態或截止狀態,因此當第一電晶體開關Q41及第四電晶體開關Q44為導通時,會使得電流行進方向如第4A圖所示之箭頭方向。When the first pulse width modulation signal PWM1 is in the high frequency switching of the high level and the low level, and the second pulse width modulation signal PWM2 is at the low level, the low level of the second pulse width modulation signal PWM2 will be The second transistor switch Q42 and the third transistor switch Q43 are turned off. At the same time, the first pulse width modulation signal PWM1 is in a state of high frequency switching between the high level and the low level, so that the first transistor switch Q41 and the first transistor switch The four transistor switches Q44 are in the same on or off switching state, that is, the first transistor switch Q41 and the fourth transistor switch Q44 are simultaneously in an on state or an off state, so when the first transistor switch Q41 and the fourth transistor When the crystal switch Q44 is turned on, the current traveling direction is made to be in the direction of the arrow shown in Fig. 4A.

反之,當第二脈衝寬度調變訊號PWM2處於高準位與低準位之高頻切換,而第一脈衝寬度調變訊號PWM1處於低準位時,則所有電晶體開關動作相反,亦即第一脈衝寬度調變訊號PWM1之低準位將使得第一電晶體開關Q41與第四電晶體開關Q44截止,同時,第二脈衝寬度調變訊號PWM2處於高準位與低準位之高頻切換的狀態係使第二電晶體開關Q42與第三電晶體開關Q43處於相同的導通或截止的切換狀態,即第二電晶體開關Q42與第三電晶體開關Q43係同時為導通狀態或截止狀態,因此當第二電晶體開關Q42及第三電晶體開關Q43為導通時,會使得電流行進方向如第4B圖所示之箭頭方向。Conversely, when the second pulse width modulation signal PWM2 is in the high frequency switching of the high level and the low level, and the first pulse width modulation signal PWM1 is at the low level, all the transistor switches operate in opposite directions, that is, the first A low level of the pulse width modulation signal PWM1 will cause the first transistor switch Q41 and the fourth transistor switch Q44 to be turned off, and at the same time, the second pulse width modulation signal PWM2 is at a high level and low level for high frequency switching. The state of the second transistor switch Q42 and the third transistor switch Q43 are in the same on or off switching state, that is, the second transistor switch Q42 and the third transistor switch Q43 are simultaneously turned on or off. Therefore, when the second transistor switch Q42 and the third transistor switch Q43 are turned on, the current traveling direction is made to be in the direction of the arrow shown in FIG. 4B.

因此當第一脈衝寬度調變訊號PWM1與第二脈衝寬度調變訊號PWM2如第5A圖所示之訊號,亦即第一脈衝寬度調變訊號PWM1與第二脈衝寬度調變訊號PWM2係分別由高頻逐漸降低至低頻再逐漸升高至高頻時,於第一電晶體開關Q41之電流輸入端以及第二電晶體開關Q42之電流輸出端間所產生之一第二切換電壓Vs2 ,以及第三電晶體開關Q43之電流輸入端以及第四電晶體開關Q44之電流輸出端所產生之一第一切換電壓Vs1 ,將會分別與第一脈衝寬度調變訊號PWM1及第二脈衝寬度調變訊號PWM2同步而由高頻逐漸降低至低頻再逐漸升高至高頻,亦即如第5B圖所示,而第一切換電壓Vs1 及第二切換電壓Vs2 分別經由第二濾波電路41及第一濾波電路40之濾波後,即得第5C圖中所示之輸出交流電壓V1以及V2係呈現平滑交流波形。Therefore, when the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 are as shown in FIG. 5A, that is, the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 are respectively When the high frequency gradually decreases to a low frequency and then gradually increases to a high frequency, a second switching voltage V s2 is generated between the current input terminal of the first transistor switch Q41 and the current output terminal of the second transistor switch Q42, and A first switching voltage V s1 generated by the current input terminal of the third transistor switch Q43 and the current output terminal of the fourth transistor switch Q44 is respectively adjusted with the first pulse width modulation signal PWM1 and the second pulse width. The variable signal PWM2 is synchronously lowered from the high frequency to the low frequency and then gradually increased to the high frequency, that is, as shown in FIG. 5B, and the first switching voltage V s1 and the second switching voltage V s2 are respectively passed through the second filter circuit 41. After filtering by the first filter circuit 40, the output AC voltages V1 and V2 shown in FIG. 5C are presented as smooth AC waveforms.

 請再參閱第5C圖,壓電致動器9所連接之驅動電能,亦即輸出交流電壓V1以及V2的相減值乃在極性切換電路4剛開始作動的一第一時間內線性達到最大電壓Vmax 的一第一比例值,例如標記1至標記2區間,會呈現上升圓滑波形之後並於標記3一第一設定時間內到達最大電壓Vmax ,例如標記2至標記3,接著於一第二時間內持平,例如標記3至標記4,接續呈現下降圓滑波形並於一第二設定時間內降低至最大電壓Vmax 的一第二比例值,例如標記4至標記5,最後線性下降至零電壓,例如標記5至標記6,至於另一半週期(反方向)的交流波形,亦即標記6至標記11,其特性係相似於標記1至標記6,因此於此不再贅述。此外,極性切換電路4所輸出之輸出交流電壓V1及V2於壓電致動器9上所形成之平滑交流波形其波形上升與下降速度、轉折圓滑弧度與最大電壓Vmax 的持平時間皆可藉由第一脈衝寬度調變訊號PWM1以及第二脈衝寬度調變訊號PWM2之調變脈波寬度變化進行調整。Referring to FIG. 5C, the driving power connected to the piezoelectric actuator 9, that is, the subtraction value of the output AC voltages V1 and V2, reaches the maximum voltage linearly in a first time when the polarity switching circuit 4 starts to operate. A first ratio value of Vmax , such as the marker 1 to marker 2 interval, will appear after the rising rounded waveform and reach the maximum voltage Vmax within a first set time of the marker 3, such as marker 2 to marker 3, followed by a Two times flat, such as mark 3 to mark 4, successively presenting a falling rounded waveform and decreasing to a second proportional value of the maximum voltage V max for a second set time, such as mark 4 to mark 5, and finally linearly falling to zero The voltages, for example, marks 5 to 6, and the other half cycle (reverse direction) of the AC waveform, that is, the marks 6 to 11, are similar in characteristics to the marks 1 to 6, and therefore will not be described again. In addition, the output AC voltages V1 and V2 outputted by the polarity switching circuit 4 can be borrowed from the smooth AC waveform formed on the piezoelectric actuator 9 by the waveform rising and falling speed, the turning rounding curve and the maximum voltage V max . The modulation is performed by the modulation pulse width variation of the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2.

由於本案之極性切換電路4所輸出之輸出交流電壓V1及V2係形成平滑交流波形分別連接於壓電致動器9之兩接點上,並非如第2A圖所示之習知極性切換電路所輸出之輸出交流電壓Vo1 及Vo2 於壓電致動器9上係形成方波,故可以較為緩和的方式逐步對壓電致動器9充電,如此可減少急速充電所造成的電力耗損,此外,亦可減少壓電致動器9上會具有以自然共振頻率產生振動之情況發生,進而避免壓電致動器9在作動時所產生之噪音問題,此外,相較於第2A圖所示之習知極性切換電路12需使用七個的電晶體開關來構成,本案之極性切換電路4僅需使用四個電晶體開關(第一至第四電晶體開關Q41~Q44),因此本案之極性切換電路4的生產成本可降低,同時可減少極性切換電路因電晶體開關在進行導通或截止切換所產生的開關損耗。Since the output AC voltages V1 and V2 outputted by the polarity switching circuit 4 of the present invention form a smooth AC waveform which is respectively connected to the two contacts of the piezoelectric actuator 9, it is not the conventional polarity switching circuit as shown in FIG. 2A. The output AC voltages V o1 and V o2 of the output form a square wave on the piezoelectric actuator 9, so that the piezoelectric actuator 9 can be gradually charged in a relatively gentle manner, thereby reducing power consumption caused by rapid charging. In addition, it is also possible to reduce the occurrence of vibration at the natural resonance frequency of the piezoelectric actuator 9, thereby avoiding the noise problem generated when the piezoelectric actuator 9 is actuated, and in addition, compared with FIG. 2A The conventional polarity switching circuit 12 is configured to use seven transistor switches. The polarity switching circuit 4 of the present invention only needs to use four transistor switches (first to fourth transistor switches Q41 to Q44), so the present case The production cost of the polarity switching circuit 4 can be reduced, and the switching loss caused by the polarity switching circuit due to the on/off switching of the transistor switch can be reduced.

於其他實施例中,如第4A圖所示,第一濾波電路40可由一第一電感L1及一第一電容C1所構成,其中第一電感L1之一端係與第一電晶體開關Q41之電流輸入端以及第二電晶體開關Q42之電流輸出端連接,第一電容C1之一端係與壓電致動器9之一接點及第一電感L1之另一端連接,第一電容C1之另一端則與接地端G連接。第二濾波電路41可由一第二電感L2及一第二電容C2所構成,其中第二電感L2之一端係與第三電晶體開關Q43之電流輸入端以及第四電晶體開關Q44之電流輸出端連接,第二電容C2之一端係與壓電致動器9之另一接點及第二電感L2之另一端連接,第二電容C2之另一端則與接地端G連接。 In other embodiments, as shown in FIG. 4A, the first filter circuit 40 can be formed by a first inductor L1 and a first capacitor C1, wherein one end of the first inductor L1 is coupled to the current of the first transistor switch Q41. The input end is connected to the current output end of the second transistor switch Q42, and one end of the first capacitor C1 is connected to one of the contacts of the piezoelectric actuator 9 and the other end of the first inductor L1, and the other end of the first capacitor C1 Then connected to the ground terminal G. The second filter circuit 41 can be composed of a second inductor L2 and a second capacitor C2, wherein one end of the second inductor L2 is connected to the current input terminal of the third transistor switch Q43 and the current output terminal of the fourth transistor switch Q44. Connected, one end of the second capacitor C2 is connected to the other contact of the piezoelectric actuator 9 and the other end of the second inductor L2, and the other end of the second capacitor C2 is connected to the ground terminal G.

又於其他實施例中,如第6圖所示,第一濾波電路40亦可僅由第一電容C1所構成,此時第一電容C1之一端係與壓電致動器9之一接點、第一電晶體開關Q41之電流輸入端及第二電晶體開關Q42之電流輸出端連接,第一電容C1之另一端則維持與接地端G連接,第二濾波電路41亦可僅由第二電容C2所構成,此時第二電容C2係與壓電致動器9之另一接點、第三電晶體開關Q43之電流輸入端及第四電晶體開關Q44之電流輸出端連接,第二電容C2之另一端則維持與接地端G連接。In other embodiments, as shown in FIG. 6, the first filter circuit 40 may also be formed only by the first capacitor C1. At this time, one end of the first capacitor C1 is connected to one of the piezoelectric actuators 9. The current input end of the first transistor switch Q41 and the current output end of the second transistor switch Q42 are connected, the other end of the first capacitor C1 is maintained connected to the ground terminal G, and the second filter circuit 41 can also be only the second The capacitor C2 is configured. At this time, the second capacitor C2 is connected to the other contact of the piezoelectric actuator 9, the current input end of the third transistor switch Q43, and the current output end of the fourth transistor switch Q44. The other end of the capacitor C2 is maintained connected to the ground terminal G.

於一些實施例中,如第4A圖所,第一~第四電晶體開關Q41~Q44係可分別由NPN的雙極共接面電晶體開關(BJT)所構成,因此第一~第四電晶體開關Q41~Q44的控制端、電流輸入端以及電流輸出端分別對應為基極、源極及射極。然而於其他實施例中,如第7A、7B圖所示,第一~第四電晶體開關Q41~Q44亦可由場校電晶體開關(FET)所構成,因此第一~第四電晶體開關Q41~Q44的控制端、電流輸入端以及電流輸出端分別對應為閘極、源極及汲極。由於第7A、7B圖所示之極性切換電路12的架構與運作原理係與第4A、4B圖相似,於此不再贅述。In some embodiments, as shown in FIG. 4A, the first to fourth transistor switches Q41-Q44 are respectively formed by NPN bipolar common-surface transistor switches (BJT), so the first to fourth electrodes are The control terminal, the current input terminal and the current output terminal of the crystal switches Q41~Q44 correspond to the base, the source and the emitter, respectively. However, in other embodiments, as shown in FIGS. 7A and 7B, the first to fourth transistor switches Q41 to Q44 may also be formed by field-corrected transistor switches (FETs), and thus the first to fourth transistor switches Q41. The control terminal, current input terminal and current output terminal of ~Q44 correspond to gate, source and drain, respectively. The structure and operation principle of the polarity switching circuit 12 shown in FIGS. 7A and 7B are similar to those of FIGS. 4A and 4B, and will not be described again.

請參閱第8圖,其係為第4A圖所示之壓電致動器應用於一機構本體之實施態樣示意圖,如圖所示,該機構本體可為一流體輸送裝置8,但不以此為限,流體輸送裝置8可適用於醫藥生技、電腦科技、列印或是能源等工業,可輸送氣體或是液體,例如一噴墨印表機內之一泵浦,主要藉由壓電致動器9將電能轉換成機械能,其中壓電致動器9包含有致動片90及振動薄模91,且分別連接輸出交流電壓V1及V2,用以因應輸出交流電壓V1及V2的驅動而使致動片90及振動薄模91產生反覆動作,俾造成壓力腔室92的體積壓縮或是膨脹,使流體輸送裝置8可藉以達到傳送流體之功效。Please refer to FIG. 8 , which is a schematic diagram of a piezoelectric actuator shown in FIG. 4A applied to a mechanism body. As shown, the mechanism body can be a fluid conveying device 8 , but not For this reason, the fluid delivery device 8 can be applied to industries such as medical technology, computer technology, printing or energy, and can transport gas or liquid, such as a pump in an inkjet printer, mainly by pressure. The electric actuator 9 converts electrical energy into mechanical energy, wherein the piezoelectric actuator 9 includes an actuating plate 90 and a vibrating thin die 91, and is respectively connected to output alternating current voltages V1 and V2 for outputting alternating current voltages V1 and V2. The driving causes the actuating sheet 90 and the vibrating thin mold 91 to perform a repetitive motion, thereby causing the volume of the pressure chamber 92 to be compressed or expanded, so that the fluid transporting device 8 can achieve the effect of transferring the fluid.

 綜上所述,本案之極性切換電路係利用第一~第四電晶體開關以及第一~第二濾波電路的連接與作動來輸出為平滑交流波形之輸出交流電壓,藉此減少電力耗損,並避免壓電致動器在作動時產生噪音,同時,因本案之極性切換電路僅需利用第一~第四電晶體開關來構成,因此本案之極性切換電路的生產成本可降低,同時可減少極性切換電路因電晶體開關在進行導通或截止切換所產生的開關損耗。In summary, the polarity switching circuit of the present invention uses the connection and actuation of the first to fourth transistor switches and the first to second filter circuits to output an output AC voltage of a smooth AC waveform, thereby reducing power consumption, and The piezoelectric actuator is prevented from generating noise when it is actuated. At the same time, since the polarity switching circuit of the present invention only needs to be constructed by using the first to fourth transistor switches, the production cost of the polarity switching circuit of the present invention can be reduced, and the polarity can be reduced. The switching circuit is caused by the switching loss caused by the transistor switch being turned on or off.

本案得由熟知此技術之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。

This case has been modified by people who are familiar with the technology, but it is not intended to be protected by the scope of the patent application.

 

4‧‧‧極性切換電路 4‧‧‧Polar switching circuit

40‧‧‧第一濾波電路 40‧‧‧First filter circuit

41‧‧‧第二濾波電路 41‧‧‧Second filter circuit

9‧‧‧壓電致動器 9‧‧‧ Piezoelectric Actuator

VB-‧‧‧直流高電壓 V B- ‧‧‧ DC high voltage

V1、V2‧‧‧輸出交流電壓 V1, V2‧‧‧ output AC voltage

Vs1‧‧‧第一切換電壓 V s1 ‧‧‧ first switching voltage

Vs2‧‧‧第二切換電壓 V s2 ‧‧‧second switching voltage

Q41‧‧‧第一電晶體開關 Q41‧‧‧First transistor switch

Q42‧‧‧第二電晶體開關 Q42‧‧‧Second transistor switch

Q43‧‧‧第三電晶體開關 Q43‧‧‧The third transistor switch

Q44‧‧‧第四電晶體開關 Q44‧‧‧4th transistor switch

G‧‧‧接地端 G‧‧‧ Grounding terminal

PWM1‧‧‧第一脈衝寬度調變訊號 PWM1‧‧‧ first pulse width modulation signal

PWM2‧‧‧第一脈衝寬度調變訊號 PWM2‧‧‧ first pulse width modulation signal

L1‧‧‧第一電感 L1‧‧‧first inductance

L2‧‧‧第二電感 L2‧‧‧second inductance

C1‧‧‧第一電容 C1‧‧‧first capacitor

C2‧‧‧第二電容 C2‧‧‧second capacitor

Claims (11)

一種極性切換電路,將一直流高電壓轉換為一輸出交流電壓,以驅動一壓電致動器,包含:
一第一開關電路,接收一第一脈衝寬度調變訊號及一第二脈衝寬度調變訊號,其中該第一脈衝寬度調變訊號與該第二脈衝寬度調變訊號互為反相導通,且該第一開關電路之一端與一接地端連接,另一端連接該直流高電壓;
一第二開關電路,接收該第一脈衝寬度調變訊號及該第二脈衝寬度調變訊號,其中該第一脈衝寬度調變訊號與該第二脈衝寬度調變訊號互為反相導通,且該第二開關電路之一端與該接地端連接,另一端連接該直流高電壓;
一第一濾波電路,與該第一開關電路、該壓電致動器之一接點及該接地端連接;以及
一第二濾波電路,與該第二開關電路、該壓電致動器之另一接點及該接地端連接;
其中當該第一脈衝寬度調變訊號以及該第二脈衝寬度調變訊號交錯地進行高準位及低準位的切換時,促使該輸出交流電壓能產生平滑交流波形之交流電壓輸入至該壓電致動器之各接點。
A polarity switching circuit converts a constant current high voltage into an output AC voltage to drive a piezoelectric actuator comprising:
a first switching circuit receives a first pulse width modulation signal and a second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are in anti-phase conduction with each other, and One end of the first switch circuit is connected to a ground end, and the other end is connected to the DC high voltage;
a second switching circuit receives the first pulse width modulation signal and the second pulse width modulation signal, wherein the first pulse width modulation signal and the second pulse width modulation signal are in anti-phase conduction with each other, and One end of the second switch circuit is connected to the ground end, and the other end is connected to the DC high voltage;
a first filter circuit connected to the first switch circuit, a contact of the piezoelectric actuator and the ground; and a second filter circuit, the second switch circuit, and the piezoelectric actuator Another contact and the ground connection;
When the first pulse width modulation signal and the second pulse width modulation signal are alternately switched between the high level and the low level, the output AC voltage is generated to generate a smooth AC waveform and the AC voltage is input to the voltage. Each contact of the electric actuator.
如申請專利範圍第1項所述之極性切換電路,其中該第一開關電路由一第一電晶體開關及一第二電晶體開關所組合之電路,該第二開關電路由一第三電晶體開關及一第四電晶體開關所組合之電路。The polarity switching circuit of claim 1, wherein the first switching circuit comprises a circuit combined with a first transistor switch and a second transistor switch, and the second switch circuit comprises a third transistor A circuit in which a switch and a fourth transistor switch are combined. 如申請專利範圍第2項所述之極性切換電路,其中該第一電晶體開關至該第四電晶體開關各別具有一控制端、一電流輸入端,以及一電流輸出端,其中該第一電晶體開關之該電流輸入端與該第二電晶體開關之該電流輸出端連接導通,且該第三電晶體開關之該電流輸入端與該第四電晶體開關之該電流輸出端連接導通。The polarity switching circuit of claim 2, wherein the first transistor switch to the fourth transistor switch respectively have a control terminal, a current input terminal, and a current output terminal, wherein the first The current input end of the transistor switch is connected to the current output end of the second transistor switch, and the current input end of the third transistor switch is connected to the current output end of the fourth transistor switch. 如申請專利範圍第3項所述之極性切換電路,其中該第一濾波電路由一第一電感及一第一電容所構成,該第一電感與該壓電致動器之該接點、該第一電晶體開關之該電流輸入端以及該第二電晶體開關之該電流輸出端連接,該第一電容與該壓電致動器之該接點、該第一電感及該接地端連接,該第二濾波電路由一第二電感及一第二電容構成,該第二電感與該壓電致動器之另一該接點、該第三電晶體開關之該電流輸入端以及該第四電晶體開關之該電流輸出端連接,該第二電容與該壓電致動器之另一該接點、該第二電感及該接地端連接。The polarity switching circuit of claim 3, wherein the first filter circuit is formed by a first inductor and a first capacitor, the first inductor and the contact of the piezoelectric actuator, The current input end of the first transistor switch is connected to the current output end of the second transistor switch, and the first capacitor is connected to the contact of the piezoelectric actuator, the first inductor and the ground end, The second filter circuit is composed of a second inductor and a second capacitor, the second inductor and the other contact of the piezoelectric actuator, the current input terminal of the third transistor switch, and the fourth The current output of the transistor switch is connected, and the second capacitor is connected to the other contact of the piezoelectric actuator, the second inductor and the ground. 如申請專利範圍第3項所述之極性切換電路,其中該第一濾波電路由該第一電容所構成,該第一電容與該壓電致動器之該接點、該第一電晶體開關之該電流輸入端、該第二電晶體開關之該電流輸出端以及該接地端連接,該第二濾波電路由該第二電容所構成,該第二電容與該壓電致動器之另一該接點、該第三電晶體開關之該電流輸入端、該第四電晶體開關之該電流輸出端以及該接地端連接。The polarity switching circuit of claim 3, wherein the first filter circuit is formed by the first capacitor, the first capacitor and the piezoelectric actuator, the first transistor switch The current input terminal, the current output terminal of the second transistor switch, and the ground terminal are connected, the second filter circuit is formed by the second capacitor, and the second capacitor and the piezoelectric actuator are another The contact, the current input end of the third transistor switch, the current output end of the fourth transistor switch, and the ground end are connected. 如申請專利範圍第2項所述之極性切換電路,其中該第一電晶體開關至該第四電晶體開關為雙極共接面電晶體。The polarity switching circuit of claim 2, wherein the first transistor switch to the fourth transistor switch are bipolar common junction transistors. 如申請專利範圍第6項所述之極性切換電路,其中該第一電晶體開關至該第四電晶體開關為NPN雙極共接面電晶體。The polarity switching circuit of claim 6, wherein the first transistor switch to the fourth transistor switch are NPN bipolar common junction transistors. 如申請專利範圍第2項所述之極性切換電路,其中該第一電晶體開關至該第四電晶體開關為場效電晶體。The polarity switching circuit of claim 2, wherein the first transistor switch to the fourth transistor switch is a field effect transistor. 如申請專利範圍第1項所述之極性切換電路,其中該第一脈衝寬度調變訊號在進行高準位及低準位的切換時,該第二脈衝寬度調變訊號為低準位,當該第二脈衝寬度調變訊號在進行高準位及低準位的切換時,該第一脈衝寬度調變訊號為低準位。The polarity switching circuit of claim 1, wherein the second pulse width modulation signal is at a low level when the first pulse width modulation signal is switched between a high level and a low level. When the second pulse width modulation signal is switched between the high level and the low level, the first pulse width modulation signal is at a low level. 如申請專利範圍第1項所述之極性切換電路,其中該第一脈衝寬度調變訊號與該第二脈衝寬度調變訊號分別由高頻逐漸降低至低頻再逐漸升高至高頻。The polarity switching circuit of claim 1, wherein the first pulse width modulation signal and the second pulse width modulation signal are gradually reduced from a high frequency to a low frequency and then gradually increased to a high frequency. 如申請專利範圍第1項所述之極性切換電路,其中該輸出平滑交流波形之交流電壓係於半週期內於一第一時間內線性達到一最大電壓的一第一比例值,接續呈現上升圓滑波形並於一第一設定時間內到達該最大電壓,接續於一第二時間內持平,接續呈現下降圓滑波形並於一第二設定時間內降低至最大電壓的一第二比例值,接續線性下降至零電壓。The polarity switching circuit of claim 1, wherein the AC voltage of the output smooth AC waveform is linearly reaches a first proportional value of a maximum voltage in a first period in a half cycle, and then rises and sleek. The waveform reaches the maximum voltage within a first set time, continues to be flat for a second time, continues to exhibit a falling rounded waveform, and decreases to a second ratio of the maximum voltage for a second set time, followed by a linear decrease To zero voltage.
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