TWI523019B - Method of booting system with non-volatile memory device and related memory apparatus - Google Patents

Description

Memory device and booting the system using non-volatile memory components method

The present invention relates to a memory device; and more particularly to a method of booting a system using a non-volatile memory component and associated memory device.

In the process of erasing a non-volatile memory, more specifically, in the process of erasing a particular block in a non-volatile memory, unintended interruptions, such as unintended power interruptions, may occur. In this case, the complete erase operation will not be successfully performed. For example, referring to FIG. 1, if a memory block has completed the preprogramming step (step 12), the over Erase Correction (OEC) step (step) is not completed when the power is interrupted. 16), because the over-wipe phenomenon may cause leakage of the bit line. When the system is powered again, the bit line leakage caused by the memory block that fails to complete the OEC step may affect the associated memory block sharing the same bit line. If the associated memory block is used to store the booting code, the boot process is executed after the system is re-powered. The system may not be able to read the boot code. This can result in a very long boot time or the system may not boot.

With the rapid development of handheld electronic devices, system stability is an important issue in many consumer products. In addition, more and more memory blocks are combined in high-capacity memory components. Therefore, it is necessary to solve the above-mentioned scheme of bit line leakage phenomenon.

A method for booting a system using a non-volatile memory component according to an embodiment of the invention includes the steps of: reading at least one memory corresponding to the non-volatile memory component when the system is powered a status flag of the block, the flag value of the status flag indicating whether a complete erasing operation applied to the memory block has been completed; according to the flag of the status flag, the corresponding memory The block selectively performs a leakage current suppression process; and powering up the system based on one of the boot codes stored in the non-volatile memory component.

A memory device according to an embodiment of the invention includes a non-volatile memory component, a state register, a control unit and a leakage current correction unit. The non-volatile memory component includes a plurality of memory blocks. The state register is electrically coupled to the non-volatile memory component and configured to store a state flag for indicating one of the at least one memory block applied to the non-volatile memory component Whether the complete erase operation has been completed. The control unit is configured to read the power after the memory device is powered The flag value of the status flag. The leakage current correcting unit is electrically connected to the control unit, and is configured to selectively perform a leakage current suppression process on the memory blocks according to the flag value of the status flag.

10-18‧‧‧Steps

200‧‧‧ memory device

202‧‧‧Non-volatile memory components

204‧‧‧Status Register Library

206‧‧‧ or gate circuit

208‧‧‧Control unit

210‧‧‧Leakage current correction unit

212‧‧‧First bias voltage generator

214‧‧‧Second bias voltage generator

216‧‧‧Repeating unit

32‧‧‧ boot block

34‧‧‧Information block

36‧‧‧Sense Amplifier

400‧‧‧complete erase operation

402-414‧‧‧Steps

500‧‧‧ boot method

502-512‧‧‧Steps

600‧‧‧ boot method

602-612‧‧‧Steps

BL‧‧‧ bit line

Figure 1 shows a flow chart of a conventional complete erase operation.

2 is a block diagram showing a memory device in accordance with an embodiment of the present invention.

Figure 3 shows a schematic diagram of two memory blocks sharing a same bit line.

4 shows a flow chart of a complete erase operation of one of the non-volatile memory elements in accordance with an embodiment of the present invention.

5 shows a flow chart of one method of booting a system using a non-volatile memory component, in accordance with an embodiment of the present invention.

6 shows a flow chart of a method for booting a system using a non-volatile memory element in accordance with another embodiment of the present invention.

2 shows a block diagram of a memory device 200 in accordance with an embodiment of the present invention. Referring to FIG. 2, the memory device 200 includes a non-volatile memory component 202, a state register bank 204, a gate circuit 206, a control unit 208, and a leakage current correction unit 210. The leakage current correcting unit 210 includes a first bias voltage generator 212, a second bias voltage generator 214, and a re-erasing unit 216.

Referring to FIG. 2, the non-volatile memory component 202 includes N memory blocks [0] to memory blocks [N-1] to store normal data or boot codes, where N is a positive integer. For example, in the present embodiment, the memory cell system in the memory block [0] is constructed to store normal data, and the memory cell system in the memory block [1] is constructed to store the boot code. In addition, the memory cell in the memory block [0] and the memory cell in the memory block [1] are electrically connected to the same bit line. In order to reduce the wafer area of the memory element 202, the memory cell in the memory block [0] and the memory cell in the memory block [1] have no isolation elements therebetween.

Referring to FIG. 3, a schematic diagram of two memory blocks sharing the same bit line BL is shown, wherein the boot block 32 is used to store the boot code, and the data block 34 is used to store normal data. It is assumed that the memory cell of the data block 34 is over-erased, and the power supply is interrupted when the OEC step is not completed, due to the memory cell in the boot block 32 and the memory cell share in the data block 34. The same bit line, when the boot process is performed after power transmission, the read failure will be read when the boot code is read from the boot block 32. This is due to the leakage of the bit line caused by the erase phenomenon (Ileak>0μA), so that the sense amplifier (SA) 36 reads the logic “0” data of the selected cell in the boot block 32. The wrong current is sensed and the wrong data value is read. This can result in a very long boot time or the system may not boot.

Referring to FIG. 2, the state register library 204 includes N status registers [0] through [N-1] in this embodiment. The registers [0] to [N-1] are used for storage The status flags FL[0] to FL[N-1], wherein each status flag is used to indicate whether the corresponding memory block in the non-volatile memory element 202 has successfully completed a complete erase operation. For example, FL[0] indicates whether the memory block [0] has successfully completed a complete erase operation, and FL[1] indicates whether the memory block [1] has successfully completed a complete erase operation. ,So on and so forth. However, the invention should not be limited thereto. In other embodiments, the state register library 204 can include fewer than N state registers. That is, there may be multiple memory blocks assigned to a status flag.

4 shows a flow diagram of a complete erase operation 400 of the non-volatile memory component 202 in accordance with an embodiment of the present invention. Referring to Figure 4, step 402 begins first, wherein at least one particular block of the non-volatile memory element 202 is ready to be erased. Next, in step 404, the status flag FL corresponding to the temporary register of the at least one particular block in the status register bank 204 is set to logic "1". In step 406, a pre-programming operation is performed on the memory cells in the particular block. In step 408, an erase operation is performed on the memory cells in the particular block. In step 406, an erase erase correction operation is performed on the memory cells in the particular block. When the memory cells in the particular block have sequentially performed the pre-programming operation 406, the erase operation 408 and the erase erase correction operation 410, the state register library 204 corresponds to the specific regions. The flag of the status flag FL of the block register is set to logic "0".

Figure 5 shows the use of non-volatile notes in accordance with an embodiment of the present invention. A flow chart of a method 500 for booting a system into a system. Those skilled in the art should recognize that the practice of the present invention is not limited to the need to implement each of the steps of FIG. 5 one by one or accurately. For example, an intermediate step or partial modification can be added between each step in FIG.

Referring to Figure 5, step 502 is first performed, in which power is supplied to the memory device 200. Next, in step 504, a total status flag OFL corresponding to all of the memory blocks [0] through [N-1] in the non-volatile memory element 202 is read. Then, in step 506, it is determined whether the flag value of the total status flag OFL is logic "1", and if not, the power-on code stored in the non-volatile memory element 202 is turned on; if so, check each The status flag FL is used to confirm which flag value is logical "1".

In step 508, if the flag of the status flag FL is logic "1", it indicates that the corresponding block has not completed the complete erasing operation, for example, the OEC operation has not been performed. Therefore, in step 510, a leakage current suppression procedure must be performed on the block corresponding to the status flag value of logic "1". Then, in step 512, the power-on code stored in the non-volatile memory element 202 can be turned on.

Referring to FIG. 2, the total status flag OFL is generated by the OR gate circuit 206. The total status flag OFL is used to indicate if any incomplete erase operations have occurred. If the flag of the total status flag OFL is logic "1", indicating that one or more memory blocks have not completed the erasing method 400, the control unit 208 sequentially reads the corresponding to the memory area. The shape of the block [0] to [N-1] The flag value of the flag is used to find the block corresponding to the flag value of the logical "1". Next, a leakage current suppression program is added to the unselected memory cells in the found block to ensure that the sense amplifier in Figure 3 does not sense the erroneous current when performing the power-on procedure.

Details of the leakage current suppression program will be described in detail below by way of examples. When the flag of the total status flag OFL is logic "0", it indicates that all memory blocks [0] to [N-1] in the non-volatile memory element 202 have completely performed the pre-program operation. , erase operations and OEC operations. In this case, the first bias voltage generator 212 in FIG. 2 applies a first bias voltage, that is, a normal bias voltage is applied to the unselected memory in the memory blocks. Body unit cell. Conversely, when the flag of the total status flag OFL is logic "1", it indicates that at least one memory block of the non-volatile memory element 202 has not completed a complete erase operation. In this case, the second bias voltage generator 214 of FIG. 2 applies a second bias voltage, that is, a suppression bias voltage is applied to all unselected ones of the memory blocks. The memory cell, or at least all of the unselected memory cells in the boot block. In this embodiment, the second bias voltage is a negative voltage, and the voltage value is sufficient to turn off the erase memory cell. In step 512, the system is powered on based on the boot code stored in the non-volatile memory component 202. When the system is successfully powered on, the memory block corresponding to the flag flag of the status flag FL is logical "1", or is restored or maintained in the original state.

Figure 6 shows the use of non-volatiles in accordance with another embodiment of the present invention. A flowchart of one method 600 of booting a memory component to a system. Those skilled in the art will recognize that the practice of the present invention is not limited to the need to implement each of the steps of FIG. 6 one by one or accurately. For example, an intermediate step or partial modification can be added between each step in FIG.

Referring to Figure 6, step 602 is first performed, in which power is supplied to the memory device 200. Next, in step 604, a total status flag OFL corresponding to all of the memory blocks [0] through [N-1] in the non-volatile memory element 202 is read. Thereafter, in step 606, it is checked whether the flag value of the total status flag OFL is logic "1", and if so, step 608 is performed, and if not, step 612 is performed. In step 608, the flag values for each of the status flags FL[0] through FL[N-1] are examined. In step 610, a leakage current repair operation is performed on the memory block corresponding to the flag value of logic "1". In step 612, the system is powered on based on the boot code stored in the non-volatile memory component 202.

Referring to FIG. 2, the total status flag OFL is generated by the OR gate circuit 206. The total status flag OFL is used to indicate if any incomplete erase operations have occurred. In step 604, the flag value of the total status flag OFL is read. In step 606, if the flag of the total status flag OFL is logic "0", step 612 is performed; if the flag of the total status flag OFL is logic "1", the control is performed in step 608. A single 208 element will further perform an inspection operation for each of the status flags FL[0] to FL[N-1]. This is because if the flag of the total status flag OFL is logic "1", it means that the non-volatile memory element 202 has At least one of the memory blocks does not complete the complete erasing step, so the control unit 208 will find the block corresponding to the flag value of the logic "1". Then, the leakage current correcting unit 210 performs a leakage current repair operation on all the memory cells of the found block to ensure that the sense amplifier in FIG. 3 does not occur when the system attempts to read the associated block. The status of misjudgment. More specifically, when the total status flag OFL indicates that at least one memory block has not completed the complete erase step, the re-erase unit 216 performs re-memory of all memory cells in the memory block. Wipe the operation.

Therefore, the potential problem of booting in the prior art can be avoided by the method disclosed by the present invention. The stability of the system can be improved, and the associated memory blocks sharing the same bit line will not have bit line leakage.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

200‧‧‧ memory device

202‧‧‧Non-volatile memory components

204‧‧‧Status Register Library

206‧‧‧ or gate circuit

208‧‧‧Control unit

210‧‧‧Leakage current correction unit

212‧‧‧First bias voltage generator

214‧‧‧Second bias voltage generator

216‧‧‧Repeating unit

Claims (11)

A method of booting a system using a non-volatile memory component, the non-volatile memory component comprising a boot block and a plurality of data blocks, wherein the memory cell and the data in the boot block The memory cells in the block are electrically connected to the same bit line, the method comprising: when the system is powered, reading the boot block and the data block corresponding to the non-volatile memory element a status flag, the flag value of the status flag indicating whether a complete erase operation applied to the non-volatile memory element has been completed; according to the flag of the status flag, the corresponding boot area The block and the data blocks selectively perform a leakage current suppression procedure; and powering up the system based on one of the boot codes stored in the boot block. The method of claim 1, wherein the step of selectively performing the leakage current suppression procedure on the corresponding boot block and the data blocks according to the flag value of the status flag comprises: The status flag indicates that when the complete erase operation applied to the non-volatile memory element has been completed, applying a first bias voltage to the boot block and the unselected memory in the data block a unit cell; and when the status flag indicates that the complete erase operation applied to the non-volatile memory element is not complete, applying a second bias voltage to the boot block and the data blocks Unselected memory cell; The voltage value of the second bias voltage is lower than the voltage value of the first bias voltage. The method of claim 2, wherein the second bias voltage is a negative voltage and the voltage value is sufficient to turn off the erase memory cell. According to the method of claim 1, the method further comprises: when the system is powered on, performing a leakage current repair operation on the data blocks. The method of claim 1, wherein the step of selectively performing the leakage current suppression procedure on the corresponding boot block and the data blocks according to the flag value of the status flag comprises: The status flag indicates that the memory cell in the data block is re-erased when the complete erase operation applied to the non-volatile memory element is not completed. The method of claim 1, wherein the step of reading the status flag corresponding to the boot block and the data blocks in the non-volatile memory element comprises: reading the non-volatile memory a status flag of each of the data blocks; and performing an OR operation on all of the status flags of the data blocks to obtain a total status flag; and the method further comprises: checking the total The status flag is used to confirm whether the non-volatile memory element has at least one data block that does not complete the complete erase step. A memory device comprising: a non-volatile memory component, comprising a boot block and a plurality of data blocks, the memory cell in the boot block and the memory cell in the data block Connected to the same bit line; a state register electrically coupled to the non-volatile memory element, configured to store a status flag for indicating application to the non-volatile memory element Whether a complete erase operation has been completed; a control unit configured to read a flag value of the status flag after powering the memory device; and a leakage current correction unit electrically connected to the control unit And configured to selectively perform a leakage current suppression process on the non-volatile memory component according to the flag value of the state flag, thereby completing a booting process. The memory device of claim 7, wherein the leakage current correcting unit comprises: a first bias voltage generator configured to indicate the integrity applied to the non-volatile memory element when the status flag indicates When the erasing operation is completed, applying a first bias voltage to the boot block and the unselected memory cells in the data blocks; and a second bias voltage generator configured to When the status flag indicates that the complete erase operation applied to the non-volatile memory element is not completed, applying a second bias voltage to the unselected memory cell in the non-volatile memory element ; The voltage value of the second bias voltage is lower than the voltage value of the first bias voltage. The memory device of claim 8 wherein the second bias voltage is a negative voltage and the voltage value is sufficient to turn off the erased memory cell. The memory device of claim 7, wherein the leakage current correction unit comprises: a re-wiping unit configured to indicate the complete erase operation applied to the non-volatile memory element when the status flag indicates When it is not completed, the data blocks are repeatedly erased. The memory device of claim 7 further comprising: a plurality of state registers; and an OR gate circuit electrically connected to the state registers configured to generate a total status flag; The control unit reads the flag value of the total status flag after the memory device is powered, and when the total status flag indicates that the non-volatile memory element has not completed the complete erasing operation, the control unit individually The status registers are read to find the data block that did not complete the complete erase operation.