CN104575605B - Storage arrangement and the method booted up using nonvolatile memory to system - Google Patents
Storage arrangement and the method booted up using nonvolatile memory to system Download PDFInfo
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Abstract
Storage arrangement and the method booted up using nonvolatile memory to system.A kind of storage arrangement according to an embodiment of the invention, include a non-volatile memory device, a status register, a control unit and a Leakage Current Calibration Method unit.The non-volatile memory device includes boot block and multiple data blocks, and the wherein memory crystal cell in the memory crystal cell and the plurality of data block in the boot block is electrically connected to identical bit line.The status register is electrically connected to the non-volatile memory device, and it is configured to store a Status Flag, and whether the Status Flag has been completed to indicate to apply to the complete running of erasing of one in the non-volatile memory device.The control unit is configured to read the value of statistical indicant of the Status Flag after storage arrangement power supply.The Leakage Current Calibration Method unit is electrically connected to the control unit, and it is configured optionally performs a drain current suppressing program to the non-volatile memory device with the value of statistical indicant according to the Status Flag.
Description
Technical field
The present invention relates to a kind of storage arrangement；It is more particularly to a kind of that system is carried out using non-volatile memory device
The method of start and the storage arrangement of correlation.
Background technology
During a nonvolatile memory of erasing, more specifically, in a nonvolatile memory of erasing
During particular block, it may occur that unexpected interruption, such as unexpected power interruptions.In this situation, by nothing
Method successful execution is completely erased running.For example, reference picture 1 a, if memory block has completed pre-programmed
(preprogramming) step (step 12), but in the supply break when fail to complete correction (the Over Erase that erase
Correction, OEC) step (step 16), then it may cause the electric leakage of bit line due to crossing phenomenon of erasing.When system power transmission once again
When, the correlation of shared same bit lines may be influenced whether by failing to complete the bit line leakage caused by the memory block of OEC steps
Join memory block.If the associated memory block is used for storing boot code (booting code), in system again
When boot program is performed after power transmission, system possibly can not read boot code.This can cause the available machine time grown very much, or, system
It may cannot be started up.
With flourishing for portable electric device, the stability of system is one important in many consumer products
Problem.In addition, increasing memory block can be merged in the memory component of high power capacity.Therefore, it is necessary to solve above-mentioned
The scheme of bit line leakage phenomenon.
The content of the invention
A kind of side booted up using a non-volatile memory device to a system according to an embodiment of the invention
Method, comprise the steps of：When the system power supply, at least memory corresponded in the non-volatile memory device is read
One Status Flag of block, the value of statistical indicant instruction of the Status Flag, which applies to a complete running of erasing of the memory block, is
It is no to have completed；One drain current suppressing journey is optionally performed to corresponding memory block according to the value of statistical indicant of the Status Flag
Sequence；And the system is booted up according to the boot code being stored in the non-volatile memory device.
A kind of storage arrangement according to an embodiment of the invention, comprising a non-volatile memory device, a state is posted
Storage, a control unit and a Leakage Current Calibration Method unit.The non-volatile memory device includes multiple memory blocks.Should
Status register is electrically connected to the non-volatile memory device, and it is configured to store a Status Flag, and the Status Flag is used
Whether complete erase applied with instruction at least memory block in the non-volatile memory device operate
Complete.The control unit is configured to read the value of statistical indicant of the Status Flag after storage arrangement power supply.The Leakage Current Calibration Method
Unit is electrically connected to the control unit, and it is configured with the value of statistical indicant according to the Status Flag to such memory block selectivity
Ground performs a drain current suppressing program.
Brief description of the drawings
Fig. 1 shows the flow chart for running of completely being erased known to one.
Fig. 2 shows the block schematic diagram of the storage arrangement with reference to one embodiment of the invention.
Fig. 3 shows the schematic diagram of two memory blocks of a shared same bit lines.
Fig. 4 shows the stream of a complete running of erasing of the non-volatile memory device according to an embodiment of the invention
Cheng Tu.
Fig. 5 shows the side according to an embodiment of the invention booted up using non-volatile memory device to system
The flow chart of method.
Fig. 6 show it is according to another embodiment of the present invention system is booted up using non-volatile memory device one
The flow chart of method
【Symbol description】
10-18 steps
200 storage arrangements
202 non-volatile memory devices
204 status register storehouses
206 OR circuits
208 control units
210 Leakage Current Calibration Method units
212 first bias voltage generators
214 second bias voltage generators
216 erased cells again
32 boot blocks
34 data blocks
36 sensing amplifiers
400 complete runnings of erasing
402-414 steps
500 starting-up methods
502-512 steps
600 starting-up methods
602-612 steps
BL bit lines
Embodiment
Fig. 2 shows the block schematic diagram of the storage arrangement 200 with reference to one embodiment of the invention.Reference picture 2, the storage
Device device 200 includes a non-volatile memory device 202, a status register storehouse 204, an OR circuit 206, a control list
The Leakage Current Calibration Method unit 210 of member 208 and one.The Leakage Current Calibration Method unit 210 includes one first bias voltage generator 212,
One second bias voltage generator 214 and again and again erased cell 216.
Reference picture 2, the non-volatile memory device 202 include N number of memory block [0] to memory block [N-1]
To store normal data or boot code, wherein N is a positive integer.For example, in the present embodiment in memory block [0]
Memory crystal cell construction is to store normal data, and the memory crystal cell construction in memory block [1] is to store boot code.This
Outside, the memory crystal cell in the memory crystal cell and memory block [1] in memory block [0] is electrically connected to identical position
Line.In order to reduce the chip area of the memory component 202, memory crystal cell and memory areas in memory block [0]
Memory crystal cell in block [1] has no isolation element to each other.
Fig. 3 is refer to, it shows the schematic diagram of a shared same bit lines BL two memory blocks, wherein boot block 32
To store boot code, and data block 34 is storing normal data.Assuming that the memory crystal cell of the data block 34 is by mistake
Degree is erased, and the power interruptions when failing to complete OEC steps, due to the memory crystal cell in boot block 32 and data block 34
In memory crystal cell share same bit line, after power transmission carry out boot program when, from boot block 32 read boot code when
Failure can be read.This was due to the bit line leakage (Ileak caused by phenomenon that erases>0 μ A) so that sensing amplifier (Sense
Amplifier, SA) 36 sensed in the logic zero data of the selected structure cell in reading boot block 32 mistake electric current,
And then read the data value of mistake.This can cause the available machine time grown very much, or, system may cannot be started up.
Reference picture 2, in the present embodiment the status register storehouse 204 include N number of status register [0] to [N-1].It is such
Register [0] to [N-1] is to storage state flags FL [0] to FL [N-1], and each of which Status Flag is indicating that this is non-easily
Whether corresponding memory block is successfully completed a complete running of erasing in the property lost memory component 202.For example, FL
[0] indicate whether memory block [0] is successfully completed a complete running of erasing, and FL [1] instruction memory blocks [1] are
No to be successfully completed a complete running of erasing, the rest may be inferred.However, the present invention should not be as limit.In other embodiments
The status register storehouse 204 may include to be less than N number of status register.That is, there may be multiple memory blocks to be assigned to one
Status Flag.
Fig. 4 shows a complete running of erasing of the non-volatile memory device 202 according to an embodiment of the invention
400 flow chart.Reference picture 4, start to carry out step 402 first, wherein have at least one in the non-volatile memory device 202
Individual particular block prepares to be erased.Then, in step 404, at least one spy is corresponded in the status register storehouse 204
Logical one can be set as by determining the Status Flag FL of the register of block.In a step 406, to the storage in such particular block
Device structure cell performs pre-programmed running.In a step 408, one is performed to the memory crystal cell in such particular block to erase fortune
Make.In a step 406, one is performed to the memory crystal cell in such particular block and crosses correction running of erasing.When such given zone
Memory crystal cell in block sequentially performs pre-programmed running 406, erases after operating 408 and crossing correction running 410 of erasing, by this
The value of statistical indicant that the Status Flag FL of the register of such particular block is corresponded in status register storehouse 204 is set as logical zero.
Fig. 5 shows the side according to an embodiment of the invention booted up using non-volatile memory device to system
The flow chart of method 500.The execution that those skilled in the art should realize the present invention is not limited to that Fig. 5 must be implemented one by one or exactly
In each step.For example, increase intermediate steps in Figure 5 between each step that can be or carry out local modification.
Reference picture 5, step 502 is carried out first, provide electric power to the storage arrangement 200 in step 502.Then, exist
In step 504, read the whole memory blocks [0] to [N-1] corresponded in the non-volatile memory device 202 one is total
Status Flag OFL.Afterwards, in step 506, whether the value of statistical indicant for judging total Status Flag OFL is logical one, if not,
Boot code according to being stored in the non-volatile memory device 202 boots up；If it is, check each Status Flag FL
To confirm whichever value of statistical indicant as logical one.
In step 508, if Status Flag FL value of statistical indicant is logical one person, block corresponding to expression has not completed
Whole running of erasing, such as not yet carry out OEC runnings.Therefore, must be in step 510 logic to correspondence to status flag value
The drain current suppressing program of onblock executing one of " 1 ".Then, in step 512 can be according to being stored in the nonvolatile memory
Boot code in element 202 boots up.
Reference picture 2, total Status Flag OFL are as produced by the OR circuit 206.Total Status Flag OFL is referring to
Whether show has any incomplete running of erasing.If the value of statistical indicant of total Status Flag OFL is logical one, indicate
One or the unfinished erasing method 400 of the memory block more than one, therefore the control unit 208 can sequentially read and correspond to extremely
Memory block [0] is to the value of statistical indicant of the Status Flag of [N-1] to find out the block corresponding to the value of statistical indicant of logical one.Connect
, the non-selected memory crystal cell that a drain current suppressing program can be added in found block, to ensure the sense in Fig. 3
Amplifier will not sense the electric current of mistake when performing boot program.
The details of the drain current suppressing program will be described in detail for embodiment below.When the mark of total Status Flag OFL
Be worth for logical zero when, represent whole memory blocks [0] to [N-1] in the non-volatile memory device 202 intactly
Pre-programmed running is performed, erase running and OEC runnings.In this situation, meeting of the first bias voltage generator 212 in Fig. 2
Apply one first bias voltage, that is, a normal bias voltage can apply the non-selected storage into such memory block
Device structure cell.Conversely, when the value of statistical indicant of total Status Flag OFL is logical one, the non-volatile memory device 202 is represented
In an at least memory block do not complete complete running of erasing.In this situation, second bias voltage production in Fig. 2
Raw device 214 can apply one second bias voltage, that is, a suppression bias voltage can apply owning into such memory block
Non-selected memory crystal cell, or all non-selected memory crystal cells at least in boot block.In the present embodiment
In, second bias voltage is a negative voltage, and magnitude of voltage is enough to end a mistake erasing memory structure cell.In step 512, should
System boots up according to the boot code being stored in the non-volatile memory device 202.After the system is successfully started shooting,
It can be repaired for the memory block of logical one corresponding to Status Flag FL value of statistical indicant, or be maintained at original state.
Fig. 6 show it is according to another embodiment of the present invention system is booted up using non-volatile memory device one
The flow chart of method 600.The execution that those skilled in the art should realize the present invention is not limited to one by one or exactly to implement
Each step in Fig. 6.For example, increase intermediate steps in figure 6 between each step that can be or carry out local modification.
Reference picture 6, step 602 is carried out first, provide electric power to the storage arrangement 200 in step 602.Then, exist
In step 604, read the whole memory blocks [0] to [N-1] corresponded in the non-volatile memory device 202 one is total
Status Flag OFL.Afterwards, in step 606, whether procuratorial work total Status Flag OFL value of statistical indicant is logical one, if it is,
Step 608 is carried out, if not, carrying out step 612.In step 608, the such Status Flag FL [0] of procuratorial work is into FL [N-1]
The value of statistical indicant of each.In step 610, repaiied to carrying out a leakage current corresponding to value of statistical indicant for the memory block of logical one
Multiple running.In step 612, the system is opened according to the boot code being stored in the non-volatile memory device 202
Machine.
Reference picture 2, total Status Flag OFL are as produced by the OR circuit 206.Total Status Flag OFL is referring to
Whether show has any incomplete running of erasing.In step 604, the value of statistical indicant of total Status Flag OFL can be read.
In step 606, if the value of statistical indicant of total Status Flag OFL is logical zero, step 612 can be carried out；If total Status Flag
OFL value of statistical indicant is logical one, in step 608 208 yuan of meetings of the control list to such Status Flag FL [0] to FL's [N-1]
Each further performs one and checks running.If the value of statistical indicant that this is due to total Status Flag OFL is logical one, representing should
There is at least one memory block not complete complete erase step, therefore the control list in non-volatile memory device 202
Member 208 can find out the block corresponding to the value of statistical indicant of logical one.Then, the Leakage Current Calibration Method unit 210 understands the area to being found out
All memory crystal cells of block carry out leakage current reparation running, to ensure that system will not occur when attempting and reading associated block
The erroneous judgement situation of sensing amplifier in Fig. 3.More specifically, when total Status Flag OFL instructions have at least one memory
Block do not complete it is complete erase step when, erased cell 216 can enter to all memory crystal cells in memory block again for this
Capable running of erasing again.
Therefore, the start potential problems in known technology can be avoided by the method disclosed in the present.The stabilization of system
Degree can improve, and the associated memory block of shared same bit lines does not have the phenomenon of bit line leakage.
The technology contents and technical characterstic of the present invention have revealed that as above, but those skilled in the art are still potentially based on this hair
Bright teaching and announcement and make a variety of replacements and modification without departing substantially from spirit of the present invention.Therefore, protection scope of the present invention should not
It is limited to those disclosed embodiments, and various replacements and modification without departing substantially from the present invention should be included, and is appended claims
Claimed scope is covered.
Claims (11)
1. a kind of method booted up using a non-volatile memory device to a system, the non-volatile memory device
Include boot block and multiple data blocks, wherein depositing in the memory crystal cell and the plurality of data block in the boot block
Reservoir structure cell is electrically connected to identical bit line, and this method includes：
When the system power supply, reading corresponds to the boot block and the plurality of data block in the non-volatile memory device
A Status Flag, the value of statistical indicant instruction of the Status Flag applies to a complete fortune of erasing of the non-volatile memory device
Whether work has been completed；
One is optionally performed to the corresponding boot block and the plurality of data block according to the value of statistical indicant of the Status Flag
Drain current suppressing program；And
A boot code according to being stored in the boot block boots up to the system.
2. the method as described in claim 1, wherein this is according to the value of statistical indicant of Status Flag start area corresponding to this
Block and the plurality of data block optionally perform the step of drain current suppressing program and included：
When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device has been completed, apply
Non-selected memory crystal cell in one first bias voltage to boot block and the plurality of data block；And
When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device does not complete, apply
Non-selected memory crystal cell in one second bias voltage to boot block and the plurality of data block；
Wherein, the magnitude of voltage of second bias voltage is less than the magnitude of voltage of first bias voltage.
3. method as claimed in claim 2, wherein second bias voltage are a negative voltage, and magnitude of voltage is enough to end a mistake
Erasing memory structure cell.
4. the method as described in claim 1, also include：
After the system boot, leakage current reparation running is performed to the plurality of data block.
5. the method as described in claim 1, wherein this is according to the value of statistical indicant of Status Flag start area corresponding to this
Block and the plurality of data block optionally perform the step of drain current suppressing program and included：
When the complete running of erasing that Status Flag instruction applies to the non-volatile memory device does not complete, to this
Memory crystal cell in multiple data blocks is erased running again.
6. start area that the method as described in claim 1, the wherein reading are corresponded in the non-volatile memory device
The step of block and the Status Flag of the plurality of data block, includes：
Read a Status Flag of each data block in the non-volatile memory device；And
By performing one or computing to all Status Flags of the data block, use and obtain a total Status Flag；And the party
Method also includes：
Total Status Flag is checked to confirm whether there is an at least data block not complete in the non-volatile memory device
Complete step of erasing.
7. a kind of storage arrangement, including：
One non-volatile memory device, comprising boot block and multiple data blocks, the memory crystal cell in the boot block
Identical bit line is electrically connected to the memory crystal cell in the plurality of data block；
One status register, the non-volatile memory device is electrically connected to, it is configured to store a Status Flag, the state
Indicate to indicate to apply to the complete running of erasing of one in the non-volatile memory device whether completed；
One control unit, it is configured to read the value of statistical indicant of the Status Flag after storage arrangement power supply；And
One Leakage Current Calibration Method unit, is electrically connected to the control unit, and it is configured with the value of statistical indicant according to the Status Flag to institute
State non-volatile memory device and optionally perform a drain current suppressing program, to complete boot program.
8. storage arrangement as claimed in claim 7, wherein the Leakage Current Calibration Method unit include：
One first bias voltage generator, it is configured with when Status Flag instruction applies into the non-volatile memory device
The complete running of erasing when having completed, apply one first bias voltage into the boot block and the plurality of data block
Non-selected memory crystal cell；And
One second bias voltage generator, it is configured with when Status Flag instruction applies into the non-volatile memory device
The complete running of erasing when not completing, apply and be not chosen in one second bias voltage to the non-volatile memory device
The memory crystal cell selected；
Wherein, the magnitude of voltage of second bias voltage is less than the magnitude of voltage of first bias voltage.
9. storage arrangement as claimed in claim 8, wherein second bias voltage are a negative voltage, and magnitude of voltage is enough to cut
Only one cross erasing memory structure cell.
10. storage arrangement as claimed in claim 7, wherein the Leakage Current Calibration Method unit include：
Erased cell again and again, its configure with when Status Flag instruction apply in the non-volatile memory device this is complete
Erase running do not complete when, running of being erased again and again to the plurality of data interval.
11. storage arrangement as claimed in claim 7, is also included：
Multiple status registers；And
One OR circuit, the status register is electrically connected to, it is configured to produce a total Status Flag；
Wherein, the control unit reads the value of statistical indicant of total Status Flag after storage arrangement power supply, and works as total state
Mark indicate the non-volatile memory device do not complete it is complete erase running when, the control unit individually reads the shape
State register does not complete the data block of complete running of erasing to find out.
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| CN201310521695.3A CN104575605B (en) | 2013-10-29 | 2013-10-29 | Storage arrangement and the method booted up using nonvolatile memory to system |
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| CN106710627B (en) * | 2015-11-18 | 2019-11-26 | 凌阳科技股份有限公司 | Polycrystalline born of the same parents chip and its memory device |
| KR102637160B1 (en) * | 2016-04-14 | 2024-02-19 | 삼성전자주식회사 | Storage device including nonvolatile memory device and operating method of storage device |
| CN110970076B (en) * | 2019-12-02 | 2022-03-18 | 武汉新芯集成电路制造有限公司 | Memory structure and erasing method thereof |
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| CN101154447A (en) * | 2006-09-28 | 2008-04-02 | 北京握奇数据系统有限公司 | Flash memory and its control method |
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| US7023734B2 (en) * | 2004-03-03 | 2006-04-04 | Elite Semiconductor Memory Technology, Inc. | Overerase correction in flash EEPROM memory |
| US8208337B2 (en) * | 2009-12-21 | 2012-06-26 | Macronix International Co., Ltd. | Operation method and leakage controller for a memory and a memory applying the same |
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| CN101154447A (en) * | 2006-09-28 | 2008-04-02 | 北京握奇数据系统有限公司 | Flash memory and its control method |
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