TWI521708B - A transistor device with portions of its strained layer disposed in its insulating recesses - Google Patents

Description

Transistor device with strained layer implanted insulating trench

The present invention relates to an electro-optical device.

In recent years, under the continuous shrinkage of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the performance of the transistor itself can be effectively improved, but the oxide layer is also encountered. Problems such as thinner thickness and shorter leakage current caused by the channel. However, the amount of equipment required for each component's miniaturization is quite large, so many companies and experts and scholars are looking for other ways to increase component performance from time to time.

The operating time of the circuit of the transistor can be expressed by the formula (1): Where τ is the reaction time of the circuit, C is the sum of the capacitance of the transistor and the output, V is the operating voltage of the transistor, and I is the driving current of the transistor. Therefore, if the reaction time of the transistor is to be lowered to increase the operating frequency, it is one of the effective methods to increase the current of the transistor.

To increase the current of the transistor, you can understand it by the current saturation formula (2): Where μ _eff is the carrier mobility of the transistor, C _OX is the gate capacitance of the transistor, V _g is the gate voltage, V _t is the threshold voltage, m is the substrate effect coefficient, and L is the channel length of the transistor, W It is the width of the transistor. Therefore, if you want to increase the saturation current, increasing C _OX , W , μ _{eff ,} or shortening L is a way to increase the component current. However, increasing the width W of the transistor increases the area of the transistor and conflicts with the purpose of miniaturization. To reduce the channel length L , the problem of short channel effects needs to be overcome. Increasing the gate capacitance C _OX requires the combination of other gate materials and process technology, which is inconvenient. Therefore, how to design the structure of the transistor to increase the carrier mobility μ _eff and increase the operating frequency is one of the goals of the industry and the academic community.

One aspect of the present invention provides an optoelectronic device comprising at least one transistor and a strained layer. The transistor includes a substrate, a gate dielectric layer, and a gate. The substrate has two insulating trenches, and the substrate includes a doped well region, a source, a drain, and a channel. The source and the drain are respectively located on the doped well region and are disposed separately. The source and the drain are both located between the two insulating trenches, one of the two insulating trenches is adjacent to the source, and the other of the two insulating trenches is adjacent to the drain. The channel is placed between the source and the drain. A gate dielectric layer is placed over the substrate and covers at least the via. The gate is placed on the gate dielectric layer and placed over the channel. Characterized in that the strain layer covers at least the gate of the transistor, the source of the portion, and Part of the bungee, and at least partially placed in the two insulating trenches.

In one or more embodiments, the strained layer is a Contact Etching Stop layer (CESL).

In one or more embodiments, the transistor is an N-type (also N-channel) transistor and the strained layer is a tensile strained layer.

In one or more embodiments, the transistor is a P-type (also P-channel) transistor and the strained layer is a compressive strain layer.

In one or more embodiments, the transistor device further includes at least one insulating portion disposed in one of the insulating grooves and placed under the strained layer.

In one or more embodiments, the number of transistors is two and is a P-type (channel) transistor and an N-type (channel) transistor, respectively. A P-type (channel) transistor is placed adjacent to the N-type (channel) transistor. The strained layer comprises a compressive strained layer and a tensile strained layer. The compressive strain layer covers at least a portion of the P-type (channel) transistor. The tensile strained layer covers at least a portion of the N-type (channel) transistor.

In one or more embodiments, one of the two insulating trenches of the P-type (channel) transistor forms an intermediate insulating trench together with one of the two insulating trenches of the N-type (channel) transistor, and P The other one of the two types of insulating trenches of the type (channel) transistor, and the other two of the insulating trenches of the N-type (channel) transistor are edge insulating trenches. Part of the compressive strain layer is respectively placed in the intermediate insulating trench and the edge insulating trench of the P-type (channel) transistor, and part of the tensile strain layer is placed in the edge insulating trench of the N-type (channel) transistor.

In one or more embodiments, a portion of the tensile strained layer is respectively disposed in an intermediate insulating trench and an edge insulating trench of the N-type (channel) transistor, and A portion of the compressive strain layer is placed in the edge insulating trench of the P-type (channel) transistor.

In one or more embodiments, a portion of the compressive strain layer is respectively disposed at an edge insulating trench of the intermediate insulating trench and the P-type (channel) transistor, and a portion of the tensile strain layer is respectively disposed in the intermediate insulating trench The trench is insulated from the edge of the N-type (channel) transistor.

In one or more embodiments, the number of transistors is plural and is a P-type (channel) transistor and an N-type (channel) transistor, respectively. A P-type (channel) transistor is alternately arranged with an N-type (channel) transistor. The strained layer comprises a plurality of compressive strain layers and a plurality of tensile strain layers. The compressive strain layer covers at least a portion of the P-type (channel) transistor, respectively. The tensile strained layer covers at least a portion of the N-type (channel) transistor, respectively.

The strain layer described above can be deformed due to the relationship between its own material and the process. By deforming the strained layer as a whole, a portion of the strained layer placed in the two insulating trenches can apply a positive stress to the transistor, thereby changing the stress of the channel to increase its carrier mobility.

100‧‧‧Optoelectronics

100p‧‧‧P type (channel) transistor

100n‧‧‧N type (channel) transistor

102‧‧‧Substrate

110‧‧‧Base

112‧‧‧Intermediate insulation trench

114, 116, 114n, 114p, 116n, 116p, 118, 119n, 119p‧‧‧ insulated trenches

122‧‧‧Doped well area

124‧‧‧ source

126‧‧‧汲polar

128, 128n, 128p‧‧‧ channels

134‧‧‧Source extension

136‧‧‧Bungee Extension

140‧‧‧ gate dielectric layer

150‧‧‧ gate

160, 170‧‧‧ barrier

160, 170‧‧ ‧ etch stop layer

180, 190‧‧ ‧ spacer

200‧‧‧ strain layer

210‧‧‧Compressed strain layer

220‧‧‧ tensile strain layer

310, 340‧‧‧ sacrificial oxide layer

320‧‧‧ nitride layer

330‧‧‧Undoped glass layer

332, 334‧‧‧ undoped glass

350‧‧‧ patterned photoresist layer

Fig. 1 is a cross-sectional view showing a crystal device according to a first embodiment of the present invention.

2A to 2K are flow charts showing a process section of the transistor device of Fig. 1.

Fig. 3 is a cross-sectional view showing a transistor device according to a second embodiment of the present invention.

4 is a cross-sectional view showing a transistor device according to a third embodiment of the present invention. Figure.

Fig. 5 is a cross-sectional view showing a transistor device according to a fourth embodiment of the present invention.

Fig. 6 is a cross-sectional view showing a transistor device according to a fifth embodiment of the present invention.

Fig. 7 is a cross-sectional view showing a crystal device according to a sixth embodiment of the present invention.

The various embodiments of the present invention are disclosed in the following drawings, and many of the However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

Fig. 1 is a cross-sectional view showing a crystal device according to a first embodiment of the present invention. The transistor device includes at least one transistor 100 and a strained layer 200. The transistor 100 includes a substrate 110, a gate dielectric layer 140, and a gate 150. The substrate 110 has two insulating trenches 114 and 116, and the substrate 110 includes a doped well region 122, a source 124, a drain 126, and a channel 128. Source 124 and drain 126 are respectively located on doped well region 122 and are disposed separately. Source 124 and drain 126 are both located between insulating trenches 114 and 116. The insulating trench 114 is disposed adjacent to the source 124, and the insulating trench 116 is disposed adjacent to the drain 126. Channel 128 is placed between source 124 and drain 126 between. A gate dielectric layer 140 is placed over the substrate 110 and at least covers the channel 128. Gate 150 is placed over gate dielectric layer 140 and placed over channel 128. The strained layer 200 covers at least the gate 150 of the transistor 100, a portion of the source 124 and a portion of the drain 126, and is at least partially disposed in the insulating trenches 114 and 116. For example, in FIG. 1, a portion of the strained layer 200 fills the insulating trenches 114 and 116.

In the present embodiment, the strain layer 200 can be deformed due to the relationship between its own material and the process technology. By straining the strained layer 200 as a whole, the partial strain layers 200 placed in the insulating trenches 114 and 116 can respectively apply positive stress to the transistor 100 (ie, from the source 124 and the drain 126 to the outside of the transistor, respectively). 100 applies force), thereby changing the stress of the channel 128 to increase its carrier mobility. Since the portion of the strained layer 200 disposed in the insulating trenches 114 and 116 is mainly subjected to the forward stress of the transistor 100, the channel 128 can effectively sense the stress applied by the strained layer 200 regardless of whether it is a long channel or a short channel. Although in practical applications, an external conductive plug can pass through the strained layer 200 and is electrically connected to the source 124 and the drain 126, respectively (not shown), even if it is in contact with the external conductive plug. The portion of the strained layer 200 may be deformed irregularly, and the portion of the strained layer 200 placed in the insulating trenches 114 and 116 is not greatly affected, so that the carrier mobility of the transistor 100 can also be greatly increased.

In the present embodiment, the strained layer 200 may be a contact etch stop layer (CESL). For example, the material of the contact etch stop layer may be tantalum nitride (SiN _x ). By controlling the ratio between the nitrogen and the ruthenium and the process conditions, the contact etch stop layer may have tensile deformation ability or compressive deformation ability to match the stress required for the transistor 100 itself. It should be noted, however, that the material of the contact etch stop layer is merely illustrative and is not intended to limit the invention. In the technical field of the present invention, the material of the contact etch stop layer should be elastically selected according to actual needs.

In an embodiment, the transistor 100 can be an N-type (channel) transistor and the strained layer 200 is a tensile strained layer. The N-type (channel) transistor refers to a semiconductor in which the source 124 and the drain 126 are both N-type doped. As shown in FIG. 1, in this case, a portion of the tensile strain layer placed in the insulating trenches 114 and 116 can apply a tensile forward stress to the transistor 100 such that the source 124 and the drain 126 are respectively The direction of the insulating trenches 114 and 116 is deformed, thereby causing the channel 128 to undergo tensile deformation to increase its electron mobility.

In other embodiments, the transistor 100 can be a P-type (channel) transistor and the strained layer 200 is a compressive strain layer. The P-type (channel) transistor refers to a transistor in which the source 124 and the drain 126 are both P-type doped. In this case, a portion of the compressive strain layer disposed in the insulating trenches 114 and 116 can apply a compressive forward stress to the transistor 100 such that the source 124 and the drain 126 are respectively deformed in the direction of the channel 128, thereby The channel 128 is caused to undergo compression deformation to increase its hole mobility.

In the present embodiment, the transistor 100 may further include two barrier layers 160 and 170 respectively disposed in the insulating trenches 114 and 116 and disposed between the strained layer 200 and the substrate 110, respectively. In detail, after the process of insulating trenches 114 and 116 is completed, a portion of the substrate 110 is exposed. In order to protect the substrate 110 from contamination by intrusion of impurities in subsequent processes, barrier layers 160 and 170 may be applied to the edges of the insulating trenches 114 and 116, Thereby the substrate 110 is protected. In addition, in the present embodiment, the transistor 100 may further include etch stop layers 165 and 175 disposed in the insulating trenches 114 and 116, respectively, and placed between the strained layer 200 and the barrier layers 160 and 170, respectively.

In this embodiment, the transistor 100 may further include two spacers 180 and 190 respectively disposed on opposite sides of the gate 150. The substrate 110 can further include a source extension 134 and a drain extension 136. The source extension 134 is disposed between the source 124 and the channel 128, and the source extension 134 is disposed below the spacer 180 and the gate dielectric layer 140. The drain extension 136 is disposed between the drain 126 and the channel 128, and the drain extension 136 is disposed below the spacer 190 and the gate dielectric layer 140. In the present embodiment, the source extension 134 and the drain extension 136 can be formed using a Lightly Doped Drain (LDD) layout technique, which can reduce or avoid the hot carrier. Too large to deteriorate the gate dielectric layer 140.

The above contents are all for the structure of the transistor device, and the method of manufacturing the transistor device will be further described next. It should be noted, however, that the process methods described below are merely illustrative and are not intended to limit the invention, and are focused on demonstrating how the strain layer 200 covers at least the gate 150 of the transistor 100, the portion of the source 124, and portions thereof. The drain 126 is at least partially disposed in the two insulating trenches 114, 116, the remainder of which are conventional processes. Referring to FIGS. 2A-2K, a flow chart of a process section of the transistor device of FIG. 1 is shown.

Please refer to Figure 2A first. The manufacturer may first provide a substrate 102 of a material such as ruthenium. The manufacturer can then form a crucible on the substrate 102 in sequence. The oxide layer 310 and the nitride layer 320 are formed. The method for forming the sacrificial oxide layer 310 and the nitride layer 320 is, for example, a low pressure chemical vapor deposition method. The material of the nitride layer 320 may be tantalum nitride.

Please refer to Figure 2B. The manufacturer can then form insulating trenches 114 and 116 in substrate 102. For example, the manufacturer can sequentially pattern the nitride layer 320 and the dielectric layer 310 (as shown in FIG. 2A) to expose the two portions of the substrate 102. Substrate 102 is then etched to form insulating trenches 114 and 116, respectively. In order to prevent the exposed portion of the substrate 102 from being contaminated in the subsequent process, the barrier layers 160 and 170 may be separately formed in the insulating trenches 114 and 116, wherein the barrier layers 160 and 170 may be made of an oxide. . The insulating trenches 114 and 116 are structures in which the transistors are insulated from each other.

Please refer to Figure 2C. At this time, the manufacturer may form an etch stop layer 165 and 175 respectively in the insulating trenches 114 and 116, wherein the material of the etch stop layers 165 and 175 may be tantalum nitride. The manufacturer can then form an Undoped Silicate Glass (USG) layer 330 on the substrate 102 to form Shallow Trench Isolation (STI). The undoped bismuth glass layer 330 fills at least the insulating trenches 114 and 116.

Please refer to the 2D figure. At this point, the manufacturer can remove portions of the undoped bismuth glass layer 330, the nitride layer 320, and the sacrificial oxide layer 310 (as shown in FIG. 2C) to expose the underlying substrate 102 and in the insulating structure. Undoped glass portions 332 and 334 are formed in the grooves 114 and 116, respectively. In this step, a portion of the barrier layers 160, 170 and a portion of the etch stop layer 165, 175 was also removed.

Please refer to Figure 2E. The manufacturer can then form a substrate 110 comprising a doped well region 122. For example, the manufacturer may first form another embedding oxide layer 340 that covers the substrate 102 (as shown in FIG. 2D), undoped glass portions 332 and 334. The substrate 102 can be doped and implanted. For a P-type (channel) transistor, the doped well region 122 should be an N-well (N-well), and for an N-type (channel) transistor. For example, the doped well region 122 should be a P-well. In addition, for N-type wells, doping implantation may be performed first using phosphorus (P) ions, followed by annealing to increase the doping depth of the doped well region 122. For P-type wells, boron (B) ions can be used for doping and then annealed.

Please refer to Figure 2F. The manufacturer may form the channel 128 in the doped well region 122, for example, a doping implant process may be performed on the upper portion of the doped well region 122, and for the P-doped channel 128, boron (B) ions may be used. Doping is implanted, and for N-doped channels 128, phosphorus (P) ions can be used for doping. It should be noted, however, that the material doped in this step may be the same or different from the material doped by the doped well region 122, but at a different concentration than the material doped by the doped well region 122 to control the electricity. The critical voltage of the crystal. In practice, the doping well region 122 and the channel 128 can be doped twice or more, and the invention is not limited thereto.

Please refer to the 2G chart. The manufacturer can form the gate dielectric layer 140 and the gate 150 sequentially on the substrate 110. For example, first, the manufacturer may first remove the oxide layer 340 (as shown in FIG. 2F), and then sequentially form a gate dielectric layer 140, a polysilicon layer, and a photoresist layer on the substrate 110. The manufacturer can then sequentially pattern the photoresist layer and the polysilicon layer to pattern the polysilicon layer into the gate 150. The method for forming the gate dielectric layer 140 and the polysilicon layer may be, for example, a low pressure chemical vapor deposition method, and the method for forming the photoresist layer may be, for example, a spin coating method, and the patterning method is, for example, a photolithography method.

Please refer to Figure 2H. The manufacturer can then form a source extension 134 and a drain extension 136 in the substrate 110. For example, the manufacturer may first form the patterned photoresist layer 350 to conceal the undoped glass portions 332 and 334 and expose the gate dielectric layer 140 and the gate 150. The manufacturer can then use the gate 150 as a mask to dope the substrate 110 with a low doped drain (LDD) layout technique. For P-type (channel) transistors, boron difluoride (BF ₂ ⁺ ) ions can be used for doping values, while for N-type (channel) transistors, arsenic (As) ions can be used. Doped fabric value.

Please refer to Figure 2I. The manufacturer can then form source 124 and drain 126. For example, the manufacturer may form spacers 180 and 190 on opposite sides of the gate 150, and then doping the substrate 110 with the gate 150 and the spacers 180 and 190 as masks. Compared with the above-mentioned low-doped bungee cloth value technology, this step is performed by a heavily doping technique, and the current supplied by the doping process is lower than that of the doped bungee plate value technique. For the P-type (channel) doped source 124 and the drain 126, boron (B) ions may be used for doping, and for the N-type (channel) doped source 124 and the drain 126, Doping can be performed using phosphorus (P) ions. Then, a portion of the gate dielectric layer 140 is removed, and a metallization process (not shown) of the source 124, the drain 126, and the gate 150 is performed.

Please refer to the 2J picture. The manufacturer can now place the photoresist layer 350 (eg It is removed in Figure 2I) and then completely overlaid with another layer of photoresist. Using the steps of FIG. 2B, the insulating trenches 114 and 116 are etched back to the etch stop layers 165 and 175. After removing the photoresist layer, a cross-sectional view of FIG. 2J can be obtained.

Please refer to Figure 2K. Then, the manufacturer can form a strained layer 200 over the substrate 110, a portion of the strained layer 200 fills the insulating trenches 114 and 116, and another portion of the strained layer 200 covers the gate 150, a portion of the source 124, and a portion thereof. The drain 126 is separated from the spacers 180 and 190. In this way, the process of the transistor device is completed. The wiring process at the back end of the integrated circuit (IC) can be the same as in the prior art.

In other embodiments, in order to facilitate the process, after completing the step of FIG. 2B, the manufacturer may omit the steps of fabricating the undoped germanium glass portions 332 and 334, thus eliminating the need to form the etch stop layers 165 and 175. However, the invention is not limited thereto.

Next, please refer to FIG. 3, which is a cross-sectional view showing a transistor device according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in the presence of undoped bismuth glass portions 332 and 334. In the present embodiment, the transistor device further includes at least one insulating portion disposed in one of the insulating trenches 114 and 116 and placed under the strained layer 200. For example, in FIG. 3 , the insulating portions may be undoped glass portions 332 and 334 respectively disposed in the insulating trenches 114 and 116 and placed under the strain layer 200, respectively. In the present embodiment, since the strained layers 200 are also placed in the insulating trenches 114 and 116, respectively, the strained layer 200 can also increase the carrier mobility of the channel layer 128 by deformation. As for the other details of the embodiment, as compared with the first embodiment The same, therefore will not repeat them.

Next, please refer to FIG. 4, which is a cross-sectional view showing a transistor device according to a third embodiment of the present invention. The third embodiment differs from the first embodiment in the number of transistors. In the present embodiment, the number of transistors is two, and is a P-type (channel) transistor 100p and an N-type (channel) transistor 100n, respectively. The P-type (channel) transistor 100p is disposed adjacent to the N-type (channel) transistor 100n, for example, a complementary metal-oxide-semiconductor (CMOS) can be formed. The strained layer 200 includes a compressive strain layer 210 and a tensile strained layer 220. The compressive strain layer 210 covers at least a portion of the P-type (channel) transistor 100p. The tensile strained layer 220 covers at least a portion of the N-type transistor 100n. In other words, the compressive strain layer 210 can be used to cause the channel 128p of the P-type (channel) transistor 100p to undergo compression deformation to increase its hole mobility; and the tensile strain layer 220 can be used to make the channel of the N-type transistor 100n. 128n produces tensile deformation to increase its electron mobility.

In detail, the insulating trench 116p of the P-type (channel) transistor 100p and the insulating trench 114n of the N-type transistor 100n together form the intermediate insulating trench 112, and the insulating trench 114p of the P-type (channel) transistor 100p The insulating trenches 116n of the N-type transistor 100n are both edge insulating trenches. A portion of the compressive strain layer 210 is placed and filled with the edge insulating trenches of the intermediate insulating trenches 112 and the P-type (channel) transistors 100p, and a portion of the tensile strained layer 220 is placed and filled with N-type electricity. The edge of the crystal 100n is insulated. It should be noted that, in the present embodiment, the transistor device is described by a P-type (channel) transistor 100p and an N-type (channel) transistor 100n. The insulating trenches 114p and 116n are both edge insulating trenches. However, in other embodiments, if the transistor device includes three or more transistors adjacent to each other, the insulating trenches 114p and 116n may also merge with other insulating trenches to form intermediate insulating trenches 112, respectively, depending on the actual structure. And set.

As shown in FIG. 4, for the P-type (channel) transistor 100p, a portion of the compressive strain layer 210 in the intermediate insulating trench 112 is subjected to a forward stress of the P-type (channel) transistor 100p to the left, At the same time, part of the compressive strain layer 210 in the edge insulating trench of the P-type (channel) transistor 100p is applied with a rightward positive stress of the P-type (channel) transistor 100p, so that the P-type (channel) transistor 100p is channeled. 128p produces compression deformation. On the other hand, for the N-type (channel) transistor 100n, a portion of the compressive strain layer 210 in the intermediate insulating trench 112 is subjected to a positive stress toward the left of the N-type (channel) transistor 100n, while at the same time A portion of the tensile strain layer 220 in the edge insulating trench of the type (channel) transistor 100n is applied with a rightward positive stress of the N-type (channel) transistor 100n, so that the channel 128n of the N-type (channel) transistor 100n is generated. Stretch deformation. Therefore, the structure of the strain layer 200 of the present embodiment can simultaneously achieve the purpose of increasing the carrier mobility of the channel layers 128p and 128n. Other details of the present embodiment are the same as those of the first embodiment, and thus will not be described again.

Next, please refer to FIG. 5, which is a cross-sectional view showing a transistor device according to a fourth embodiment of the present invention. The fourth embodiment differs from the third embodiment in the distribution of the strained layer 200. In the present embodiment, a portion of the tensile strain layer 220 is placed and filled with the edge insulating trenches of the intermediate insulating trenches 112 and the N-type (channel) transistors 100n, and a portion of the compressive strain layer 210 is placed. And filling the edge insulating trench of the P-type (channel) transistor 100p. In other words In the present embodiment, the tensile strain layer 220 is present in the intermediate insulating trench 112. However, due to the stress distribution exhibited by the tensile strain layer 220 as a whole, the portion of the tensile strain layer 220 located in the intermediate insulating trench 112 is also subjected to the leftward positive stress, so that the same as the third embodiment can be achieved. effect. Other details of the present embodiment are the same as those of the third embodiment, and thus will not be described again.

Next, please refer to FIG. 6, which is a cross-sectional view showing a transistor device according to a fifth embodiment of the present invention. The fifth embodiment differs from the third embodiment in the distribution of the strained layer 200. In this embodiment, a portion of the compressive strain layer 210 is respectively disposed on the edge insulating trenches of the intermediate insulating trench 112 and the P-type (channel) transistor 100p, and a portion of the tensile strain layer 220 is respectively placed in the intermediate insulating layer. The trench 112 is insulated from the edge of the N-type (channel) transistor 100n. In other words, in the present embodiment, the compressive strain layer 210 and the tensile strain layer 220 are simultaneously present in the intermediate insulating trench 112. Due to the stress distribution exhibited by the compressive strain layer 210 as a whole, a portion of the compressive strain layer 210 located in the intermediate insulating trench 112 is subjected to a forward stress of the P-type (channel) transistor 100p to the left, and the tensile strain layer 220 is applied. The stress distribution exhibited as a whole causes the tensile strain layer 220 located in the intermediate insulating trench 112 to also apply the forward stress of the N-type (channel) transistor 100n to the left, so that the same as the third embodiment can still be achieved. Effect. Other details of the present embodiment are the same as those of the third embodiment, and thus will not be described again.

Next, please refer to FIG. 7, which is a cross-sectional view showing a transistor device according to a sixth embodiment of the present invention. The sixth embodiment differs from the first embodiment in the number of transistors. In the present embodiment, the number of transistors There are a plurality of P-type (channel) transistor 100p and N-type (channel) transistor 100n, respectively. The P-type (channel) transistor 100p is alternately arranged with the N-type (channel) transistor 100n, for example, a complementary metal oxide semiconductor can be formed. The strained layer 200 includes a plurality of compressive strain layers 210 and a plurality of tensile strain layers 220. The compressive strain layer 210 covers at least a portion of the P-type (channel) transistor 100p, respectively. The tensile strained layer 220 covers at least a portion of the N-type (channel) transistor 100n, respectively. In detail, the insulating trenches 118 of the two adjacent P-type (channel) transistors 100p and the insulating trenches 118 of the N-type (channel) transistor 100n together form the intermediate insulating trenches 112, and the P-type (channel) The insulating trenches 119p of the transistor 100p and the insulating trenches 119n of the N-type (channel) transistor 100n are edge insulating trenches. A portion of the compressive strain layer 210 is disposed in the insulating trench 119p, and may be further disposed in at least a portion of the intermediate insulating trench 112, and another portion of the tensile strained layer 220 is disposed in the insulating trench 119n, and may be further disposed In at least a portion of the intermediate insulating trenches 112. In fact, the distribution of the strain layer 200 of each of the intermediate insulating trenches 112 can be the same as that of FIG. 4, FIG. 5 or FIG. 6, and the design is not limited thereto. Other details of the present embodiment are the same as those of the first embodiment, and thus will not be described again.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Optoelectronics

110‧‧‧Base

114, 116‧‧‧Insulation trench

122‧‧‧Doped well area

124‧‧‧ source

126‧‧‧汲polar

128‧‧‧ channel

134‧‧‧Source extension

136‧‧‧Bungee Extension

140‧‧‧ gate dielectric layer

150‧‧‧ gate

160, 170‧‧‧ barrier

165, 175‧‧ ‧ etch stop layer

180, 190‧‧ ‧ spacer

200‧‧‧ strain layer

Claims (10)

A transistor device comprising: at least one transistor, comprising: a substrate having two insulating trenches, the substrate comprising: a doped well region; a source and a drain, respectively located on the doped well region, And separately disposed, wherein the source and the drain are located between the two insulating trenches, one of the two insulating trenches is disposed adjacent to the source, and the other of the two insulating trenches is adjacent to the drain And a channel disposed between the source and the drain; a gate dielectric layer disposed on the substrate and covering at least the channel; and a gate disposed on the gate dielectric layer And being disposed above the channel; and a strained layer, the strain layer covering at least the gate of the transistor, the source and the portion of the drain of the portion, and at least partially disposed on the second In the insulating trench. The transistor device of claim 1, wherein the strained layer is a contact etch stop layer. The transistor device of claim 1, wherein the transistor is an N-type transistor, and the strained layer is a tensile strain layer. The transistor device of claim 1, wherein the transistor is a P-type transistor, and the strained layer is a compressive strain layer. The transistor device of claim 1, further comprising: at least one insulating portion disposed in one of the insulating trenches and disposed under the strained layer. The transistor device of claim 1, wherein the number of the transistors is two, and is respectively a P-type transistor and an N-type transistor, the P-type transistor being disposed adjacent to the N-type transistor; And wherein the strained layer comprises: a compressive strain layer covering at least a portion of the P-type transistor; and a tensile strain layer covering at least a portion of the N-type transistor. The transistor device of claim 6, wherein one of the two insulating trenches of the P-type transistor forms an intermediate insulating trench together with one of the two insulating trenches of the N-type transistor. And the other of the two insulating trenches of the P-type transistor, and the other two insulating trenches of the N-type transistor are an edge insulating trench; and a part of the compressive strain layers are respectively disposed The intermediate insulating trench and the edge of the P-type transistor are insulated from the trench, and part of the tensile strain layer The edge insulating trench is placed in the N-type transistor. The transistor device of claim 6, wherein one of the two insulating trenches of the P-type transistor forms an intermediate insulating trench together with one of the two insulating trenches of the N-type transistor. And the other of the two insulating trenches of the P-type transistor and the two insulating trenches of the N-type transistor are an edge insulating trench; and a part of the tensile strain layer is respectively The intermediate insulating trench is disposed in the edge insulating trench of the N-type transistor, and a portion of the compressive strain layer is disposed in the edge insulating trench of the P-type transistor. The transistor device of claim 6, wherein one of the two insulating trenches of the P-type transistor forms an intermediate insulating trench together with one of the two insulating trenches of the N-type transistor. And the other of the two insulating trenches of the P-type transistor, and the other two insulating trenches of the N-type transistor are an edge insulating trench; and a part of the compressive strain layers are respectively disposed The intermediate insulating trench and the edge insulating trench of the P-type transistor, and a portion of the tensile strained layer are respectively disposed in the intermediate insulating trench and the edge insulating trench of the N-type transistor. The transistor device of claim 1, wherein the number of the transistors is plural, and respectively, a plurality of P-type transistors and a plurality of N-type transistors, and the P-type transistors and the N-type transistors Crystals are alternately set; And the strain layer comprises: a plurality of compressive strain layers covering at least a portion of the P-type transistors; and a plurality of tensile strain layers covering at least a portion of the N-type transistors .