TWI521611B - Method for fabricating mos device - Google Patents

Description

Method for manufacturing MOS semiconductor device

The present invention relates to a method of fabricating a MOS device.

Gold oxide semi-transistors are a basic structure widely used in various semiconductor elements such as memory elements, image sensors, or displays.

Conventional gold oxide half field effect transistors are limited by the manufacturing process and are difficult to develop to smaller sizes, thus developing multiple gate MOS transistors. Double gate MOS transistors have better characteristics. The FinFET device is a double-gate MOS transistor. It has a three-sided three-dimensional gate structure design, which can enhance the control of the gate to the channel and suppress the channel breakdown effect. Leakage current, so the traditional MOSFET of the same size has better gate control capability.

However, in the current FinFET process, the implantation angle of the ion implantation process for forming the source/drain extension and the pocket-type doping region is considerably limited, and the process margin is very small. Moreover, the formed source/drain extension region and the pocket-type doped region have a problem of uneven doping concentration and depth distribution, and even electric leakage.

The present invention provides a method of fabricating a gold oxide semiconductor device which can form a source and drain extension region and a pocket type doped region having a uniform doping concentration and a uniform depth.

The present invention provides a method of fabricating a MOS device that can enhance the process margin of ion implantation.

The present invention provides a method of fabricating a MOS device, comprising forming a first hard mask material layer on a substrate, then patterning the first hard mask material layer and removing a portion of the substrate to form a fin surrounded by a trench And a first hard mask layer, wherein the fins extend in a first direction. Thereafter, an insulating layer is formed on the bottom of the trench, and a gate conductor layer is formed on the insulating layer of the trench, and the gate conductor layer extends in the second direction. Thereafter, the first ion implantation process is performed by using the first hard mask as a mask, and the first source and the drain extension are formed on the sidewall of the fin. Then, remove the first hard mask layer and expose the top of the fin. Thereafter, a second ion implantation process is performed to form a second source and drain extension on the top of the fin.

The method may further include: performing a first pocket type ion implantation process after the first ion implantation process to form a first pocket type doped region on the sidewall of the fin, and performing after the second ion implantation process A second pocket type ion implantation process forms a second pocket-type doped region on top of the fin.

According to an embodiment of the invention, the method for forming the gate conductor comprises forming a conductor material layer on the insulating layer of the trench, and then using the first hard mask layer as a stop layer to planarize the conductor material layer, and then, on the conductor A second hard mask material layer is formed on the material layer, and then the second hard mask material layer and the conductor material layer are patterned to form a second hard mask layer and the gate conductor layer.

According to an embodiment of the invention, the method for forming the gate conductor layer comprises forming a layer of a conductor material on the insulating layer of the trench, and then planarizing the layer of the conductor material, leaving a surface of the conductor material layer higher than the first hard The surface of the mask layer. Thereafter, the conductor material layer is patterned to form the above-described gate conductor layer.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming a first spacer around the gate conductor layer before performing the first ion implantation process.

According to an embodiment of the invention, the method for forming the insulating layer includes forming a layer of insulating material on the substrate, and then planarizing the layer of insulating material with the first hard mask layer as a stop layer, and then removing portions of the trench A layer of insulating material to form the above insulating layer.

According to an embodiment of the invention, in the method for fabricating the MOS device, the ion implantation angle of the first ion implantation process is 30°-60°.

According to an embodiment of the invention, the ion implantation angle of the second ion implantation process is 90°.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming a second spacer on a sidewall of the gate conductor layer, and then removing a portion of the fin to be on both sides of the gate conductor layer. A recess is formed, and a semiconductor compound is formed in each recess, and then a source and a drain region are formed in each semiconductor compound.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming an etch stop layer on the substrate and forming a dielectric layer on the etch stop layer.

According to an embodiment of the invention, the method for fabricating the MOS device further includes removing a portion of the dielectric layer and the etch stop layer to expose the gate conductor layer, and then removing the gate conductor layer to form an opening. Then, a gate metal layer is formed in the opening.

According to an embodiment of the invention, the method for fabricating the MOS device further includes forming a successful function metal layer in the opening before forming the gate metal layer in the opening.

According to an embodiment of the invention, the method of fabricating the MOS device further includes forming a first thyristor layer on the fin before forming the gate conductor layer.

According to an embodiment of the invention, the first gate dielectric layer has a dielectric constant of less than 4.

According to an embodiment of the invention, the method for fabricating the MOS device further includes: removing the first thyristor layer having a dielectric constant lower than 4 after removing the gate conductor layer, and removing the first After the gate dielectric layer, a second gate dielectric layer having a dielectric constant higher than 4 is formed.

Based on the above, the MOS device of the embodiment of the present invention can form a source and drain extension region and a pocket type doping region having a uniform doping concentration and a uniform depth.

The manufacturing method of the MOS device of the embodiment of the invention can improve the process margin of ion implantation.

The above described features and advantages of the present invention will be more apparent from the following description.

1 to 7 are side views of a method of fabricating a MOS device in a first direction, in accordance with an embodiment of the invention. 8 to FIG. 11 are schematic cross-sectional views showing a process of manufacturing the MOS device of FIG. 7 in a second direction. 5A to 7A are perspective views of Figs. 5 to 7.

Referring to FIG. 1, a hard mask material layer 12 is formed on the substrate 10. The substrate 10 material includes a semiconductor such as germanium. The hard mask material layer 12 may be a single material layer or a material layer of two or more layers. In one embodiment, the hard mask material layer 12 is composed, for example, of a yttrium oxide (SiO ₂ ) layer and a tantalum nitride layer (from bottom to top). The method of forming the ruthenium oxide layer and the tantalum nitride layer is, for example, a chemical vapor deposition method. The thickness of the ruthenium oxide layer is, for example, 20 angstroms to 200 angstroms. The thickness of the tantalum nitride layer is, for example, 500 angstroms to 3,000 angstroms.

Next, referring to FIG. 2, the hard mask material layer 12 is patterned by a lithography and etching process and a portion of the substrate 10 is removed to form the fins 14 and the hard mask layer 12a. The fins 14 extend in a first direction and are surrounded by a trench 16 . A layer 18 of insulating material is then formed on the substrate 10. The material of the insulating material layer 18 is, for example, cerium oxide, and the forming method is, for example, chemical vapor deposition.

Thereafter, referring to FIG. 3, a planarization process is first performed with the hard mask layer 12a as a stop layer to remove the insulating material layer 18 over the hard mask layer 12a. The planarization process is, for example, a chemical mechanical polishing process. Thereafter, a portion of the insulating material layer 18 in the trench 16 is removed, leaving the insulating material layer of the trench bottom 16 as the insulating layer 18a of the isolation structure. Thereafter, a conductor material layer 20 is formed on the insulating layer 18a in the trench 16. The material of the conductor material layer 20 is, for example, a single crystal germanium, an undoped polysilicon, a doped polysilicon, an amorphous germanium, a germanium material or a combination thereof, and the formed method is, for example, a chemical vapor deposition method, and the thickness is, for example, 500 Å to 2000. Ai.

Thereafter, referring to FIG. 4, the conductor layer 20 is planarized with the hard mask layer 12a as a stop layer. The planarization process is, for example, a chemical mechanical polishing process. Then, a hard mask material layer 22 is formed on the conductor material layer 20. The hard mask material layer 22 can be a single material layer or a two or more material layer. In an embodiment, the hard mask material layer 12 is, for example, an oxide (such as hafnium oxide) layer or a nitride (such as tantalum nitride) layer or a carbide (such as tantalum carbide) layer or a carbonitride (tantalum carbonitride). The layer or any combination thereof is formed, for example, by chemical vapor deposition, and has a thickness of, for example, 50 angstroms to 1000 angstroms.

Thereafter, referring to FIG. 5 and FIG. 5A, the hard mask material layer 22 and the conductor material layer 20 are patterned by a lithography and etching process to form the hard mask layer 22a and the gate conductor layer 20a. The gate conductor layer 20a extends in a second direction substantially perpendicular to the aforementioned first direction to sandwich the fins 14. That is, the fin 14 is located between the two portions of the gate conductor layer 20a.

Then, referring to FIGS. 6 and 6A, the first ion implantation process 24 is performed with the first hard mask 12a as a mask, and the first source and drain extension regions 26 are formed on the sidewalls of the fin 14. Another ion implantation process is then performed to form a first pocket-type doped region 27 (see Figures 8-11). The ion implantation angle θ _{1 of the} first ion implantation process 24 is greater than 30°, for example, 30° to 60°.

Thereafter, referring to Figures 7 and 7A, the hard mask layer 12a is removed to expose the top of the fin 12. The method of removing the hard mask layer 12a may employ an etching process such as a dry etching process or a wet etching process. In one embodiment, removing the hard mask layer 12a includes a tantalum oxide layer and a tantalum nitride layer. When performing the removing step, the tantalum oxide layer may be first removed as an etch stop layer. Then remove the yttrium oxide layer.

Thereafter, a second ion implantation process 28 is performed to form a second source and drain extension 30 on top of the fin 14. Another ion implantation process is then performed to form a second pocket-type doped region (not shown). The second ion implantation process 28 is performed. The ion implantation angle θ ₂ of the second ion implantation process 28 is 90°. The second source and drain extension regions 30 have the same conductivity type dopant as the first source and drain extension regions 26, but have different conductivity types from the first pocket type doping region and the second pocket type doping region. Admixture. In one embodiment, the dopants of the first source and drain extension regions 26 and the second source and drain extension regions 30 are p-type; the first pocket-type doped region and the second pocket-type doped region The dopant is n-type. In another embodiment, the dopants of the first source and drain extension regions 26 and the second source and drain extension regions 30 are n-type; the first pocket-type doped region and the second pocket-type doped region The dopant is p-type. The P-type dopant is, for example, boron or boron difluoride; the N-type dopant is, for example, phosphorus or arsenic.

Thereafter, a spacer 32 is formed on the sidewall of the gate conductor layer 20a with reference to FIG. Then, an etching process is performed to remove a portion of the fins 14a to form two grooves 34 in the substrate 10 on both sides of the spacer 32. In an embodiment, the depth of the groove 34 is, for example, hundreds of angstroms. The shape of the groove 34 may be diamond-shaped or square, and is not particularly limited. Next, a semiconductor compound 36 is formed in each of the grooves 34. The semiconductor compound is, for example, a group IV-IV semiconductor compound. The Group IV-IV semiconductor compound may be composed of a first Group IV element and a second Group IV element. The first Group IV element is, for example, ruthenium; the second Group IV element is a non-ruthenium element, such as ruthenium or carbon. That is, the Group IV-IV semiconductor compound is, for example, germanium telluride (SiGe) or tantalum carbide (SiC). Semiconductor compound 36 can have a dopant.

In the PMOS device, the material of the semiconductor compound layer 36 is germanium telluride, and the dopant is P-type, for example, boron or boron difluoride; in the NMOS device, the material of the semiconductor compound layer 36 is tantalum carbide, and the dopant is N-type. For example, phosphorus or arsenic.

Thereafter, an ion implantation process 38 is performed to implant dopants into the semiconductor compound layer 36 to form source and drain regions 40, respectively. The source and drain regions 38 have the same conductivity type dopant as the second source and drain extension regions 30 and the first source and drain extension regions 26. In one embodiment, the dopant of the source and drain regions 40 is p-type. In another embodiment, the dopant of the source and drain regions 40 is n-type. The P-type dopant is, for example, boron or boron difluoride; the N-type dopant is, for example, phosphorus or arsenic.

Next, referring to FIG. 9, an etch stop layer 42 and a dielectric layer 44 are formed on the substrate. The material of the etch stop layer 42 is different from the material of the dielectric layer 44, and can be used as an etch stop layer during the subsequent etching of the dielectric layer 44. The material of the etch stop layer 42 is, for example, tantalum nitride or hafnium oxynitride, and is formed by, for example, chemical vapor deposition, and has a thickness of, for example, 50 to 1000 angstroms. The material of the dielectric layer 44 is, for example, ruthenium oxide, and is formed by, for example, chemical vapor deposition, and has a thickness of, for example, 1,000 to 5,000 angstroms.

Thereafter, referring to FIG. 10, a portion of the dielectric layer 42 and the etch stop layer 44 are removed to expose the gate conductor layer 20a. For example, the gate conductor layer 20a is used as a polishing stop layer, and a portion of the dielectric layer 42 and the etch stop layer 44 are removed by chemical mechanical polishing. Thereafter, the gate conductor layer 20a is removed to form an opening 46. A dielectric layer 48, a work function metal layer 50, and a metal layer 52 are sequentially formed in the opening 46. The dielectric layer 48 is, for example, a high dielectric constant material having a K value of more than 4, such as hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), niobium oxynitride (hafnium). Silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta ₂ O) ₅ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSiO ₄ ), or hafnium zirconium oxide (HfZrO). The work function metal layer 50 is, for example, titanium, tantalum, titanium nitride, tantalum nitride, titanium carbide or titanium aluminum alloy, or a combination thereof. The material of the metal layer 52 is, for example, aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof, and is formed by, for example, chemical vapor deposition or sputtering.

Thereafter, referring to FIG. 11, a portion of the metal layer 52, a portion of the work function metal layer 50, and a portion of the dielectric layer 48 are removed to form a gate metal layer 52a, a work function metal layer 50a, and a gate dielectric layer 48a. The removal method may be a chemical mechanical polishing method or an etch back method.

The dielectric layer 48 having a high dielectric constant of the above process is formed after the opening 46 is formed. However, the invention is not limited thereto. If a gate dielectric layer having a high dielectric constant (k value greater than 4) is formed on the fin 14 before forming the conductor material layer 20 of FIG. 3, the gate conductor layer of FIG. 10 is removed. After 20a, it is not necessary to form a gate dielectric layer 48 having a high dielectric constant (k value greater than 4).

12 to 15 are side views of a method of fabricating a MOS device in a first direction, in accordance with another embodiment of the present invention. 13A to 15A are perspective views of Figs. 13 to 15.

Referring to FIGS. 1 through 3, the fin 14, the hard mask layer 12a, the insulating layer 18a, and the conductive material layer 20 are formed in accordance with the methods of FIGS. 1 through 3 described above.

Thereafter, referring to FIG. 12, the conductor material layer 20 is planarized so that the surface of the remaining conductor material layer 20b is higher than the surface of the hard mask layer 12a.

Thereafter, referring to FIGS. 13 and 13A, the conductor material layer 20b is patterned by a lithography and etching process to form a gate conductor layer 20c.

Thereafter, referring to FIGS. 14 and 14A, a spacer 54 is formed around the gate conductor layer 20c. The spacer 54 is formed by, for example, depositing a layer of spacer material and then performing an anisotropic etching process. The material of the spacer material layer is, for example, tantalum nitride or tantalum oxide, which is formed by, for example, thermal oxidation or chemical vapor deposition.

Thereafter, the first ion implantation process 24 is performed with the first hard mask 12a and the spacers 54 as masks, and the first source and drain extension regions 56 are formed on the sidewalls of the fins 14. Another ion implantation process is then performed to form a first pocket-type doped region (not shown). The ion implantation angle of the first ion implantation process 24 is greater than 30°, such as 30°-60°. Since the spacer 54 covers the periphery of the gate conductor layer 20c, the distance (channel) between the first source and the drain extension 56 formed here is slightly larger than the first source formed in the previous embodiment. The distance between the pole and the bungee extension 26 (channel).

Thereafter, referring to Figures 7 and 7A, the hard mask layer 12a is removed in accordance with the method described above, exposing the top of the fins 14. Thereafter, a second ion implantation process 28 is performed to form a second source and drain extension 58 on top of the fin 14. Another ion implantation process is then performed to form a second pocket-type doped region (not shown). The second ion implantation process 28 has an ion implantation angle of 90°. Since the spacer 54 is attached around the gate conductor layer 20c, the distance (channel) between the second source and the drain extension 58 formed here is slightly larger than that formed in the previous embodiment. The distance (channel) between the source and the drain extension 30.

The subsequent process is similar to the process of FIG. 8 to FIG. 11 described above, and details are not described herein again.

The present invention utilizes two ion implantation processes to form source and drain extensions of different orientations, and may further include a two-pocket ion implantation process to form a pocket-type doped region. During the first ion implantation process and the first pocket type ion implantation process, the surface of the fin is covered by the first hard mask layer, so the dopant is not implanted on the top of the fin, but only A first source and drain extension region and a first pocket-type doped region are formed on sidewalls of the fin. After the first ion implantation process first pocket type ion implantation process, the first hard mask layer attached to the top of the fin is removed, and then the second ion implantation process is performed on the fin. The top forms a second source and drain extension and passes through a second pocket type ion implantation process to form a second pocket-type doped region. Since the first (pocket type) ion implantation process is different from the area implanted in the second (pocket type) ion implantation process, and the doses of the two ion implantation processes can be separately controlled, the doping concentration can be formed as well Deeply uniform source and drain extensions (and pocket doped areas). Moreover, the angle of the first ion implantation process is not excessively limited. Therefore, the margin of the process can be improved.

In summary, a three-dimensional structure of a MOS device (ie, a FinFET) having uniform doping characteristics can be fabricated, and the process is simple, the process margin is large, and excessive manufacturing cost is not increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12, 22. . . Hard mask material layer

12a, 22a. . . Patterned hard mask material layer

14. . . Fin

16. . . ditch

18. . . Insulating material layer

18a. . . Insulation

20, 20b. . . Conductor material layer

20a, 20c. . . Gate conductor layer

twenty four. . . First ion implantation process

26, 56. . . First source and drain extension

27. . . First pocket doped region

28. . . Second ion implantation process

30, 58. . . Second source and drain extension

32, 54. . . Clearance wall

34. . . Groove

36. . . Semiconductor compound

38. . . Ion implantation process

40. . . Source and bungee area

42. . . Etch stop layer

44, 48. . . Dielectric layer

46. . . Opening

48a. . . Gate dielectric layer

50, 50a. . . Work function metal layer

52. . . Metal layer

52a. . . Gate metal layer

θ ₁ , θ ₂ . . . angle

1 to 7 are side views of a method of fabricating a MOS device in a first direction, in accordance with an embodiment of the invention.

8 to FIG. 11 are schematic cross-sectional views showing a process of manufacturing the MOS device of FIG. 7 in a second direction.

5A to 7A are perspective views of Figs. 5 to 7.

12 to 15 are side views of a method of fabricating a MOS device in a first direction, in accordance with another embodiment of the present invention.

13A to 15A are perspective views of Figs. 13 to 15.

10. . . Base

12a, 22a. . . Patterned hard mask material layer

14. . . Fin

18a. . . Insulation

20a. . . Gate conductor layer

twenty four. . . First ion implantation process

26. . . First source and drain extension

θ ₁ . . . angle

Claims (15)

A method of fabricating a MOS device, comprising: forming a first hard mask material layer on a substrate; patterning the first hard mask material layer and removing a portion of the substrate to form a trench surrounded by a trench a fin and a first hard mask layer, wherein the fin extends in a first direction; an insulating layer is formed at a bottom of the trench; and a gate conductor layer is formed on the insulating layer of the trench The pole conductor layer extends in the second direction, wherein the gate conductor layer is formed by: forming a conductor material layer on the insulating layer of the trench; planarizing the conductor material layer, leaving the surface of the conductor material layer a surface of the first hard mask layer; and patterning the conductive material layer to form the gate conductor layer; using the first hard mask as a mask, performing a first ion implantation process, The sidewall of the fin forms a first source and drain extension; the first hard mask layer is removed to expose the top of the fin; and a second ion implantation process is performed on the fin The top of the body forms a second source and a drain Area. The method for fabricating a MOS device according to claim 1, wherein the method for forming the gate conductor layer comprises: forming a layer of a conductor material on the insulating layer of the trench; and using the first hard mask The layer is a stop layer, planarizing the conductor material layer; forming a second hard mask material layer on the conductor material layer; and patterning the second hard mask material layer and the conductor material layer to form a second hard mask layer and the gate conductor layer. The method for fabricating a MOS device according to claim 1, further comprising: forming a first spacer around the gate conductor layer before performing the first ion implantation process. The method for fabricating a MOS device according to claim 1, wherein the method for forming the insulating layer comprises: forming a layer of insulating material on the substrate; using the first hard mask layer as a stop layer, flat The insulating material layer is removed; and a portion of the insulating material layer in the trench is removed to form the insulating layer. The method of fabricating a MOS device according to claim 1, wherein the first ion implantation process has an ion implantation angle of 30°-60°. The method of manufacturing a MOS device according to claim 1, wherein the second ion implantation process has an ion implantation angle of 90°. The method for manufacturing a MOS device according to claim 1, further comprising: forming a second spacer on a sidewall of the gate conductor layer; removing a portion of the fin to the gate conductor Forming a recess on each side of the layer; forming a semiconductor compound in each of the recesses; and forming a source and drain regions in each of the semiconductor compounds. The system of MOS devices as described in claim 7 The method further includes: forming an etch stop layer on the substrate; and forming a dielectric layer on the etch stop layer. The method for fabricating a MOS device according to claim 8 , further comprising: removing a portion of the dielectric layer and the etch stop layer to expose the gate conductor layer; removing the gate conductor layer Forming an opening; and forming a gate metal layer in the opening. The method for fabricating a MOS device according to claim 9, further comprising: forming a work function metal layer in the opening before forming a gate metal layer in the opening. The method for fabricating a MOS device according to claim 9, further comprising: forming a gate dielectric layer in the opening before forming the gate metal layer in the opening. The method of fabricating a MOS device according to claim 11, wherein the first gate dielectric layer has a dielectric constant higher than 4. The method for fabricating a MOS device according to claim 9, further comprising: forming a first thyristor layer on the fin before forming the gate conductor layer. As claimed in claim 13 of the MOS device The manufacturing method, wherein the first gate dielectric layer has a dielectric constant of less than 4. The method for fabricating a MOS device according to claim 14, further comprising: removing the first thyristor layer after removing the gate conductor layer; and removing the first thyristor dielectric A second gate dielectric layer is formed after the layer, wherein the second gate dielectric layer has a dielectric constant higher than 4.