TWI520245B - Methods of characterizing semiconductor light-emitting devices based on product wafer characteristics - Google Patents
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Description
本發明係關於發光二極體及雷射二極體的半導體發光裝置(LED)之製造,尤其係關於一種基於產品晶圓特性來特性化半導體LED之方法。 The present invention relates to the fabrication of semiconductor light-emitting devices (LEDs) for light-emitting diodes and laser diodes, and more particularly to a method for characterizing semiconductor LEDs based on product wafer characteristics.
在實際上全部的燈及照明應用範圍中,諸如發光二極體及雷射二極體之半導體LED正快速替代習知光源。結果,正按不斷增加之數目、針對非常廣泛範圍之發射波長製造半導體LED。 In virtually all lighting and lighting applications, semiconductor LEDs such as light-emitting diodes and laser diodes are rapidly replacing conventional light sources. As a result, semiconductor LEDs are being fabricated for a very wide range of emission wavelengths in increasing numbers.
用於一般採光之實例半導體LED為發光二極體(亦稱作「LED」)及雷射二極體。可使用磷光體塗層創造「白」光光譜。磷光體與裝置之特定發射波長(例如,藍波長)反應,且斯托克(Stokes)將發射光之一部分自較短波長移位至較長波長以賦予輸出光白光譜。白光譜可由與對應的黑體輻射之發射光譜相關聯的等效色溫來特性化。「暖」的白光譜由大致2800°K之色溫來特性化,而「冷」白光譜具有大致5000°K之色溫。在大量應用中,暖白光譜係較佳的。 Example semiconductor LEDs for general daylighting are light emitting diodes (also known as "LEDs") and laser diodes. Phosphorescent coatings can be used to create a "white" spectrum of light. The phosphor reacts with a particular emission wavelength of the device (eg, blue wavelength), and Stokes shifts a portion of the emitted light from a shorter wavelength to a longer wavelength to impart an output white spectrum. The white spectrum can be characterized by an equivalent color temperature associated with the emission spectrum of the corresponding blackbody radiation. The "warm" white spectrum is characterized by a color temperature of approximately 2800 °K, while the "cold" white spectrum has a color temperature of approximately 5000 °K. In many applications, warm white spectroscopy is preferred.
為了獲得適當色溫,需要使半導體發光裝置之發射波長λE匹配磷光體之吸收及發射光譜△λ。通常,實際發射波長λE需要與所要的(選擇)發射之波長λED相差不超過+/- 2 nm,以與磷光體吸收及發射特性適當匹配。在適當匹配後,LED燈具提供具有大約2800°K之色溫的「白光」。在特定波長規格外之裝置具有小得多 的價值,此係因為其產生「變色」且因此不大為消費者所需之光。LED製造商常將此等「變色」LED出售給色彩較不關鍵之應用,諸如,閃光燈或外部停車場設施。然而,此等LED之價值比出售給一般家用照明市場之LED小得多,在一般家用照明市場,色溫很關鍵。為此,LED製造商努力在每晶圓中製造更多的在較有價值光譜範圍內的LED。 To obtain an appropriate color temperature, it is necessary to make the emission wavelength [lambda] of the semiconductor light emitting device E match absorbed by the phosphor and an emission spectrum of △ λ. Typically, the actual emission wavelength λ E needs to differ from the desired (selected) emission wavelength λ ED by no more than +/- 2 nm to properly match the phosphor absorption and emission characteristics. After proper matching, the LED luminaires provide "white light" with a color temperature of approximately 2800 °K. Devices that are outside of a particular wavelength specification have much less value because they produce "discoloration" and are therefore less of a light desired by the consumer. LED manufacturers often sell these "discoloration" LEDs to applications where color is less critical, such as flashlights or external parking facilities. However, the value of such LEDs is much smaller than the LEDs sold to the general household lighting market, where color temperature is critical. To this end, LED manufacturers strive to create more LEDs in each of the more valuable spectral ranges.
為了最佳良率及因此最佳價值及利潤,需要製造半導體發光裝置,使得其具有在指定容限內之準確的發射波長。亦需要能夠事先知曉在製造過程期間進入最終半導體發光裝置的發光晶片(晶粒)之發射波長。 For optimum yield and therefore best value and profit, it is desirable to fabricate a semiconductor light emitting device that has an accurate emission wavelength within a specified tolerance. There is also a need to be able to know in advance the emission wavelength of the luminescent wafer (grain) entering the final semiconductor light-emitting device during the manufacturing process.
揭示了基於產品晶圓特性來特性化半導體發光裝置(LED)之方法。該等方法包括量測至少一產品晶圓特性,諸如,曲率或裝置層應力。該方法亦包括確立該至少一特性與自產品晶圓形成的LED晶粒之發射波長之間的關係。該關係允許預測在類似形成之產品晶圓之裝置層中形成的LED結構之發射波長。此又可用以特性化產品晶圓及在大量LED製造中執行製程控制。 A method of characterizing a semiconductor light emitting device (LED) based on product wafer characteristics is disclosed. The methods include measuring at least one product wafer characteristic, such as curvature or device layer stress. The method also includes establishing a relationship between the at least one characteristic and an emission wavelength of the LED dies formed from the product wafer. This relationship allows prediction of the emission wavelength of the LED structure formed in the device layer of a similarly formed product wafer. This in turn can be used to characterize product wafers and perform process control in a large number of LED fabrications.
根據本發明之一態樣,一種方法包括藉由量測一測試產品晶圓之一裝置層應力S(x,y),分割該測試產品晶圓以形成晶粒,及量測該等晶粒的隨其裝置層應力及對應的裝置結構位置(x,y)而變之發射波長來確立該裝置層應力S(x,y)與形成於該產品晶圓上之該等裝置結構之發射波長λE(x,y)之間的一關係。該方法進一步 包括基於在用以形成該等裝置結構的基板處理之前及之後執行的該基板之曲率量測來量測該測試產品晶圓之一曲率改變△C(x,y)。該方法亦包括基於該量測之曲率改變△C來計算該測試產品晶圓中之該裝置層應力S(x,y)。且該方法進一步包括基於該裝置層應力S(x,y)與該測試產品晶圓上之該等(x,y)位置之間的該關係使該實際發射波長λE與該等裝置結構相關聯,以確立該等裝置結構之對應於該發射波長λE的一預測之發射波長。 According to one aspect of the invention, a method includes dividing a test product wafer to form a die by measuring a device layer stress S(x, y) of a test product wafer, and measuring the grains The emission wavelength of the device layer is determined by the device layer stress and the corresponding device structure position (x, y) to establish the device layer stress S(x, y) and the emission wavelength of the device structures formed on the product wafer. A relationship between λ E (x, y). The method further includes measuring a curvature change ΔC(x, y) of the test product wafer based on a curvature measurement of the substrate performed before and after processing the substrate to form the device structures. The method also includes calculating the device layer stress S(x, y) in the test product wafer based on the measured curvature change ΔC. And the method further includes correlating the actual emission wavelength λ E with the device structure based on the relationship between the device layer stress S(x, y) and the (x, y) position on the test product wafer To establish a predicted emission wavelength of the device structure corresponding to the emission wavelength λ E .
該方法較佳地進一步包括經由以下關係基於該量測之曲率改變△C來計算該測試產品晶圓中之應力S(x,y)S(x,y)={MShS 2/6hF}△C(x,y) The method preferably further comprises calculating a stress S(x,y)S(x,y)={M S h S 2 /6h in the test product wafer based on the measured curvature change ΔC via the following relationship F }△C(x,y)
其中Ms為該基板20之一雙軸向模數,hS為該基板之一高度,hF為該等裝置結構之一厚度。 Where M s is a biaxial modulus of the substrate 20, h S is a height of the substrate, and h F is a thickness of one of the device structures.
在該方法中,該等裝置結構可具有一發光二極體或雷射二極體組態。 In this method, the device structures can have a light emitting diode or a laser diode configuration.
該方法較佳地進一步包括確立一所要的發射波長,分割該產品晶圓以自該等裝置結構形成晶粒,及基於該預測之發射波長精選該等晶粒。 The method preferably further includes establishing a desired emission wavelength, dividing the product wafer to form a die from the device structures, and selecting the grains based on the predicted emission wavelength.
該方法較佳地進一步包括定義該發射波長之一變化量的一容限,及將該預測之發射波長與該容限比較,且自該比較判定一行動方案,包括拋棄該產品晶圓、重加工該產品晶圓或使用該產品晶圓之一選定部分。 The method preferably further includes defining a tolerance of the amount of change in the emission wavelength, and comparing the predicted emission wavelength to the tolerance, and determining an action scheme from the comparison, including discarding the product wafer, heavy Process the wafer of the product or use a selected portion of the wafer of the product.
在該方法中,該基板處理可包括執行一有機金屬化學氣相沈積(MOCVD)製程。 In the method, the substrate processing can include performing an organometallic chemical vapor deposition (MOCVD) process.
本發明之另一態樣為一種特性化具有一基板及一裝置層的一產品晶圓之一半導體發光裝置(LED)結構之一發射波長之方法。該方法包括量測以實質上與該產品晶圓相同的方式形成之一測試產品晶圓之至少一特性,其中該至少一特性係選自包含裝置層應力及產品晶圓曲率的特性之群組。該方法亦包括分割該至少一測試產品晶圓以形成LED晶粒,該等LED晶粒具有與之相關聯的在該測試產品晶圓上之一位置。該方法亦包括量測該等LED晶粒中之每一者的一LED發射波長以確立隨該產品晶圓上之位置變化的一組LED發射波長。該方法進一步包括判定該至少一測試產品晶圓特性、該組LED發射波長與該等LED晶粒之該等位置之間的一關係,及使用在動作「判定一關係」中判定之關係預測形成於該產品晶圓上的該等LED結構之LED發射波長。 Another aspect of the invention is a method of characterizing one of the semiconductor light emitting device (LED) structures of a product wafer having a substrate and a device layer. The method includes measuring at least one characteristic of a test product wafer in substantially the same manner as the product wafer, wherein the at least one characteristic is selected from the group consisting of: a device layer stress and a product wafer curvature characteristic . The method also includes dividing the at least one test product wafer to form LED dies having a location associated with the test product wafer associated therewith. The method also includes measuring an LED emission wavelength of each of the LED dies to establish a set of LED emission wavelengths as a function of position on the product wafer. The method further includes determining a relationship between the wafer characteristics of the at least one test product, the set of LED emission wavelengths, and the locations of the LED dies, and predicting the relationship using the relationship determined in the action "decision-relationship" The LED emission wavelength of the LED structures on the product wafer.
該方法較佳地包括基於在動作「判定一關係」中之該關係分選該產品晶圓之該等LED結構。 The method preferably includes sorting the LED structures of the product wafer based on the relationship in the action "Decision-Relationship".
在該方法中,該產品晶圓較佳地包括一基板。且該方法較佳地進一步包括在形成該產品晶圓之前量測該基板之一曲率。 In the method, the product wafer preferably includes a substrate. And the method preferably further comprises measuring a curvature of the substrate prior to forming the product wafer.
該方法較佳地進一步包括使用相干梯度感測(CGS)量測基板曲率及產品晶圓曲率中之至少一者。 The method preferably further includes measuring at least one of a substrate curvature and a product wafer curvature using coherent gradient sensing (CGS).
在該方法中,該等裝置結構可具有一尺寸。且該方法較佳地 包括在實質上等於或小於該裝置結構尺寸之一尺寸上判定該至少一測試產品晶圓特性。 In this method, the device structures can have a size. And the method is preferably The determining at least one test product wafer characteristic is determined at a size substantially equal to or less than one of the device structural dimensions.
本發明之另一態樣為一種形成半導體發光裝置(LED)之方法。該方法包括藉由具有一或多個製程變數之一製程形成包含形成於一基板上之LED結構的一產品晶圓,其中在於該基板上形成該等LED結構前,該基板具有一已知初始曲率C0(x,y)。該方法進一步包括在於該產品晶圓上形成該等發光裝置結構後量測該產品晶圓之一曲率C(x,y),且判定一曲率改變△C(x,y)=C(x,y)-C0(x,y)。該方法進一步包括基於該量測之曲率改變△C(x,y)來計算該產品晶圓中之一應力S(x,y)。該方法進一步包括基於該計算之應力S(x,y)與在該產品晶圓上的該等發光裝置結構之(x,y)位置之間的一關係而使該等LED結構之一發射波長λE與該計算之應力S(x,y)相關聯。且該方法進一步包括將該發射波長λE與一發射波長變化容限比較,且基於該容限將該等LED結構分選至一或多個箱(bin)內。 Another aspect of the invention is a method of forming a semiconductor light emitting device (LED). The method includes forming a product wafer comprising an LED structure formed on a substrate by one of a process variable having one or more process variables, wherein the substrate has a known initiality prior to forming the LED structures on the substrate Curvature C 0 (x, y). The method further includes measuring a curvature C(x, y) of the product wafer after forming the light-emitting device structure on the product wafer, and determining a curvature change ΔC(x, y)=C(x, y) - C 0 (x, y). The method further includes calculating a stress S(x, y) in the product wafer based on the measured curvature change ΔC(x, y). The method further includes causing one of the LED structures to emit a wavelength based on a relationship between the calculated stress S(x, y) and the (x, y) position of the illuminator structures on the product wafer λ E is associated with the calculated stress S(x, y). And the method further includes comparing the emission wavelength λ E to an emission wavelength variation tolerance, and sorting the LED structures into one or more bins based on the tolerance.
該方法較佳地進一步包括僅使用在一或多個選定箱中之LED結構形成LED裝置。 The method preferably further includes forming the LED device using only the LED structures in one or more selected bins.
該方法較佳地進一步包括調整該一或多個製程變數中之至少一者以減小該等發光裝置結構中的隨在該產品晶圓上的該等發光裝置結構之該等(x,y)位置而變的發射波長變化之一量。 The method preferably further includes adjusting at least one of the one or more process variables to reduce the structure of the illuminating devices on the product wafer in the illuminating device structure (x, y The amount of change in the wavelength of the change in position.
在該方法中,該等製程變數較佳地選自包含下列各者的製程 變數之集合:時間、溫度、溫度均勻性、氣體分壓、氣體分壓均勻性、氣體流動速率及氣體流動均勻性。 In the method, the process variables are preferably selected from processes comprising the following A collection of variables: time, temperature, temperature uniformity, gas partial pressure, gas partial pressure uniformity, gas flow rate, and gas flow uniformity.
該方法較佳地進一步包括進行按與該產品晶圓相同的方式形成之一或多個測試產品晶圓之曲率量測,分割該一或多個測試產品晶圓以形成LED晶粒,及量測該等LED晶粒之發射波長為在該一或多個測試產品晶圓上之該等LED晶粒之(x,y)位置對該量測之測試產品晶圓曲率對該等發射波長之一函數。 The method preferably further includes performing a curvature measurement of one or more test product wafers in the same manner as the product wafer, dividing the one or more test product wafers to form LED dies, and Detecting the emission wavelengths of the LED dies for the (x, y) position of the LED dies on the one or more test product wafers a function.
該方法較佳地進一步包括形成一新產品晶圓,量測該新產品晶圓之該曲率,及基於該新產品晶圓之該量測之曲率判定在該新產品晶圓上的LED結構之LED發射波長。 The method preferably further includes forming a new product wafer, measuring the curvature of the new product wafer, and determining an LED structure on the new product wafer based on the measured curvature of the new product wafer LED emission wavelength.
本發明之另一態樣為一種形成半導體發光裝置(LED)之方法。該方法包括藉由具有一或多個製程變數之一製程形成包含形成於一半導體基板上之LED結構的一產品晶圓,在於該產品晶圓上形成該等LED結構後量測該產品晶圓之一曲率均勻性,及調整該一或多個製程變數中之至少一者以符合一曲率均勻性要求及一應力均勻性要求中之至少一者。 Another aspect of the invention is a method of forming a semiconductor light emitting device (LED). The method includes forming a product wafer including an LED structure formed on a semiconductor substrate by one of a process variable having one or more process variables, and measuring the product wafer after forming the LED structures on the product wafer One of curvature uniformity, and adjusting at least one of the one or more process variables to meet at least one of a curvature uniformity requirement and a stress uniformity requirement.
本發明之另一態樣為一種形成一半導體發光裝置(LED)之方法。該方法包括藉由具有一或多個製程變數之一製程形成包含形成於一基板上之LED結構的一產品晶圓,其中在於該基板上形成該等發光裝置結構前,該基板具有已知初始曲率C0(x,y)。該方法亦包括在於該產品晶圓上形成該等發光裝置結構後量測該產 品晶圓之一曲率C(x,y),且基於C0(x,y)及C(x,y)判定一曲率均勻性。該方法亦包括判定屬於曲率均勻性之一第一範圍的第一數目個晶粒。該方法亦包括判定屬於曲率均勻性之一第二範圍的第二數目個晶粒。且該方法亦包括基於該第一數目及該第二數目為該產品晶圓指派一品質值。 Another aspect of the invention is a method of forming a semiconductor light emitting device (LED). The method includes forming a product wafer comprising an LED structure formed on a substrate by one of a process variable having one or more process variables, wherein the substrate has a known initiality prior to forming the light emitting device structure on the substrate curvature C 0 (x, y). The method also includes measuring a curvature C(x, y) of the product wafer after forming the light-emitting device structure on the product wafer, and determining based on C 0 (x, y) and C (x, y) A uniformity of curvature. The method also includes determining a first number of grains belonging to a first range of curvature uniformity. The method also includes determining a second number of grains belonging to a second range of curvature uniformity. And the method also includes assigning a quality value to the product wafer based on the first number and the second number.
該方法較佳地進一步包括基於該指派之品質值安排該產品晶圓。 The method preferably further includes arranging the product wafer based on the assigned quality value.
該方法較佳地進一步包括分割該產品晶圓以形成與該第一數目及該第二數目相關聯之LED晶粒。該方法較佳地進一步包括將與該第一數目相關聯之該等LED晶粒用於一第一應用,及將與該第二數目相關聯之該等LED晶粒用於一第二應用。 The method preferably further includes splitting the product wafer to form LED dies associated with the first number and the second number. The method preferably further includes using the LED dies associated with the first number for a first application, and using the LED dies associated with the second number for a second application.
本發明之另一態樣為一種形成半導體發光裝置之方法。該方法包括藉由具有一或多個製程變數之一製程形成包含形成於一基板上之發光裝置結構的一產品晶圓,其中在於該基板上形成該等發光裝置結構前,該基板具有已知初始曲率C0(x,y)。該方法亦包括在於該產品晶圓上形成該等發光裝置結構後量測該產品晶圓之一曲率C(x,y),且判定一曲率改變△C(x,y)=C(x,y)-C0(x,y)。該方法亦包括基於該計算之曲率C(x,y)與在該產品晶圓上的該等發光裝置結構之(x,y)位置之間的一關係使該等發光裝置結構之一發射波長λE與該計算之晶圓曲率C(x,y)相關聯。且該方法亦包括將該發射波長λE與一發射波長變化容限比較以判定可使用 哪些發光結構來形成一發光裝置。 Another aspect of the invention is a method of forming a semiconductor light emitting device. The method includes forming a product wafer comprising a light-emitting device structure formed on a substrate by one of a process variable having one or more process variables, wherein the substrate has a known structure before the light-emitting device structure is formed on the substrate Initial curvature C 0 (x, y). The method also includes measuring a curvature C(x, y) of the product wafer after forming the light-emitting device structure on the product wafer, and determining a curvature change ΔC(x, y)=C(x, y) - C 0 (x, y). The method also includes causing one of the illuminating device structures to emit a wavelength based on a relationship between the calculated curvature C(x, y) and the (x, y) position of the illuminating device structures on the product wafer λ E is associated with the calculated wafer curvature C(x, y). And the method also includes comparing the emission wavelength λ E with an emission wavelength variation tolerance to determine which illumination structures can be used to form a illumination device.
本發明之額外特徵及優勢在以下詳細描述中闡明,且部分地將由熟習此項技術者自彼描述顯而易見,或藉由實踐如本文中描述之本發明(包括以下詳細描述、申請專利範圍及附圖)來認識到。申請專利範圍被併入至本發明之詳細描述內且構成本發明之詳細描述之部分。 The additional features and advantages of the invention are set forth in the description which follows, and in part Figure) to recognize. The scope of the invention is incorporated in the Detailed Description of the Invention and is a part of the detailed description of the invention.
應理解,前述總體描述及以下詳細描述皆呈現本發明之實施例,且意欲提供用於理解本發明之性質及特性(如其被主張)的綜述或構架。包括隨附圖式以提供對本發明之進一步理解,且隨附圖式被併入至此說明書內且構成此說明書之一部分。該等圖式說明本發明之各種實施例且與描述一起用以解釋本發明之原理及操作。 It is to be understood that both the foregoing general description and the following description of the embodiments of the invention The accompanying drawings are included to provide a further understanding of the invention The drawings illustrate various embodiments of the invention and, together,
現在詳細參考本發明之目前較佳實施例,該等實施例之實例說明於隨附圖式中。在可能時,貫穿該等圖式使用相同參考數字及符號來指代相同或相似部分。申請專利範圍被併入至此詳細描述內且構成此詳細描述之部分。 Reference will now be made in detail to the preferred embodiments embodiments Wherever possible, the same reference numerals and the The scope of the patent application is incorporated into and constitutes a part of this detailed description.
在以下論述中,裝置層應力為裝置層30中之界定形成於裝置層30中之裝置50的應力,且由S(x,y)或僅S表示,其為S(x,y;σ i,j )之速記記法,其中σ i,j 為應力張量。應力張量σ i,j 定義在基板之裝置層中之任一點處的應力。座標(x,y)表示裝置層30中定義了應力之點的晶圓笛卡爾座標。應力張量σ i,j 定義三個正交法向 應力分量(σ11、σ22、σ33)及六個正交剪應力(σ 12 、σ 13 、σ 21 、σ 23 、σ 31 、σ 32 )。當用以量測應力之座標系統定向於主方向上時,應力張量僅包含三個正交法向應力分量。在一實例中,S(x,y)具有表示應力之單一值,且此單一值可為(例如)最大應力分量、應力分量之總和、應力分量之平均值或應力分量之某一組合。在使用在給定(x,y)位置處的應力改變速率之另一實例中,使用記法S'(x,y)。 In the following discussion, the device layer stress is the stress in the device layer 30 that defines the device 50 formed in the device layer 30, and is represented by S(x, y) or only S, which is S(x, y; σ i , j ) shorthand notation, where σ i,j is the stress tensor. The stress tensor σ i,j defines the stress at any point in the device layer of the substrate. The coordinates (x, y) represent the wafer Cartesian coordinates of the point in the device layer 30 where the stress is defined. The stress tensor σ i,j defines three orthogonal normal stress components (σ 11 , σ 22 , σ 33 ) and six orthogonal shear stresses (σ 12 , σ 13 , σ 21 , σ 23 , σ 31 , σ 32 ). When the coordinate system used to measure stress is oriented in the main direction, the stress tensor contains only three orthogonal normal stress components. In one example, S(x,y) has a single value representative of stress, and this single value can be, for example, a maximum stress component, a sum of stress components, an average of stress components, or some combination of stress components. In another example of using a rate of stress change at a given (x, y) position, the notation S'(x, y) is used.
又,在以下論述中,表面之曲率C(x,y)為C(x,y; n )之速記,其中 n 為X-Y平面中在給定方向上之法向向量,且其界定與X-Y平面成直角地與表面相交之一平面,且C(x,y)為該表面當與該平面相交時形成的曲線之曲率。通常將曲率定義為1/R,其中R為在由法向向量 n 界定之平面中的點(x,y)處該表面之彎曲之局部半徑。在一實例中,沿著單一方向取得 n ,在該情況下,C(x,y)為純量函數。通常,C(x,y)為張量,此係因為其可具有與其相關聯之多個曲率,即,對於單位向量 n 之每一方向有一個曲率。在一實例中,可自定義每一(x,y)表面點之高度(如相對於某一參考平面(例如,完全平坦的晶圓)所量測)的函數H(x,y)判定曲率C(x,y)。詳言之,可藉由使圓曲線擬合至給定平面中之在點(x,y)周圍的點以獲得最佳擬合半徑R且接著將曲率判定為1/R來根據H(x,y)獲得C(x,y)。亦可使用標準數學技術自H(x,y)之二階導數獲得C(x,y)。使用記法C0來表示用以形成產品晶圓的基板之曲率。 Also, in the following discussion, the curvature C(x, y) of the surface is a shorthand for C(x, y; n ), where n is the normal vector in a given direction in the XY plane, and it is defined with the XY plane A plane intersecting the surface at right angles, and C(x, y) is the curvature of the curve formed by the surface when intersecting the plane. Curvature is generally defined as 1/R, where R is the local radius of the curvature of the surface at a point (x, y) in the plane defined by the normal vector n . In one example, n is taken in a single direction, in which case C(x, y) is a scalar function. Typically, C(x,y) is a tensor because it can have multiple curvatures associated with it, i.e., one curvature for each direction of the unit vector n . In one example, the height of each (x,y) surface point can be customized (as measured relative to a reference plane (eg, a perfectly flat wafer) by a function H(x, y) to determine the curvature C(x, y). In detail, H(x) can be obtained by fitting a circular curve to a point around a point (x, y) in a given plane to obtain a best fit radius R and then determining the curvature as 1/R. , y) obtain C(x, y). C(x, y) can also be obtained from the second derivative of H(x, y) using standard mathematical techniques. The notation C 0 is used to indicate the curvature of the substrate used to form the product wafer.
在本文中之論述中,通常將縮寫「LED」理解為意謂「發光裝置」,但其亦可意謂「發光二極體」,且熟習此項技術者會基於使用此縮寫之上下文來理解該差異。 In the discussion herein, the abbreviation "LED" is generally understood to mean "lighting device", but it can also mean "light emitting diode", and those skilled in the art will understand based on the context of using this abbreviation. The difference.
圖1為用以形成半導體LED(諸如,發光二極體及雷射二極體)的一實例產品晶圓10之平面圖,且圖2為其橫截面圖。此處,術語「產品晶圓」通常意謂其上形成有裝置結構之晶圓或基板,且其中裝置結構接著被用以製造發光裝置,在一實例中,發光裝置可用以形成LED產品或裝置。 1 is a plan view of an example product wafer 10 used to form a semiconductor LED, such as a light emitting diode and a laser diode, and FIG. 2 is a cross-sectional view thereof. As used herein, the term "product wafer" generally means a wafer or substrate having a device structure formed thereon, and wherein the device structure is then used to fabricate a light emitting device, in one example, the light emitting device can be used to form an LED product or device. .
產品晶圓10包含一半導體基板20,其具有一邊緣21、一頂表面22及一底表面24,其中裝置層30形成於表面22上。一實例半導體基板20由藍寶石或矽製成。裝置層30包含半導體發光裝置結構(「裝置結構」)40之一陣列32。在一實例中,產品晶圓10包括可具有約1 mm之大小的數千個裝置結構40。對於藍寶石基板20而言,實例產品晶圓10具有2吋至6吋之直徑,且對於矽基板而言,具有6吋至12吋之直徑。裝置結構40具有與其相關聯之實際發射波長λE及與前述色溫相關聯之輸出光譜△λ。將裝置結構40之所要或選定發射波長表示為λED。 The product wafer 10 includes a semiconductor substrate 20 having an edge 21, a top surface 22, and a bottom surface 24, wherein the device layer 30 is formed on the surface 22. An example semiconductor substrate 20 is made of sapphire or germanium. Device layer 30 includes an array 32 of semiconductor light emitting device structures ("device structures") 40. In one example, product wafer 10 includes thousands of device structures 40 that can have a size of about 1 mm. For the sapphire substrate 20, the example product wafer 10 has a diameter of 2 吋 to 6 , and has a diameter of 6 吋 to 12 矽 for the 矽 substrate. The device structure 40 has an actual emission wavelength λ E associated therewith and an output spectrum Δλ associated with the aforementioned color temperature. The desired or selected emission wavelength of device structure 40 is expressed as λ ED .
一旦產品晶圓10經完全處理而使得裝置結構40發揮功能,則切割(「分割」)產品晶圓10,使得分開陣列32中之個別裝置結構以形成個別晶粒42。接著將晶粒42併入至半導體發光裝置結構內以形成發光裝置50,諸如,在圖3中說明為一實例LED 裝置之透視圖。圖3之LED裝置50包括延伸至環氧樹脂透鏡殼56之內部54中的一陽極52A及一陰極52C。陰極52C包括晶粒42所在之反射腔58。線接合60將陽極52A及陰極52C電連接至LED。電源(未圖示)連接至陽極52A及陰極52C以提供對LED供電所需之電,使得LED在實際波長λE下發射光62。當晶粒42為先前技術晶粒時,圖3之LED裝置50為先前技術裝置,但當使用本文中揭示之方法形成晶粒42時,圖3之LED裝置50就並非先前技術裝置。 Once the product wafer 10 is fully processed such that the device structure 40 functions, the product wafer 10 is diced ("split") such that individual device structures in the array 32 are separated to form individual dies 42. The die 42 is then incorporated into a semiconductor light emitting device structure to form a light emitting device 50, such as illustrated in Figure 3 as a perspective view of an example LED device. The LED device 50 of FIG. 3 includes an anode 52A and a cathode 52C that extend into the interior 54 of the epoxy lens housing 56. Cathode 52C includes a reflective cavity 58 in which die 42 is located. Wire bond 60 electrically connects anode 52A and cathode 52C to the LED. A power source (not shown) is coupled to anode 52A and cathode 52C to provide the power required to power the LED such that the LED emits light 62 at the actual wavelength λ E . When the die 42 is a prior art die, the LED device 50 of FIG. 3 is a prior art device, but when the die 42 is formed using the methods disclosed herein, the LED device 50 of FIG. 3 is not a prior art device.
實例裝置結構40為藉由在藍寶石基板20上生長GaN而製造的LED之形式。使用有機金屬化學氣相沈積(MOCVD)製程來生長GaN。MOCVD製程在MOCVD反應器中進行,且按導致形成多量子井結構(未圖示)的方式執行。 The example device structure 40 is in the form of an LED fabricated by growing GaN on a sapphire substrate 20. GaN is grown using a metalorganic chemical vapor deposition (MOCVD) process. The MOCVD process is performed in an MOCVD reactor and is performed in a manner that results in the formation of a multi-quantum well structure (not shown).
圖4展示支撐於具有一頂表面72之基板固持器或晶座70中的藍寶石基板20之集合。圖5為說明將基板20支撐於晶座70中之方式的一實例之晶座70之特寫橫截面圖。晶座70包括形成於頂表面72中之開口76,其中開口界定在基板之底表面24上在基板之邊緣21附近支撐基板20的端緣78。 4 shows a collection of sapphire substrates 20 supported in a substrate holder or wafer holder 70 having a top surface 72. FIG. 5 is a close-up cross-sectional view of the crystal holder 70 illustrating an example of the manner in which the substrate 20 is supported in the crystal holder 70. The crystal holder 70 includes an opening 76 formed in the top surface 72, wherein the opening defines an end edge 78 that supports the substrate 20 near the edge 21 of the substrate on the bottom surface 24 of the substrate.
圖6展示具有可操作地連接至MOCVD子系統96之反應器腔室100之MOCVD反應器系統90。MOCVD子系統96包括各種MOCVD系統組件(未圖示),諸如,真空泵、氣體源、通風系統、baratron(薄膜電容式壓力傳感器)等。MOCVD腔室100具有 當執行MOCVD製程時晶座70及基板20位於其中之內部104。注意,在執行了MOCVD製程後,基板20變為產品晶圓10。MOCVD反應器系統90包括一控制器110,其可操作地耦接至MOCVD子系統96。控制器110經組態以控制發生於反應器內部104中之MOCVD製程(如由箭頭105指示)。 FIG. 6 shows an MOCVD reactor system 90 having a reactor chamber 100 operatively coupled to an MOCVD subsystem 96. The MOCVD subsystem 96 includes various MOCVD system components (not shown) such as a vacuum pump, a gas source, a ventilation system, a baratron (film capacitive pressure sensor), and the like. The MOCVD chamber 100 has The crystal holder 70 and the substrate 20 are located inside the interior 104 when the MOCVD process is performed. Note that the substrate 20 becomes the product wafer 10 after the MOCVD process is performed. MOCVD reactor system 90 includes a controller 110 that is operatively coupled to MOCVD subsystem 96. Controller 110 is configured to control the MOCVD process occurring in reactor interior 104 (as indicated by arrow 105).
詳言之,將控制器110用以仔細控制產品晶圓10之溫度T,此係因為實際發射波長λE顯著地隨MOCVD生長條件而變化。圖7A至圖7D為一實例產品晶圓10之平面圖,其分別示意性說明溫度T(x,y)、裝置尺寸D(x,y)、裝置層應力S(x,y)及(實際)發射波長λE(x,y)之實例等值線。此處,由於基板20正經歷處理以形成產品晶圓10,故溫度T指基板溫度或產品晶圓溫度。為了易於論述,以下之論述指「產品晶圓溫度」。 In particular, the controller 110 is used to carefully control the temperature T of the product wafer 10 because the actual emission wavelength λ E varies significantly with MOCVD growth conditions. 7A-7D are plan views of an example product wafer 10, which schematically illustrate temperature T(x, y), device size D(x, y), device layer stress S(x, y), and (actual), respectively. An example contour of the emission wavelength λ E (x, y). Here, since the substrate 20 is undergoing processing to form the product wafer 10, the temperature T refers to the substrate temperature or the product wafer temperature. For ease of discussion, the following discussion refers to "product wafer temperature."
隨著產品晶圓溫度T(x,y)改變(圖7A),裝置尺寸D(x,y)(例如,在MOCVD製程期間形成的多量子井結構(未圖示)之厚度)按對應方式改變(圖7B)。此亦轉譯為在產品晶圓10上的裝置層應力S(x,y)之對應改變(圖7C),其又導致實際發射波長λE(x,y)之對應改變(圖7D)。 As the product wafer temperature T(x,y) changes (Fig. 7A), the device size D(x,y) (eg, the thickness of a multiple quantum well structure (not shown) formed during the MOCVD process) is in a corresponding manner Change (Figure 7B). This is also translated as a corresponding change in the device layer stress S(x, y) on the product wafer 10 (Fig. 7C), which in turn results in a corresponding change in the actual emission wavelength λ E (x, y) (Fig. 7D).
在某些情況下,產品晶圓溫度T之1°K溫度改變可導致發射波長λE的大致1 nm之位移δλE。因此,首先偵測且最終控制MOCVD反應器系統90中之溫度不均勻性及溫度可重複性以確保對產品晶圓溫度T之適當控制變得合乎需要。產品晶圓上之溫 度不均勻性可導致生長條件之局部改變,其可導致LED發射波長之變化。 In some cases, the product wafer temperature T 1 ° K temperature change may result in the emission wavelength λ E of approximately 1 nm displacement δλ E. Therefore, it is desirable to first detect and ultimately control temperature non-uniformity and temperature repeatability in the MOCVD reactor system 90 to ensure proper control of the product wafer temperature T. Temperature non-uniformity on the product wafer can result in localized changes in growth conditions that can result in changes in the LED emission wavelength.
在裝置結構40的當今基於MOCVD之製造中,實際發射波長λE及對應的發射均勻性直至自產品晶圓10分割裝置結構40以形成晶粒42且接著將晶粒併入至諸如圖3之LED裝置50的發光裝置或等效測試結構內才已知。 In today's MOCVD-based fabrication of device structure 40, the actual emission wavelength λE and corresponding emission uniformity are up to the device wafer 40 from the product wafer 10 to form the die 42 and then the die is incorporated into an LED such as FIG. The illumination device or equivalent test structure of device 50 is known.
當前,為了估計或預測LED發射波長λE,藉由光致發光技術來檢驗基板,其中使短波長源(通常248 nm)入射於多量子井區域上以激發發射。然而,此技術之顯著限制為其係逐點檢驗技術。按高空間解析度(例如,小於晶粒大小之空間解析度)準確映射整個產品晶圓花費30分鐘至240分鐘,該時間視用以形成產品晶圓之基板大小而定。 Currently, in order to estimate or predict the LED emission wavelength λ E , the substrate is inspected by photoluminescence techniques in which a short wavelength source (typically 248 nm) is incident on the multiple quantum well region to excite the emission. However, this technology is significantly limited by its point-by-point inspection technique. Accurate mapping of the entire product wafer by high spatial resolution (eg, less than the spatial resolution of the grain size) takes from 30 minutes to 240 minutes, depending on the substrate size used to form the product wafer.
此技術之再一限制為來自光致發光之發射波長通常不同於在電刺激期間來自LED之發射波長。據信此差異之根源來自LED在光致發光檢驗與最終產品之間所經歷的額外製造步驟。通常,在光致發光發射波長與電刺激之LED發射波長之間存在在生產中預先量測的偏差。此接著用作製程監視器。 A further limitation of this technique is that the emission wavelength from photoluminescence is typically different from the emission wavelength from the LED during electrical stimulation. The root cause of this difference is believed to be the additional manufacturing steps experienced by the LED between the photoluminescence inspection and the final product. Typically, there is a pre-measured deviation in production between the photoluminescence emission wavelength and the LED emission wavelength of the electrical stimulus. This is then used as a process monitor.
形成於產品晶圓10上的裝置結構40中之裝置層應力S(x,y)之量與產品晶圓溫度T(x,y)之歷史(亦即,T(x,y,t),其中t為時間)直接有關。根本上,在沈積製程期間產品晶圓溫度之差(亦即,非均勻加熱)導致經沈積之GaN層(且詳言之,多量子井層) 中之厚度變化。在沈積後,且當使基板返回至室溫時,組成裝置結構40的構成材料之熱膨脹係數之差導致在熱循環期間裝置結構40相對於基板20之相對膨脹或收縮。非均勻加熱導致非均勻的裝置層應力及非均勻的發射波長(λE)。 The amount of device layer stress S(x, y) in the device structure 40 formed on the product wafer 10 and the history of the product wafer temperature T(x, y) (ie, T(x, y, t ), Where t is time) directly related. Fundamentally, the difference in product wafer temperature during the deposition process (i.e., non-uniform heating) results in a thickness variation in the deposited GaN layer (and in particular, the multi-quantum well layer). After deposition, and when the substrate is returned to room temperature, the difference in thermal expansion coefficients of the constituent materials of the constituent device structures 40 results in relative expansion or contraction of the device structure 40 relative to the substrate 20 during thermal cycling. Non-uniform heating results in non-uniform device layer stress and non-uniform emission wavelength (λ E ).
此相對膨脹或收縮引起形成於產品晶圓10上的裝置結構40中之應力,使得賦予產品晶圓之熱能部分地作為機械能儲存於裝置層30中。在沈積期間產品晶圓溫度T(x,y)之不均勻性(亦即,變化)導致層厚度及最終裝置層應力S(x,y)之不均勻性(變化)。具有均勻但不同溫度T(x,y)之產品晶圓10將具有均勻但不同的裝置層應力S(x,y)。 This relative expansion or contraction causes stress in the device structure 40 formed on the product wafer 10 such that thermal energy imparted to the product wafer is partially stored as mechanical energy in the device layer 30. The non-uniformity (i.e., variation) of the product wafer temperature T(x, y) during deposition results in layer thickness and non-uniformity (change) in the final device layer stress S(x, y). A product wafer 10 having uniform but different temperatures T(x, y) will have a uniform but different device layer stress S(x, y).
可經由基板曲率之改變△C(x,y)來監視裝置層應力S(x,y)。最普通的應力計量系統依賴於對產品晶圓形狀之改變的量測來計算裝置層應力。由產品晶圓10支撐的裝置結構40中之裝置應力S(x,y)係使用Stoney公式自曲率改變△C(x,y)計算:S(x,y)={MShS 2/6hF}△C(x,y) 等式1 The device layer stress S(x, y) can be monitored via the change in the curvature of the substrate ΔC(x, y). The most common stress metering systems rely on measurements of changes in the shape of the product wafer to calculate device layer stress. The device stress S(x, y) in the device structure 40 supported by the product wafer 10 is calculated using the Stoney formula from the curvature change ΔC(x, y): S(x, y) = {M S h S 2 / 6h F }△C(x,y) Equation 1
其中M為雙軸向模數,h為厚度,且下標「F」代表沈積之薄膜(在此實例中為GaN),且下標「s」代表基板(在此實例中為藍寶石或矽)。在晶圓上的C(x,y)之變化指示非均勻的裝置層應力S。 Where M is the biaxial modulus, h is the thickness, and the subscript "F" represents the deposited film (GaN in this example), and the subscript "s" represents the substrate (sapphire or germanium in this example). . The change in C(x, y) on the wafer indicates a non-uniform device layer stress S.
在知曉可歸因於薄膜(亦即,裝置層30)與下伏基板20之間的溫度及熱膨脹係數(α)不匹配而引起裝置層應力S後,吾人可導 出針對裝置層應力S及曲率C之以下表達式:S(x,y)=Mfεm(T)=Mf(αf-αs)△T 等式2 After knowing that the temperature and thermal expansion coefficient (α) mismatch between the film (ie, the device layer 30) and the underlying substrate 20 does not match to cause the device layer stress S, we can derive the stress S and curvature for the device layer. The following expression of C: S(x, y) = M f ε m (T) = M f (α f - α s ) ΔT Equation 2
C(x,y)={6Mfhf/Mshs 2}(αf-αs)△T 等式3 C(x,y)={6M f h f /M s h s 2 }(α f -α s )ΔT Equation 3
其中εm為薄膜與基板之間的不匹配或不擬合應變,△T為與無應力溫度To(亦即,薄膜與基板匹配時之溫度)之溫差。 Wherein ε m is the mismatch or misfit strain between the membrane and the substrate, △ T is the stress-free temperature T o (i.e., the substrate temperature during the film match) the temperature difference.
以上等式展示曲率變化△C(x,y)如何與沈積溫度之改變有關。因此,自此等表達式,吾人可使產品晶圓曲率與溫度有關,溫度直接與LED之發射波長λE有關。 The above equation shows how the curvature change ΔC(x, y) is related to the change in deposition temperature. Therefore, from these expressions, we can make the product wafer curvature temperature-dependent, and the temperature is directly related to the emission wavelength λ E of the LED.
以上提供之等式係基於關於應力及變形狀態、裝置結構之幾何形狀及構成材料之熱機械性質的特定假定。可針對具有任意屬性之薄膜/基板系統產生此等等式之更複雜形式或版本。然而,對於任一特定裝置/基板系統,可沿著本文中闡明之思路產生適當的關係式以使基板曲率變化與溫度變化與發射波長變化有關。 The equations provided above are based on specific assumptions regarding the stress and deformation state, the geometry of the device structure, and the thermomechanical properties of the constituent materials. A more complex form or version of this equation can be produced for a film/substrate system with any attributes. However, for any particular device/substrate system, an appropriate relationship can be created along the lines set forth herein to correlate substrate curvature changes with temperature changes and emission wavelength variations.
本發明之一態樣使至少一產品晶圓特性(諸如,產品晶圓應力(亦即,應力張量之一或多個分量)及曲率)與至少一LED效能特性(諸如,發射功率、效率、波長、光譜頻寬及類似者)相關。在一實例中,此藉由按經驗確立LED之至少一量測之效能特性與至少一產品晶圓特性之間的關係來實現。在一實例中,此可藉由對照用以形成產品晶圓之個別製程步驟評估自產品晶圓獲得的LED之至少一效能特性來實現。此亦可藉由對照用以形成產品晶圓之多個製程步驟評估至少一LED效能特性來實現。 One aspect of the present invention enables at least one product wafer characteristic (such as product wafer stress (i.e., one or more components of stress tensor) and curvature) and at least one LED performance characteristic (such as transmit power, efficiency) , wavelength, spectral bandwidth, and the like) are related. In one example, this is accomplished by empirically establishing a relationship between at least one measured performance characteristic of the LED and at least one product wafer characteristic. In one example, this can be accomplished by evaluating at least one performance characteristic of the LEDs obtained from the product wafer against individual process steps used to form the product wafer. This can also be accomplished by evaluating at least one LED performance characteristic against a plurality of process steps used to form the product wafer.
因此,本發明之一態樣包括一種使用產品晶圓應力及產品晶圓曲率中之至少一者作為製程監視器來執行品質控制之方法,該品質控制分選或精選產品晶圓之個別晶粒的效能。該方法亦可包括監視在產品晶圓形成期間之沈積特性,及執行製程最佳化。該方法可進一步包括匹配同一類型之製程工具中之兩者或兩者以上之集合的效能,使得當在不同製程工具上形成時產品晶圓匹配且因此其LED晶粒亦匹配。亦即,藉由在匹配集合中之不同製程工具形成的產品晶圓比製程工具不匹配之情況下所形成的產品晶圓相似。 Accordingly, one aspect of the present invention includes a method of performing quality control using at least one of product wafer stress and product wafer curvature as a process monitor for sorting or selecting individual wafers of a product wafer Performance. The method can also include monitoring deposition characteristics during product wafer formation and performing process optimization. The method can further include matching the performance of a set of two or more of the same type of process tool such that the product wafers match when formed on different process tools and thus their LED dies also match. That is, the product wafer formed by the different process tools in the matching set is similar to the product wafer formed without the process tool.
圖8A至圖8C為示意性說明曲率C(x,y)、裝置層應力S(x,y)及實際發射波長λE(x,y)之實例等值線的一實例產品晶圓10之平面圖。本發明之一態樣涉及藉由量測產品晶圓曲率C(x,y)來判定裝置層應力S(x,y),及接著使用判定之裝置層應力S(x,y)預測隨產品晶圓10之對應裝置結構40之位置(x,y)而變的所得(分開之)晶粒42的實際發射波長λE。 8A-8C are an example product wafer 10 illustrating an example contour of curvature C(x, y), device layer stress S(x, y), and actual emission wavelength λ E (x, y). Floor plan. One aspect of the invention relates to determining the device layer stress S(x, y) by measuring the product wafer curvature C(x, y), and then using the determined device layer stress S(x, y) to predict the product The actual emission wavelength λ E of the resulting (separated) die 42 of the wafer 10 corresponding to the location (x, y) of the device structure 40.
在圖8C中,展示一特定裝置結構40,其具有相對於一參考位置(例如,產品晶圓之中心)量測之位置(x i ,y j )。裝置結構40之陣列32之特寫插圖按1 nm增量展示實際發射波長λE之較詳細的(亦即,緊密間隔)等值線λE。在一實例中,可預測1 nm之發射波長變化(偏移)δλE。 In Figure 8C, a particular device structure 40 is shown having a position (x i , y j ) measured relative to a reference location (e.g., the center of the product wafer). Close-up device 32 configuration of the array 40 by 1 nm increments illustration shows actual emission wavelength λ E of more detailed (i.e., closely spaced) contour λ E. In one example, an emission wavelength change (offset) δλ E of 1 nm can be predicted.
圖8D為假想產品晶圓10之平面圖,其展示預測之發射波長 λEP的實例2 nm等值線,其中產品晶圓10具有凹形或碗形曲率C(x,y)。假定具有+/- 1 nm之發射波長變化容限δλ的λED=456 nm之所要發射波長,圖8D之預測波長等值線允許吾人分割產品晶圓10且在最終發光裝置50中僅使用來自具有在按實線展示的455 nm及457 nm預測波長等值線內(亦即,在發射波長變化容限δλ內)的(x,y)位置的裝置結構40之彼等晶粒42。因此,在一實例中,第一數目個LED結構40在455 nm及457 nm等值線之範圍內,且第二數目個LED結構40在此等等值線範圍之外。此類型的基於選定規格(此處,發射波長)的對LED結構40之精選可用以將所得LED晶粒42安排用於第一及第二應用或第一及第二類型之LED裝置。 Figure 8D is a plan view of a hypothetical product wafer 10 showing an example 2 nm contour of the predicted emission wavelength λ EP with the product wafer 10 having a concave or bowl-shaped curvature C(x, y). Assuming a desired emission wavelength of λ ED = 456 nm with an emission wavelength variation tolerance δλ of +/- 1 nm, the predicted wavelength contour of Figure 8D allows us to split the product wafer 10 and use only the final illumination device 50 from There are crystal grains 42 of the device structure 40 at the (x, y) position within the 455 nm and 457 nm predicted wavelength contours shown in solid lines (i.e., within the emission wavelength variation tolerance δλ). Thus, in one example, the first number of LED structures 40 are in the range of 455 nm and 457 nm contours, and the second number of LED structures 40 are outside of the contour range. This type of selection of LED structures 40 based on selected specifications (here, emission wavelengths) can be used to arrange the resulting LED dies 42 for the first and second applications or the first and second types of LED devices.
在此點,可估計在接受波長變化(亦即,在此實例中,δλ=+/- 1 nm)內的晶粒42之數目。此外,可估計稍處於此窗之外但仍適用於「變色」應用的晶粒42之數目。另外,亦可估計處於任一適用範圍外且因此不具有內在價值的晶粒42之數目。根據每一波長變化範圍內的晶粒42之數目,且在知曉每一波長變化範圍的晶粒42之價值後,可判定產品晶圓10之內在價值。此允許LED製造商判定是否有充分的理由繼續處理特定產品晶圓10。舉例而言,若晶粒陣列在具有任一價值的波長範圍之外,則幾乎沒有理由繼續處理晶圓10及招致額外花費。 At this point, the number of grains 42 within the acceptance wavelength change (i.e., δλ = +/- 1 nm in this example) can be estimated. In addition, the number of dies 42 that are slightly outside the window but still suitable for "discoloration" applications can be estimated. In addition, the number of dies 42 that are outside of any applicable range and therefore have no intrinsic value can also be estimated. The intrinsic value of the product wafer 10 can be determined based on the number of dies 42 in each wavelength variation range and after knowing the value of the dies 42 for each wavelength variation range. This allows the LED manufacturer to determine if there is a good reason to continue processing the particular product wafer 10. For example, if the die array is outside of a wavelength range of any value, there is little reason to continue processing the wafer 10 and incur additional costs.
總之,在LED形成期間的沈積溫度之改變導致LED之發射 波長λE的波長偏移。此等相同的溫度改變導致沈積薄膜中的應力改變,此導致晶圓曲率之改變。因此,經由以上等式,晶圓曲率C之改變可與波長偏移有關。 In summary, a change in the deposition temperature during LED formation results in a wavelength shift of the emission wavelength λ E of the LED. These same temperature changes result in a change in stress in the deposited film, which results in a change in wafer curvature. Thus, via the above equation, the change in wafer curvature C can be related to the wavelength shift.
實務上,可能難以知曉在MOCVD製程期間使用的高溫下各種各樣材料的材料常數(諸如,熱膨脹係數α及雙軸向模數M)之確切值。舉例而言,MOCVD製程中之典型溫度常為大約1000℃。分析地使以上等式與實際LED波長偏移相聯繫需要精確知曉此等材料常數及基板20之溫度歷史。此資訊可能不可得到。 In practice, it may be difficult to know the exact values of the material constants (such as the coefficient of thermal expansion α and the biaxial modulus M) of various materials at high temperatures used during the MOCVD process. For example, typical temperatures in MOCVD processes are often about 1000 °C. Analytically correlating the above equations to the actual LED wavelength shift requires accurate knowledge of these material constants and the temperature history of the substrate 20. This information may not be available.
因此按經驗獲得必要資料,且藉由精確量測在一或多個測試產品晶圓10上之所有點的曲率C及量測自產品晶圓10獲得的LED晶粒42之LED發射波長λE而產生針對實際波長偏移之查找表或相關曲線可能更方便。此方法允許吾人使量測之基板曲率C與實際裝置資料相關,及將基板曲率用作隨後大量LED製造的製程控制及檢驗監視器。 The necessary information is thus obtained empirically, and by accurately measuring the curvature C of all points on one or more test product wafers 10 and measuring the LED emission wavelength λ E of the LED dies 42 obtained from the product wafer 10. It may be more convenient to generate a lookup table or correlation curve for the actual wavelength offset. This method allows us to correlate the measured substrate curvature C with the actual device data and to use the substrate curvature as a process control and inspection monitor for subsequent mass LED fabrication.
相對於目前使用之光致發光技術而言,使用晶圓曲率C監視發射波長λE及發射均勻性之主要優勢在於可在非常短的時間內按非常高的空間頻率來量測晶圓曲率。相干梯度感測系統(以下描述)可易於藉由幾百微米(其低於1 mm之典型晶粒大小)之空間取樣來對基板取樣,且可在大致1分鐘內檢驗(量測)200 mm晶圓。比較起來,使用光致發光系統達成關於200 mm晶圓之類似空間資 訊將花費若干小時。 The main advantage of using the wafer curvature C to monitor the emission wavelength λ E and emission uniformity over the currently used photoluminescence technology is that the wafer curvature can be measured at very high spatial frequencies in a very short time. A coherent gradient sensing system (described below) can easily sample a substrate by spatial sampling of a few hundred microns (which is typically less than 1 mm) and can be inspected (measured) by approximately 200 mm in approximately 1 minute. Wafer. In comparison, it would take several hours to achieve similar spatial information on a 200 mm wafer using a photoluminescent system.
圖9為可用以量測產品晶圓10之曲率C(x,y)的一實例相干梯度感測(CGS)系統200之示意圖。關於CGS感測之工作方式的細節描述於美國專利第6,031,611號('611專利)中,該專利被以引用的方式併入本文中。圖9係基於'611專利之圖1。 9 is a schematic diagram of an example coherent gradient sensing (CGS) system 200 that can be used to measure the curvature C(x,y) of a product wafer 10. Details of the manner of operation of the CGS sensing are described in U.S. Patent No. 6,031,611 (the ' 611 patent) which is incorporated herein by reference. Figure 9 is based on Figure 1 of the '611 patent.
CGS系統200沿著軸線A1包括一數位相機210、一濾光透鏡224(例如,與透鏡相結合之濾光器,如在'611專利中所論述且在其中之圖1中所展示)、軸向間隔開之第一光柵G1及第二光柵G2、一分光鏡230及一晶圓載物台240。CGS系統200亦包括沿著與軸線A1在分光鏡230處相交之光軸A2配置之一雷射250。CGS系統200亦包括可操作地連接至數位相機210且連接至雷射250之一控制器或信號處理器260。一實例信號處理器260為或包括具有處理器262及電腦可讀媒體(「記憶體」)264之電腦,該處理器及電腦可讀媒體係經由記錄於其上之指令加以組態以控制CGS系統200之操作,以根據在'611專利中所描述之方法執行產品晶圓曲率C(x,y)之量測。 The CGS system 200 includes a digital camera 210, a filter lens 224 along the axis A1 (e.g., a filter coupled to the lens, as discussed in the '611 patent and shown in Figure 1 therein), the shaft The first grating G1 and the second grating G2, a beam splitter 230, and a wafer stage 240 are spaced apart. The CGS system 200 also includes a laser 250 disposed along an optical axis A2 that intersects the axis A1 at the beam splitter 230. The CGS system 200 also includes a controller or signal processor 260 that is operatively coupled to the digital camera 210 and to one of the lasers 250. An example signal processor 260 is or includes a computer having a processor 262 and a computer readable medium ("memory") 264, the processor and computer readable medium being configured to control CGS via instructions recorded thereon The operation of system 200 is performed to perform a measurement of the product wafer curvature C(x, y) according to the method described in the '611 patent.
在操作中,雷射250產生由分光鏡230引至產品晶圓10的經準直之雷射束252。經準直之雷射束自產品晶圓10(且詳言之,自裝置層30)反射,作為經反射之光252R,該經反射之光252R向上行進穿過分光鏡230且穿過光柵G1及G2。兩個光柵G1及G2間隔開且以其他方式經組態以剪切經準直之雷射束。接著使 用濾光透鏡224使穿過光柵G1及G2之光聚焦至數位相機210上。 In operation, laser 250 produces a collimated laser beam 252 that is directed by beam splitter 230 to product wafer 10. The collimated laser beam is reflected from the product wafer 10 (and, in particular, from the device layer 30) as reflected light 252R, which travels upward through the beam splitter 230 and through the grating G1 and G2. The two gratings G1 and G2 are spaced apart and otherwise configured to shear the collimated laser beam. Then make The light passing through the gratings G1 and G2 is focused onto the digital camera 210 by a filter lens 224.
剪切及濾光過程在數位相機210處產生為產品晶圓10上之恆定表面斜度之等值線的條紋。因此,使用兩組正交的干涉圖來特性化表面斜度,其可經數值積分以重新建構基板構形或可經數值微分以獲得產品晶圓曲率C(x,y)。諸如'611專利之圖6中所展示的用於CGS系統之兩相機組態亦可用以促進擷取該兩組正交之干涉圖。 The shearing and filtering process produces stripes at the digital camera 210 that are contours of a constant surface slope on the product wafer 10. Thus, two sets of orthogonal interferograms are used to characterize the surface slope, which can be numerically integrated to reconstruct the substrate configuration or can be numerically differentiated to obtain the product wafer curvature C(x,y). Two camera configurations for the CGS system, such as shown in Figure 6 of the '611 patent, can also be used to facilitate the acquisition of the two sets of orthogonal interferograms.
接著使用(例如)如在控制器260中進行的在'611專利中描述之方法自干涉條紋圖案產生曲率映射(亦即,產品晶圓曲率C(x,y))。在一實例中,產品晶圓10的量測之曲率C(x,y)具有大約100微米至300微米之空間解析度。因此,對於具有大約1 mm之尺寸d(見圖3)的裝置結構40,每裝置可存在至少一曲率資料點,且在一些情況下,每裝置(晶粒)可存在多個資料點。在一實例中,本文中揭示之方法包括在實質上等於或小於裝置結構40之尺寸d之尺寸上判定產品晶圓中的應力S(x,y)之空間變化。 A curvature map (i.e., product wafer curvature C(x, y)) is then generated from the interference fringe pattern using, for example, the method described in the '611 patent as performed in controller 260. In one example, the measured curvature C(x,y) of the product wafer 10 has a spatial resolution of between about 100 microns and 300 microns. Thus, for a device structure 40 having a dimension d (see FIG. 3) of about 1 mm, there may be at least one curvature data point per device, and in some cases there may be multiple data points per device (grain). In one example, the method disclosed herein includes determining a spatial variation in stress S(x, y) in a product wafer at a size substantially equal to or less than the dimension d of the device structure 40.
在一實例中,在處理基板以形成產品晶圓10之前量測基板20之曲率C0(x,y)。此允許計算曲率改變△C(x,y)=C(x,y)-C0(x,y)。 In one example, the curvature C 0 (x, y) of the substrate 20 is measured prior to processing the substrate to form the product wafer 10. This allows the calculation of the curvature change ΔC(x, y) = C(x, y) - C 0 (x, y).
一旦量測了基板曲率C0(x,y)及產品晶圓曲率C(x,y)且計算了曲率改變△C(x,y),則可判定裝置層應力S(x,y)。在一實例 中,此係使用使裝置層應力S與曲率改變△C有關之Stoney等式(以上等式1)來實現。 Once the substrate curvature C 0 (x, y) and the product wafer curvature C(x, y) are measured and the curvature change ΔC(x, y) is calculated, the device layer stress S(x, y) can be determined. In one example, this is accomplished using the Stoney equation (Equation 1 above) relating the device layer stress S to the curvature change ΔC.
對於多數產品晶圓10而言,曲率改變△C(x,y)在晶圓上變化且亦隨定向而變化,此暗示非均勻的裝置層應力S(x,y)之存在。或者,若在各別溫度下之材料性質並非已知,則吾人可量測取樣基板(晶圓)上之波長偏移δλ對量測之曲率C,且將此等量測聯繫在一起,用於產品晶圓10之未來量測。 For most product wafers 10, the curvature change ΔC(x, y) varies across the wafer and also varies with orientation, suggesting the presence of non-uniform device layer stress S(x, y). Or, if the material properties at different temperatures are not known, we can measure the wavelength offset δλ on the sampling substrate (wafer) versus the measured curvature C, and link these measurements together. Future measurements on product wafer 10.
可使用其他方法來進行允許判定C(x,y)之量測。此等方法包括(例如)輪廓測繪、干涉量測法、電容量規及雷射束偏轉。同樣地,可藉由使用(例如)X射線繞射及拉曼(Raman)光譜法量測晶格之畸變來判定裝置層應力S(x,y)。 Other methods can be used to perform the measurement of the allowable decision C(x, y). Such methods include, for example, contour mapping, interference measurements, capacitance gauges, and laser beam deflection. Similarly, the device layer stress S(x, y) can be determined by measuring the distortion of the crystal lattice using, for example, X-ray diffraction and Raman spectroscopy.
因此,本發明之方法之一態樣包括以下。 Thus, one aspect of the method of the present invention includes the following.
1.在處理前,例如,在進行MOCVD前,量測基板20之形狀(曲率)C0(x,y)。 1. Before Before treatment, e.g., during the MOCVD, the shape (curvature) of the measurement substrate 20 C 0 (x, y).
2.在處理後,量測產品晶圓10之形狀C(x,y)。 2. After processing, measure the shape C(x, y) of the product wafer 10.
3.計算△C(x,y)=C(x,y)-C0(x,y)以判定由處理基板20以產生產品晶圓誘發的與產品晶圓10相關聯之曲率改變△C。 3. Calculate ΔC(x, y) = C(x, y) - C 0 (x, y) to determine the curvature change associated with the product wafer 10 induced by the processing substrate 20 to produce the product wafer ΔC .
4.使用Stoney公式或有關公式(例如,布氏等式(Blake's Equation))計算產品晶圓中之裝置層應力S(x,y)以基於△C(x,y)計算產品晶圓中的製程誘發之裝置層應力S(x,y)。 4. Calculate the device layer stress S(x, y) in the product wafer using the Stoney formula or related formula (eg, Blake's Equation) to calculate the product wafer based on ΔC(x, y) Process induced device layer stress S(x, y).
5.使位於位置(x i,y j )處之裝置結構40與裝置層應力S(x i,y j ) 相關聯。 5. Associate the device structure 40 at the location (x i , y j ) with the device layer stress S(x i , y j ).
6.使裝置層應力值S(x i,y j )與發射波長λE(x i,y j )相關聯,其接著允許量測產品晶圓曲率以預測當產品晶圓被分割時形成LED晶粒的LED結構40之發射波長。 6. Associate the device layer stress value S(x i , y j ) with the emission wavelength λ E (x i , y j ), which in turn allows measurement of the product wafer curvature to predict the formation of the LED when the product wafer is segmented The emission wavelength of the LED structure 40 of the die.
以上步驟6要求針對給定類型之製程及正被生產之裝置結構40確立實際發射波長λE、曲率改變△C與裝置層應力S(x,y)之改變之間的關係。若所有材料性質為熟知的且若溫度與沈積速率之間的關係為熟知的,則可進行此。如上文所論述,此等量可能並不熟知,且有必要按經驗產生資料以使量測之曲率變化與發射波長變化相關。 The above step 6 requires establishing a relationship between the actual emission wavelength λ E , the curvature change ΔC and the change in the device layer stress S(x, y) for a given type of process and the device structure 40 being produced. This can be done if all material properties are well known and if the relationship between temperature and deposition rate is well known. As discussed above, such quantities may not be well known and it is necessary to empirically generate data to correlate the change in curvature of the measurement to the change in emission wavelength.
在一實例中,此經驗「指紋識別」過程可如下進行:1.對於用於形成裝置結構40之一特定過程,針對一或多個測試產品晶圓10完成步驟1至4;2.量測自測試產品晶圓10獲得的LED晶粒之隨裝置結構位置(x,y)而變的實際發射波長λE以確立λE(x,y);及3.判定裝置層應力S(x,y)與實際發射波長λE(x,y)之間的關係。 In one example, the empirical "fingerprinting" process can be performed as follows: 1. For a particular process for forming device structure 40, steps 1 through 4 are performed for one or more test product wafers; 2. Measurement The actual emission wavelength λ E of the LED die obtained from the test product wafer 10 as a function of the device structure position (x, y) is established to establish λ E (x, y); and 3. the device layer stress S (x, y) The relationship between the actual emission wavelength λ E (x, y).
本發明之方法亦包括執行對產品晶圓10之製程監視及製程控制以判定(預測)當產品晶圓10經分割時LED晶粒42將產生的實際發射波長λE。可針對給定產品晶圓及針對同一製程(亦即,相同的裝置結構)在不同產品晶圓之間進行此步驟。使用本文中揭 示之方法特性化的選定LED晶粒42可接著用於諸如圖3中所展示的選定類型之LED裝置50中。 The method of the present invention also includes performing process monitoring and process control of the product wafer 10 to determine (predict) the actual emission wavelength λ E that the LED die 42 will produce when the product wafer 10 is segmented. This step can be performed between different product wafers for a given product wafer and for the same process (ie, the same device structure). Selected LED dies 42 characterized using the methods disclosed herein can then be used in a selected type of LED device 50 such as that shown in FIG.
本發明之方法亦包括藉由調整在形成產品晶圓10之過程中使用的製程變數中之至少一者來執行用於形成裝置結構40之製程最佳化。此包括(例如):1.確立製程變數(例如,溫度、溫度均勻性、氣體分壓、氣體分壓均勻性、流動速率、流動速率均勻性、時間)與製程誘發之應力特性(例如,平均應力及應力均勻性)之間的關係;及2.修改製程變數中之至少一者以使導致所要的裝置特性的製程之應力特性最佳化,該等所要的裝置特性諸如,發射波長儘可能地靠近所要的發射波長。 The method of the present invention also includes performing process optimization for forming device structure 40 by adjusting at least one of process variables used in forming product wafer 10. This includes, for example: 1. Establishing process variables (eg, temperature, temperature uniformity, gas partial pressure, gas partial pressure uniformity, flow rate, flow rate uniformity, time) and process induced stress characteristics (eg, average The relationship between stress and stress uniformity; and 2. modifying at least one of the process variables to optimize the stress characteristics of the process leading to the desired device characteristics, such as the emission wavelength as much as possible The ground is close to the desired emission wavelength.
旨在製程最佳化的本發明之方法亦包括下列步驟: The method of the present invention, which is intended to optimize the process, also includes the following steps:
1.確立與用以進行同一製程之不同處理工具(例如,不同MOCVD反應器系統)相關聯的應力特性。 1. Establish stress characteristics associated with different processing tools (eg, different MOCVD reactor systems) used to perform the same process.
2.識別導致最不合乎需要之應力特性(亦即,導致最大量的裝置效能變化(例如,實際發射波長之最大變化)之應力特性)的特定處理工具。 2. Identify specific processing tools that result in the most undesirable stress characteristics (i.e., the stress characteristics that result in the greatest amount of device performance variation (e.g., the largest change in actual emission wavelength).
3.識別影響應力特性的諸如硬體或控制設定、調整等之處理工具參數(亦即,晶圓溫度、晶粒溫度均勻性、氣體分壓、氣體分壓均勻性、氣體流動速度、氣體流動速率均勻性等)。 3. Identify processing tool parameters such as hardware or control settings, adjustments, etc. that affect stress characteristics (ie, wafer temperature, grain temperature uniformity, gas partial pressure, gas partial pressure uniformity, gas flow rate, gas flow) Rate uniformity, etc.).
4.調整處理工具參數以獲得減小的發射波長λE之變化,且 在一特定實例中,使LED晶粒之發射波長λE之變化最小化。 4. Adjusting the processing tool parameters to obtain a change in the reduced emission wavelength λ E , and in a particular example, minimizing variations in the emission wavelength λ E of the LED dies.
圖10為闡明基於產品晶圓及用以形成產品晶圓之基板的曲率量測而預測自產品晶圓10形成之LED晶粒42的實際發射波長λE之一實例方法之流程圖300。 10 is a flow chart 300 illustrating an example method for predicting an actual emission wavelength λ E of an LED die 42 formed from a product wafer 10 based on a curvature measurement of a product wafer and a substrate used to form the product wafer.
流程圖300包括確立裝置層應力S(x,y)與自產品晶圓10上之裝置結構40形成的晶粒42之實際發射波長λE(x,y)之間的關係之第一步驟302。 Flowchart 300 includes a first step 302 of establishing a relationship between device layer stress S(x, y) and the actual emission wavelength λ E (x, y) of die 42 formed from device structure 40 on product wafer 10. .
流程圖300包括第二步驟304,其包括基於基板曲率量測C0(x,y)(如上文所述)量測產品晶圓10之曲率改變△C(x,y)。 Flowchart 300 includes a second step 304 that measures the curvature change ΔC(x, y) of product wafer 10 based on substrate curvature measurement C 0 (x, y) (as described above).
流程圖300包括使用(例如)Stoney等式基於量測之曲率改變△C計算產品晶圓10之裝置層應力S(x,y)之第三步驟306。 Flowchart 300 includes a third step 306 of calculating the device layer stress S(x, y) of the product wafer 10 based on the measured curvature change ΔC using, for example, the Stoney equation.
流程圖300包括使產品晶圓10上的藉以形成晶粒42之(x,y)裝置結構40與計算之裝置層應力S(x,y)相關聯之第四步驟308。 Flowchart 300 includes a fourth step 308 of correlating the (x,y) device structure 40 on the product wafer 10 to form the die 42 with the calculated device layer stress S(x,y).
流程圖300包括基於在步驟302中確立之裝置層應力值S(x,y)使實際發射波長λE與各種晶粒42相關聯之第五步驟310。 Flowchart 300 includes a fifth step 310 of associating actual emission wavelengths λ E with various dies 42 based on the device layer stress values S(x, y) established in step 302.
流程圖300包括調整至少一製程變數以減小晶粒42之發射波長λE的變化之第六步驟312。 Flowchart 300 includes a sixth step 312 of adjusting at least one process variable to reduce the change in emission wavelength λ E of die 42.
在本文中揭示之方法之另一實例中,可在產品晶圓處理之完成的不同階段(步驟)進行產品晶圓曲率量測。此可提供關於產品晶圓曲率針對每一製程步驟改變之方式的洞見。 In another example of the methods disclosed herein, product wafer curvature measurements can be performed at different stages (steps) of completion of product wafer processing. This provides insight into how the product wafer curvature changes for each process step.
又,如上文所論述,流程圖300可包括作為步驟302之一部 分的子步驟,其為自測試產品晶圓10按經驗獲得必要資料以藉由精確量測晶圓之樣本(集合)上的曲率C及稍後量測其LED發射波長λE而產生針對實際波長偏移之查找表或相關曲線以使量測之基板曲率C與實際裝置資料相關。此允許將產品晶圓曲率量測用作用於隨後大量LED裝置製造之製程控制及檢驗監視器。 Again, as discussed above, flowchart 300 can include a sub-step as part of step 302 that empirically obtains the necessary data from test product wafer 10 to accurately measure the curvature on the sample (set) of the wafer C and later measuring its LED emission wavelength λ E generated wavelength shift of the actual correlation curve or lookup table so that the amount of the substrate measured curvature C means associated with the actual data. This allows the product wafer curvature measurement to be used as a process control and inspection monitor for subsequent mass LED device fabrication.
對於熟習此項技術者而言,在不偏離本發明之精神及範疇之情況下,對本發明進行各種修改及變化,其屬顯而易見。因此,希望本發明涵蓋本發明之修改及變化,只要其屬於隨附申請專利範圍及其等效物之範疇便可。 It will be apparent to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention cover the modifications and variations of the invention, as the scope of the appended claims and their equivalents.
10‧‧‧產品晶圓 10‧‧‧Product Wafer
20‧‧‧基板 20‧‧‧Substrate
21‧‧‧邊緣 21‧‧‧ edge
22‧‧‧頂表面 22‧‧‧ top surface
24‧‧‧底表面 24‧‧‧ bottom surface
30‧‧‧裝置層 30‧‧‧Device level
32‧‧‧陣列 32‧‧‧Array
40‧‧‧半導體發光裝置結構(「裝置結構」) 40‧‧‧Semiconductor light-emitting device structure ("device structure")
42‧‧‧晶粒 42‧‧‧ grain
50‧‧‧發光裝置/LED裝置 50‧‧‧Lighting device/LED device
52A‧‧‧陽極 52A‧‧‧Anode
52C‧‧‧陰極 52C‧‧‧ cathode
54‧‧‧內部 54‧‧‧Internal
56‧‧‧環氧樹脂透鏡殼 56‧‧‧Epoxy lens housing
58‧‧‧反射腔 58‧‧‧Reflection chamber
60‧‧‧線接合 60‧‧‧ wire bonding
62‧‧‧光 62‧‧‧Light
70‧‧‧晶座 70‧‧‧crystal seat
72‧‧‧頂表面 72‧‧‧ top surface
76‧‧‧開口 76‧‧‧ openings
78‧‧‧端緣 78‧‧‧Edge
90‧‧‧MOCVD反應器系統 90‧‧‧MOCVD reactor system
96‧‧‧MOCVD子系統 96‧‧‧MOCVD subsystem
100‧‧‧MOCVD腔室 100‧‧‧MOCVD chamber
104‧‧‧反應器內部 104‧‧‧Reactor inside
105‧‧‧箭頭 105‧‧‧ arrow
110‧‧‧控制器 110‧‧‧ Controller
200‧‧‧相干梯度感測(CGS)系統 200‧‧•Coherent Gradient Sensing (CGS) System
210‧‧‧數位相機 210‧‧‧Digital camera
224‧‧‧濾光透鏡 224‧‧‧ Filter lens
230‧‧‧分光鏡 230‧‧‧beam splitter
240‧‧‧晶圓載物台 240‧‧‧wafer stage
250‧‧‧雷射 250‧‧ ‧ laser
252‧‧‧經準直之雷射束 252‧‧‧ collimated laser beam
252R‧‧‧經反射之光 252R‧‧‧reflected light
260‧‧‧控制器或信號處理器 260‧‧‧Controller or signal processor
262‧‧‧處理器 262‧‧‧ processor
264‧‧‧電腦可讀媒體(「記憶體」) 264‧‧‧ Computer-readable media ("memory")
300‧‧‧流程圖 300‧‧‧ Flowchart
A1‧‧‧軸線 A1‧‧‧ axis
A2‧‧‧光軸 A2‧‧‧ optical axis
G1‧‧‧第一光柵 G1‧‧‧ first grating
G2‧‧‧第二光柵 G2‧‧‧second grating
圖1為在半導體發光裝置之形成中使用的一實例產品晶圓之平面圖,且圖2為其橫截面圖;圖3為展示將來自產品晶圓之晶粒併入至LED裝置結構內之方式的一實例LED裝置之透視圖;圖4展示支撐於晶座中的藍寶石基板之集合;圖5為晶座之一部分之特寫橫截面圖,其展示將基板支撐於晶座中之方式;圖6為用以在基板頂上形成裝置層以形成圖2之產品晶圓的MOCVD反應器系統之示意圖;圖7A至圖7D為說明等值線的產品晶圓之平面圖,該等等值線分別展示產品晶圓溫度T、裝置尺寸D、裝置層應力S及發射波長λE之變化;圖8A至圖8C為說明等值線的產品晶圓之平面圖,該等等值線分別展示產品晶圓曲率C、裝置層應力S及發射波長λE之變化;圖8D為類似於圖8C之產品晶圓且說明一展示了預測發射波長之實例的產品晶圓之平面圖,且其中457 nm及455 nm之等值線呈粗體,此係因為其表示具有456 nm +/- 1 nm之所要波長之裝置結構所在的邊界;圖9為在一實例中用以量測基板及產品晶圓曲率的一實例相干梯度感測(CGS)系統之示意圖;及 圖10為闡明基於產品晶圓之曲率量測預測來自產品晶圓的晶粒之發射波長之一實例方法之流程圖。 1 is a plan view of an example product wafer used in the formation of a semiconductor light emitting device, and FIG. 2 is a cross-sectional view thereof; FIG. 3 is a view showing a manner in which a die from a product wafer is incorporated into a structure of an LED device. Figure 4 shows a collection of sapphire substrates supported in a crystal holder; Figure 5 is a close-up cross-sectional view of a portion of the crystal holder showing the manner in which the substrate is supported in the crystal holder; Figure 6 A schematic diagram of an MOCVD reactor system for forming a device layer on top of a substrate to form the product wafer of FIG. 2; FIGS. 7A-7D are plan views illustrating product lines of the contours, respectively, showing the product Variations of wafer temperature T, device size D, device layer stress S, and emission wavelength λ E ; FIGS. 8A-8C are plan views illustrating product lines of contours showing product wafer curvature C, respectively , device layer stress S and emission wavelength λ E change; FIG. 8D is a product wafer similar to FIG. 8C and illustrates a plan view of a product wafer showing an example of a predicted emission wavelength, and wherein 457 nm and 455 nm are equal. The value line is bold, this is because It represents the boundary of the device structure with the desired wavelength of 456 nm +/- 1 nm; Figure 9 is a schematic diagram of an example coherent gradient sensing (CGS) system for measuring the curvature of the substrate and product wafer in one example. And Figure 10 is a flow chart illustrating an example method for predicting the emission wavelength of a die from a product wafer based on the curvature measurement of the product wafer.
為了參考之原因,在一些圖中展示笛卡爾(Cartesian)座標,且該等座標並不意欲作為關於定向或組態之限制。 For reference reasons, Cartesian coordinates are shown in some figures, and such coordinates are not intended to be limiting as to orientation or configuration.
10‧‧‧產品晶圓 10‧‧‧Product Wafer
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