TWI519802B - A method of taking circuit information, a method of taking non-circuit area information and a method of detecting a circuit defect utilizing the aforementioned method - Google Patents

Description

Line information acquisition method, non-line area information acquisition method and line missing using the foregoing method Trap detection method

The invention relates to a method for detecting or measuring a circuit on a substrate such as a printed circuit board or a TFT panel, and more particularly to using a skeleton to extract from a circuit image taken from the substrate for line defect detection or other applications. Methods.

According to the conventional printed circuit board, the integrated circuit manufacturing method is formed by depositing a conductor pattern on a printed circuit board. In recent years, the development of the printed circuit board technology has made the effective circuit layout space reach the limit, for example, the circuit board is limited to the circuit board. The optimal density planning (increasing number of devices per square centimeter), the thin line and space planning on the board layout, and the increase of the pitch-density grid array device, etc., therefore, the conductor pattern formed on the printed circuit board must be relatively miniaturized and the most planned. The layout density is good, so it is easy to make the circuit on the printed circuit board produce defect status in the process. Therefore, it is often necessary to further perform line detection and testing. However, with the continuous improvement of production technology, the density and diversity of printed circuit boards are rapidly increasing. It is impossible to accurately find the defects on the HDI board and the IC substrate by the naked eye inspection, so the automatic machine vision inspection method, such as Automated Optical Inspection (AOI) or automatic image detection technology (AVI) It is quite common to detect line defects on printed circuit boards.

Such image recognition-based line defect detection methods have been available in various technologies, such as Taiwan I401430, 550391, 519571, 201339594, I264793, I244359, 200540411, I240223, 200949241, I412739, I435052, I292031, 201326739. Despite this, there are still technical cases that need to be updated for this type of testing method for the industry to use.

The invention provides a line information acquisition method based on image recognition technology, a non-line area information acquisition method and a line defect detection method using the foregoing method, which are used for extracting line information from circuit images captured from a substrate. (such as the line width or the color gradation of the line itself) and / or non-line area information, and use the information obtained to perform various defect detection procedures on the substrate, or you can use the information obtained to establish the foregoing The threshold value required for the analysis and judgment step in the defect detection program.

More specifically, the method for capturing information of the line of the present invention comprises processing a computer-aided design picture into a skeleton picture having a skeleton composed of a plurality of thin lines, each of which is a computer aid. Designing a thinning result of each line corresponding to the picture; obtaining a circuit image, the circuit image is taken from a substrate made according to the computer aided design picture; and the skeleton picture is aligned with the circuit image to Having each of the thin lines of the skeleton in the skeleton picture respectively correspond to the inside of each corresponding line in the circuit image; and extracting the phase of the circuit image according to the coordinate position of the pixel point of each thin line of the skeleton Corresponding line information of each line at the same coordinate position.

In a preferred example, the skeleton picture is a horizontal skeleton picture obtained by processing the computer aided design picture in a horizontal direction, and the horizontal skeleton picture has a horizontal skeleton formed by a plurality of thin lines extending in the horizontal direction. .

In another preferred example, the skeleton picture is a vertical skeleton picture obtained by processing the computer aided design picture in a vertical direction, and the vertical skeleton picture has a vertical line formed by a plurality of thin lines extending in a vertical direction. skeleton.

Preferably, each of the circuit images is a bright area, and the step of aligning the skeleton picture with the circuit image comprises performing a horizontal portion correction program, the horizontal portion correction program comprising: from the circuit image Finding the bright area closest to one of the thin lines extending in the horizontal direction; and moving the skeleton picture vertically in the direction of the bright area such that one of the thin lines is in the middle of the bright area.

Preferably, the step of aligning the skeleton picture with the circuit image includes Performing a vertical portion correction program, the vertical portion correcting program includes: finding the bright region closest to one of the thin lines extending in the vertical direction from the circuit image; and horizontally moving the skeleton image in the direction of the bright region, so that One of the thin lines is in the middle of the bright area.

Furthermore, the method for detecting a line defect of the present invention includes: capturing a substrate to be tested to obtain a circuit image; performing the circuit information acquisition method of the present invention on the obtained substrate to be tested, thereby obtaining the to-be-tested Circuit information of each line on the circuit image of the substrate; and analyzing and judging whether there is a defect on each line on the circuit image of the substrate to be tested according to the obtained line information. Preferably, the acquired line information can also be used to pre-establish the threshold value required for performing the aforementioned analysis and determination.

The non-line area information acquisition method of the invention comprises: processing a computer-aided design picture into a skeleton picture, the skeleton picture having a skeleton composed of a plurality of thin lines, each thin line being on the computer-aided design picture Corresponding thinning result of each non-line area; obtaining a circuit image, the circuit image is taken from a substrate made according to the computer aided design picture, the circuit image has multiple lines and multiple non-line areas Each line and non-line area is made according to the corresponding line and non-line area on the computer-aided design picture; the skeleton picture is aligned with the circuit image to make the skeleton in the skeleton picture Each thin line is respectively corresponding to the interior of each non-line area corresponding to the circuit image; and each non-line area corresponding to the circuit image is captured according to the coordinate position of the pixel of each thin line of the skeleton Information at the same coordinate location.

In a preferred example of the non-line area information acquisition method, the skeleton picture is a horizontal skeleton picture obtained by processing the computer-aided design picture in a horizontal direction, and the horizontal skeleton picture has a plurality of horizontal directions. A horizontal skeleton formed by extended thin lines.

Preferably, each non-line area in the circuit image mentioned in the non-line area information acquisition method is the bright area, and the step of aligning the skeleton picture with the circuit image includes performing a horizontal part correction procedure The horizontal portion correction program includes finding the bright region closest to one of the thin lines extending in the horizontal direction from the circuit image; and vertically moving the skeleton image in the direction of the bright region, so that one of the thin lines is aligned to the The middle position of the bright area.

In another preferred example of the non-line area information capturing method, the skeleton picture is a vertical skeleton picture obtained by processing the computer aided design picture in a vertical direction. The vertical skeleton picture has a vertical skeleton composed of a plurality of thin lines extending in the vertical direction.

Preferably, each non-line area in the circuit image mentioned in the non-line area information acquisition method is a bright area, and the step of aligning the skeleton picture with the circuit image includes performing a vertical part correction a program, the vertical portion correction program includes: finding the bright region closest to one of the thin lines extending in the vertical direction from the circuit image; and horizontally moving the skeleton image in a direction of the bright region to make the thin line pair The middle position of the bright area.

Another circuit defect detecting method of the present invention comprises: capturing a substrate to be tested to obtain a circuit image, and performing the non-line area information capturing method on the obtained circuit image of the substrate to be tested, thereby obtaining the to-be-tested Information about each non-line area on the circuit image of the substrate; and analyzing and judging whether there is a defect on the circuit image of the substrate to be tested according to the obtained line information. Preferably, the obtained non-line area information may also be used to pre-establish the threshold value required for performing the foregoing analysis and determination.

Compared with the prior art, the present invention first utilizes a skeleton to capture line information and/or non-line area information on a circuit image, and uses the captured information to achieve line defect detection.

The above described features and advantages of the invention will be apparent from the following description.

1‧‧‧ Circuit image of the substrate

10‧‧‧ circuit pattern

11‧‧‧Non circuit pattern

101‧‧‧ lines

2‧‧‧ CAM picture of the substrate

20‧‧‧ circuit pattern

21‧‧‧Non circuit pattern

201‧‧‧ lines

201a‧‧‧ middle line

3‧‧‧ skeleton picture

30‧‧‧ skeleton

301‧‧‧ Thin line

P1, p2‧‧ ‧ pixels

W1, w2‧‧‧ line width

E1, e2‧‧‧ edge points

3a‧‧‧ horizontal skeleton picture

30a‧‧‧ skeleton

301a‧‧‧ Thin line

3b‧‧‧ vertical skeleton picture

30b‧‧‧ skeleton

301b‧‧‧ Thin line

4‧‧‧CAM pictures

40‧‧‧Non-line area

5‧‧‧ skeleton picture

50‧‧‧ skeleton

501‧‧‧ Thin line

5a‧‧‧Vertical skeleton picture

5b‧‧‧ horizontal skeleton picture

Steps a~b and steps b1~b3 ‧‧‧ are the execution steps of the first preferred embodiment of the method for capturing information of the line of the present invention

a'~c' step ‧‧‧ is the execution step of the second preferred embodiment of the line information acquisition method of the present invention

The first figure shows a flow chart of a first preferred embodiment of the method for capturing information of the line of the present invention.

The second figure shows a CAM picture 2 exemplified by the present invention (only a partial area enlarged view is displayed).

The third figure shows the skeleton picture 3 processed according to CAM picture 2.

The fourth figure shows the centerline 201a on each line 201 on the CAM picture 2.

The fifth figure shows a circuit image 1 (only a partial area enlarged view is displayed) taken from a substrate made in accordance with CAM picture 2.

The sixth figure shows a schematic diagram of the alignment of the skeleton picture 3 and the circuit image 1.

The seventh figure shows an enlarged line 101 taken from circuit image 1.

Figure 8 is a flow chart showing a second preferred embodiment of the method for capturing information of the line of the present invention.

The ninth figure shows that the horizontal skeleton picture 3a is processed according to the CAM picture 2.

The tenth figure shows that the vertical skeleton picture 3b is processed according to the CAM picture 2.

The eleventh figure shows the CAM picture 4 inverted from the CAM picture 2.

The twelfth image shows the skeleton picture 5 processed according to the CAM picture 4.

The thirteenth image shows that the vertical skeleton picture 5a is obtained according to the CAM picture 4.

The fourteenth figure shows that the horizontal skeleton picture 5b is processed according to the CAM picture 4.

The first figure (A) shows a flow chart of a first preferred embodiment of a method for extracting line information according to the present invention, which includes the following steps a~b:

a) A computer-aided design picture (hereinafter referred to as CAM picture 2) is processed into a skeleton picture 3.

b) using the skeleton picture 3 to extract line information of each line or designated line on a substrate (for example, a printed circuit board) produced according to the CAM picture 2, for example, the gradation or line of each line or designated line Wide information. The term "circuit" as used herein generally refers to a conductor formed on the substrate, and is not limited to the form of a wire. For example, a conductor such as a metal pad, a solder ball, a metal ring, a metal pin, or the like is included.

The CAM picture 2 illustrated in step a is as shown in the second figure, and includes a circuit pattern 20 (white portion in the figure) and a non-circuit pattern 21 (black portion in the figure), and is processed according to CAM picture 2. The skeleton picture 3 is obtained as shown in the third figure, and includes a skeleton 30 (skeleton, all white thin line portions in the figure) composed of a plurality of thin lines 301. Here, each of the lines 201 in the circuit pattern 20 of the CAM picture 2 can be correspondingly processed into the skeleton picture 3 by using an algorithm on the morphology, such as thinning or skeletonization. Each of the thin lines 301 of the skeleton 30, or other processing techniques for picking up the skeleton of the object, may also be used to perform the foregoing processing. In any event, each of the thin lines 301 in the resulting skeleton 30 has a width of only one pixel and corresponds to each of the corresponding lines 201. Since each of the thin lines 301 is substantially composed of a plurality of pixel point connections, in the thinning or skeletonizing process, each of the thin lines 301 in the skeleton 30 is also recorded. The coordinate position of each pixel (or called the backbone point). Ideally, as shown in the fourth figure, each of the thin lines 301 corresponds to the intermediate line 201a of each of the corresponding lines 201 in the representative circuit pattern 20, and each of the pixels which are connected to form each of the thin lines 301 is substantially a corresponding representative. The corresponding line 201 is at an intermediate point in the width direction.

Preferably, as shown in the first figure (B), the above step b includes the following steps b1 to b3:

B1) Obtain a circuit image 1. The circuit image 1 illustrated here is taken from the substrate, which is a gray scale image (which may also be a color image) as shown in FIG. 5, and includes a circuit pattern 10 (light portion in the figure) and A non-circuit pattern 11 (dark portion of the figure). Each of the lines 101 in the circuit pattern 10 corresponds to each of the lines 201 in the CAM picture 2, so each of the thin lines 301 in the skeleton picture 3 also corresponds to each of the corresponding lines 101 in the representative circuit pattern 10.

B2) aligning the skeleton picture 3 with the circuit image 1 such that each line 301 of the skeleton 30 in the skeleton picture 3 is respectively directed to the inside of each of the corresponding lines 101 in the circuit pattern 10 of the circuit image 1. Preferably, it is to the intermediate position of the line 101 in the width direction as shown in the sixth figure. After the alignment is completed, each line 101 in the circuit image 1 is respectively aligned with each of the corresponding lines 301 in the skeleton picture 3, which means that each of the pixels in each of the thin lines 301 has a circuit image 1 A pixel point corresponds thereto, and the coordinate position of each pixel point of each of the thin lines 301 can be used as a coordinate position of the pixel point corresponding to the circuit image 1.

B3) According to the coordinate position of the pixel of each thin line 301 in the sixth figure, the corresponding line information of each line 101 at the same coordinate position is extracted. For example, in a small enlarged line 101 shown in the seventh figure, if the coordinate positions of the pixel point p1 and the pixel point p2 of the thin line 301 in the skeleton picture 3 are (100, 100), (100, 300), respectively, since The alignment of the skeleton picture 3 and the circuit image 1 is completed. Therefore, the line information at two pixel points of coordinates (100, 100) and (100, 300) in the circuit image 1 is the line information to be captured in this step. In this step, the line width of each line 101 corresponding to each of the thin lines 301 or a plurality of pixel points may be captured, for example, according to the coordinate position of the pixel point p1 on the thin line 101 from the circuit image 1. Find the pixel point corresponding to the pixel point p1 (unlabeled in the figure, actually located directly below the pixel point p1 in the figure), and then centered on the found pixel point, along the width direction (or normal side) The coordinate positions of the two edge points e1, e2 are respectively found up and down, and then the line width w1 corresponding to the found pixel point is calculated according to the coordinate positions of the two edge points found. The line width w2 in the seventh figure is obtained based on the coordinate position of the pixel point p2 on the thin line 101, and the process is not described here as before. The manner in which the edge points are obtained can be obtained by using a related technique of edge detection, such as a gradient operator search method (a commonly used gradient operator such as Sobel, Prewitt, and the first-order differential operator). Robert, Laplacian in the second-order differential operator, and LoG).

In the above step b3, the color gradation of all the pixels in the width direction (ie, the normal direction) of each line or each of the plurality of pixel points corresponding to each of the thin lines 301 may be extracted, for example, according to the thin line 301. The coordinate position of the pixel p1 is found from the circuit image 1 to find the pixel point corresponding to the pixel point p1, and then each of the internal lines 101 is drawn up and down in the vertical direction with the found pixel point as the center point. The gradation of the pixel, that is, the gradation of all the pixels in the line 101 that are in the same row in the vertical direction as the found pixel is extracted.

In step b2, regarding the alignment of the skeleton picture 3 and the circuit image 1, the existing image alignment method (or image alignment method), such as Template matching or image registration, may be selected first, and the circuit image 1 is selected. Adjusted so that it is facing CAM picture 2, at this time, the line 101 on the circuit image 1 is equivalent to being superimposed on the line 201 of the CAM picture 2, thereby narrowing the line corresponding to the circuit image 1 on the thin line 301 on the skeleton picture 3. The position difference between the 101, so, when the skeleton picture 3 is aligned with the circuit image 1, only the calibration procedure of the fine adjustment position is needed, and the calibration procedure can be achieved by comparing the brightness and darkness of the pixel points on the circuit image 1. . For example, if the thin line 301 extending substantially in the horizontal direction of the skeleton 30 is not aligned to the corresponding line 101, a horizontal portion correction procedure is required. This procedure includes first finding the closest one from the circuit image 1 along the horizontal level. The bright area of the thin line 301 extending in direction (because the area occupied by the line 101 is brighter than the other non-line areas), then moving the skeleton picture 3 vertically in the direction of the bright area, so that one of the thin lines 301 is aligned to the bright area In the intermediate position, the positional correction of the skeleton picture 3 in the horizontal direction is completed such that the thin lines 301 extending substantially in the horizontal direction are aligned to the inner position of the corresponding line 101.

In the step b2, if the thin line 301 extending substantially in the vertical direction in the skeleton 30 is not aligned to the corresponding line 101, a vertical portion correction procedure is required. The sequence includes first finding a bright area closest to one of the thin lines 301 extending in the vertical direction, and then moving the skeleton picture 3 horizontally in the direction of the bright area such that one of the thin lines 301 is aligned to the middle of the bright area, The positional correction of the skeleton picture 3 in the vertical direction is completed such that the thin lines 301 extending substantially in the vertical direction are located at intermediate positions inside the corresponding line 101.

In the above example, the skeleton 30 in the processed skeleton picture 3 is substantially the complete skeleton of the circuit pattern 20 of the CAM picture 2. In order to simplify the skeleton processing process and improve the quality of the processed skeleton, the present invention may also be selected. The following steps a'~c' of the invention replace the a~b steps described above. More specifically, the eighth figure shows a flow chart of a second preferred embodiment of the line information capturing method of the present invention, which includes the following steps a'~c': a') CAM picture 2 is horizontally Corresponding to the vertical direction is processed into a horizontal skeleton picture 3a and a vertical skeleton picture 3b. As shown in the ninth figure, the skeleton 30a in the horizontal skeleton picture 3a is composed of a plurality of thin lines 301a extending substantially horizontally. As shown in the tenth figure, the skeleton 30b in the vertical skeleton picture 3b is composed of a plurality of outlines. It is composed of a thin line 301b extending horizontally.

b') using the horizontal skeleton picture 3a to extract line information of each horizontal line or a specified horizontal line on a substrate (for example, a printed circuit board) produced according to the CAM picture 2, for example, each horizontal line or Information such as the gradation or line width of the specified horizontal line; and c') using the vertical skeleton picture 3b to extract line information of each vertical line or the specified vertical line on the substrate, such as each vertical line or designation Information such as the color gradation or line width of the vertical line.

The above b' and c' steps have no specific execution order, and the b' and c' steps can use the sub-steps shown in the above b1~b3 to complete the purpose of extracting the line information. In short, as long as b1~ The skeleton picture 3 in b3 is changed to the horizontal skeleton picture 3a or the vertical skeleton picture 3b, and the above object can be achieved by performing the steps b1 to b3 (including the above-described horizontal portion correction program and vertical portion correction program).

It can be seen from the above description that the line information acquisition method according to the present invention can capture the line information on the substrate prepared according to the CAM picture 2, and the line information can be applied to the detection of line defects. For example, in order to detect whether the line width of each line on a substrate to be tested prepared according to the CAM picture 2 conforms to the standard, the above-mentioned line information extraction method should be used first. The line information is taken from a standard substrate fabricated according to CAM picture 2. Since each line on the standard substrate is confirmed to be a standard line conforming to a standard line width, each of the circuit images 1 taken from the standard substrate is extracted by the above-described line information acquisition method. The line width of each pixel or multi-pixel point of one line 101 (in this case, the substrate shown in FIG. 5 is regarded as the standard substrate), and then the line width drawn from each line 101 can be The averaging operation is performed to obtain the average line width of each line as the standard line width of each line 101 itself. Alternatively, a statistical analysis may be performed on the line width of each of the extracted lines 101, thereby establishing a corresponding set of minimum line width thresholds and maximum line width thresholds, and each set of the aforementioned threshold values is respectively Make judgments on the line defects of each line. Then, using the above-mentioned line information capturing method, the line width of each pixel point or the position of the multi-pixel point of each of the lines 101 is captured from the circuit image 1 taken from the substrate to be tested (this is the fifth The substrate shown in the figure is used as the substrate to be tested, and then it is compared and judged whether the captured line width is greater than the corresponding maximum line width threshold. If the judgment result is "Yes", it means that the image is captured. If the result of the determination is "No", the comparison is continued and it is determined whether the captured line width is smaller than the corresponding minimum line width threshold value, if If the result of the determination is "Yes", it indicates that the line defect is present at the position corresponding to the line width captured, and if the result of the determination is "No", it means that the line width captured is in accordance with the standard.

In addition, the line information capturing method of the present invention may also be used to detect whether there is a disconnection defect on a substrate to be tested formed according to the CAM picture 2, specifically, firstly, the line information is captured from the substrate to be tested. The circuit image 1 captures the color gradation of each pixel point of each line in the width direction of each pixel point (or a plurality of pixel points) of each line 101, and takes an average value thereof to obtain each line. An average color gradation at a position of each pixel (or a plurality of pixel points) of 101; statistically analyzing the obtained color gradation, thereby establishing a minimum color gradation threshold for each corresponding line 101; Aligning and judging whether the average color gradation at the position where each pixel is captured is smaller than the corresponding minimum color gradation threshold; if the judgment result is "Yes", it indicates that the pixel point currently being aligned is located. There is a defect that the line is broken; and if the result of the determination is "NO", it means that there is no defect that the line is disconnected at the position where the pixel is currently aligned.

The skeleton picture 3 in the above example is created for capturing the line information on the line 101 of the circuit pattern 10 in the circuit image 1, if the information to be captured is bit In the information in the non-circuit pattern 11, for example, in order to detect whether there is a short-circuit defect in the circuit image 1, it is necessary to check whether or not a bridge phenomenon occurs in the non-line area. At this time, it is necessary to extract the information in the non-circuit pattern 11. The above-mentioned line information acquisition method of the present invention can be changed into a non-line area information acquisition method for extracting information in the non-circuit pattern 11 by using a slight modification, and more specifically, only the above CAM is needed. Picture 2 can be changed to CAM picture 4 shown in Fig. 11. The CAM picture 4 is an inverted result of the CAM picture 2, that is, the white area in the CAM picture 2 is inverted into the black area in the CAM picture 4, and the black area in the CAM picture 2 is inverted to become the white area in the CAM picture 4. Then, as in the above step a, thinning or skeletonizing each non-line area 40 (that is, a part of each white area) in the CAM picture 4 is obtained, thereby obtaining a skeleton picture 5 as shown in the twelfth figure. The skeleton 50 in the skeleton picture 5 is also composed of a plurality of thin lines 501, and each of the thin lines 501 has a width of only one pixel. Then, as in step b above, the information of each non-line area on the substrate prepared according to the CAM picture 2 is extracted by using the skeleton picture 5, and the detailed process can be referred to the steps b1 to b3 above, and only the skeleton picture is needed. 3 is replaced with the skeleton picture 5, and when the alignment is performed, each thin line 501 of the skeleton 50 is respectively directed to the inside of each non-line area corresponding to the circuit image 1, and is not described herein.

In an example, the above steps a' to c' can be used to process the CAM picture 5 in the horizontal direction and the vertical direction, respectively, into a vertical skeleton picture 5a and a fourteenth picture as shown in the thirteenth figure. a horizontal skeleton picture 5b, and then, using the vertical skeleton picture 5a, the information in each of the vertical non-line areas 40 or the specified vertical non-line areas 40 on the substrate produced according to the CAM picture 2 is extracted, And using the horizontal skeleton picture 5b to extract information in each of the horizontal non-line areas 40 or the specified horizontal non-line areas 40 on the substrate produced according to the CAM picture 2.

It can be seen from the above description that the information in the non-line area on the substrate prepared according to the CAM picture 2 can be obtained by using the non-line area information acquisition method of the present invention, and the information can be applied to the detection of line defects, such as the above. The detection process of the short-circuit defect detection side is substantially the same as the detection of the above-mentioned open circuit defect, and the difference is that in the process of detecting the short-circuit defect, the circuit image captured from the substrate to be tested is taken by using the non-line area information acquisition method. 1 extracting the color gradation of all the pixels in the width direction of each pixel (or pixels) of each non-line region of each non-line region and taking an average value thereof, thereby obtaining each non-line region The average color gradation at the location of a pixel (or multiple pixels), in addition, The color gradation is statistically analyzed, so that a minimum gradation threshold value is established for each corresponding non-line area, and when the comparison between the average gradation level and the minimum gradation threshold value and the judgment procedure is performed, if the judgment result is "No" means that there is a short circuit defect at the position of the pixel currently being compared; and if the result of the determination is "Yes", it means that there is no short circuit defect at the position of the currently aligned pixel.

As can be seen from the above description, the present invention first utilizes a skeleton to capture line information or non-line area information on a circuit image, and uses the captured information to perform line defect detection.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (14)

A method for extracting line information comprises: processing a computer-aided design picture into a skeleton picture, the skeleton picture having a skeleton composed of a plurality of thin lines, each thin line being corresponding to each of the computer-aided design pictures a thinning result of a line; obtaining a circuit image, the circuit image is taken from a substrate made according to the computer aided design picture, the circuit image has a plurality of lines, each line is based on the computer aided design picture Corresponding to the corresponding line; aligning the skeleton picture with the circuit image, so that each thin line of the skeleton in the skeleton picture is respectively corresponding to the inside of each corresponding line in the circuit image; And extracting line information of each line corresponding to each line of the circuit image at the same coordinate position according to a coordinate position of a pixel point of each thin line of the skeleton. The method for extracting line information according to claim 1, wherein the skeleton picture is a horizontal skeleton picture obtained by processing the computer auxiliary design picture in a horizontal direction, and the horizontal skeleton picture has multiple horizontal levels. A horizontal skeleton formed by thin lines extending in the direction. The method for extracting line information according to claim 1, wherein the skeleton picture is a vertical skeleton picture obtained by processing the computer auxiliary design picture in a vertical direction, and the vertical skeleton picture has a plurality of vertical lines A vertical skeleton formed by thin lines extending in the direction. The method for extracting line information according to claim 1 or 2, wherein each circuit in the circuit image is a bright area, and the step of aligning the skeleton picture with the circuit image comprises performing a horizontal part. a calibration program, the horizontal portion correction program includes: finding the bright region closest to one of the thin lines extending in the horizontal direction from the circuit image; and vertically moving the skeleton image toward the bright region to make the thin line The middle position to the bright area. The method for extracting line information according to claim 1 or 3, wherein each circuit of the circuit image is a bright area, and the step of aligning the skeleton picture with the circuit image comprises performing a vertical a portion correcting program, the vertical portion correcting program includes: finding the bright region closest to one of the thin lines extending in the vertical direction from the circuit image; and horizontally moving the skeleton image in the direction of the bright region to make the one of the The thin line is in the middle of the bright area. A method for detecting a line defect includes: capturing a substrate to be tested to obtain a circuit image; and performing the circuit information acquisition as described in any one of claims 1 to 5 on the obtained circuit image of the substrate to be tested. The method is used to obtain line information of each line on the circuit image of the substrate to be tested; and, according to the obtained line information, analyze and determine whether there is a defect on each line on the circuit image of the substrate to be tested. The method for detecting a line defect as described in claim 6 includes the use of the obtained line information to pre-establish a threshold value required for performing the analysis and determination. A non-line area information acquisition method includes: processing a computer-aided design picture into a skeleton picture, the skeleton picture having a skeleton composed of a plurality of thin lines, each thin line corresponding to the computer-aided design picture a thinning result of each non-line area; obtaining a circuit image, the circuit image is taken from a substrate made according to the computer aided design picture, the circuit image has a plurality of lines and a plurality of non-line areas, each A line and non-line area are made according to the corresponding line and non-line area on the computer-aided design picture; the skeleton picture is aligned with the circuit image so that each of the skeletons in the skeleton picture The thin lines are respectively corresponding to the interior of each non-line area corresponding to the circuit image; and each of the non-line areas corresponding to the circuit image is the same according to the coordinate position of the pixel of each thin line of the skeleton Information on the coordinates of the coordinates. The non-line area information acquisition method according to claim 8, wherein the skeleton picture is a horizontal skeleton picture obtained by processing the computer auxiliary design picture in a horizontal direction, and the horizontal skeleton picture has a plurality of A horizontal skeleton formed by thin lines extending in the horizontal direction. The method for extracting non-line area information according to item 8 of the patent application scope, wherein the skeleton picture is to process the computer auxiliary design picture in a vertical direction A vertical skeleton picture is obtained, the vertical skeleton picture having a vertical skeleton formed by a plurality of thin lines extending in the vertical direction. The method for extracting non-line area information according to claim 8 or 9, wherein each non-line area in the circuit image is a bright area, and the step of aligning the skeleton picture with the circuit image includes Performing a horizontal portion correction program, the horizontal portion correcting program includes: finding the bright region closest to one of the thin lines extending in the horizontal direction from the circuit image; and vertically moving the skeleton image in the direction of the bright region, so that One of the thin lines is in the middle of the bright area. The method for extracting non-line area information according to claim 8 or 10, wherein each non-line area in the circuit image is a bright area, and the step of aligning the skeleton picture with the circuit image Including performing a vertical portion correction program, the vertical portion correction program includes: finding the bright region closest to one of the thin lines extending in the vertical direction from the circuit image; and horizontally moving the skeleton image in the direction of the bright region, One of the thin lines is aligned to the middle of the bright area. A method for detecting a line defect includes: capturing a substrate to be tested to obtain a circuit image; and performing non-line area information according to any one of claims 8 to 11 on the obtained circuit image of the substrate to be tested. a method for obtaining information in each non-line area on the circuit image of the substrate to be tested; and Based on the obtained information, the analysis determines whether there is a defect on the circuit image of the substrate to be tested. The method for detecting a line defect according to claim 13 of the patent application, comprising using the obtained non-line area information to pre-establish a threshold value required for performing the analysis and determination.