TWI518902B - Flip-chip fet cell - Google Patents

Description

Flip-chip field effect transistor unit

The present invention relates to systems, components, and methods for a field effect transistor (FET) cell to be bonded to a substrate by flip-chip technology. More specifically, the present invention relates to a field-matching structure of a potentivating transistor unit to a separate substrate, electrically connected via a flip chip connection.

At high operating frequencies, field effect transistor (FET) components are typically fabricated on a substrate composed of gallium arsenide (GaAs) or gallium nitride (GaN) materials. While other materials can be used, gallium arsenide or gallium nitride is a higher quality material that is designed and controlled to provide superior performance of field effect transistor components. However, in addition to being of higher quality than other possible materials, gallium arsenide and gallium nitride are also more expensive and more difficult to manufacture. Unfortunately, in a typical wafer configuration, the major portion of the wafer area encompasses integrated passive components, such as a matching structure. These passive components do not benefit from the higher quality substrate materials described above, resulting in inefficient use of the wafer layout.

Referring to the prior art in FIG. 1, a typical wafer 100 includes a substrate 101 having active and passive components. In an exemplary embodiment, the wafer 100 is a monolithic microwave integrated circuit (MMIC). For example, wafer 100 can include a single crystal microwave integrated circuit for use in a power amplifier. Most of the space above the wafer 100 is occupied by passive components, such as a matching structure 110 and/or certain interconnect features. A smaller portion of the space is covered by active components, such as field effect transistor component 120 located in the region designated by component symbol 121. In the example depicted in FIG. 1, the region 121 containing the active field effect transistor element 120 occupies less than 10% of the area of the wafer 100, while the passive component occupies the remaining area.

The field effect transistor component 120 of Figure 1 can include an interdigital field effect transistor or a folded field effect transistor as is well known in the art. Field effect transistor component 120 and matching structure 110 are typically located on the same substrate 101 as shown. Integrating the matching structure 110 with the field effect transistor 120 on the same substrate has the advantage of reducing associated parasitic circuitry, and removing any interface between the field effect transistor and the corresponding integrated matching structure. This achieves the high degree of repeatability necessary under high frequency operating conditions. This high repeatability is ideal to achieve the required level of performance and reduce the need to tune this circuit. Similarly, as the operating frequency of this circuit increases, the parasitic circuitry also increases. Therefore, what the prior art teaches is the tendency to integrate the matching structure with other functional units on the single crystal microwave integrated circuit (MMIC) (ie, integrated on a single substrate).

Moreover, and with continued reference to the prior art of FIG. 1, a typical gallium arsenide substrate 101 is often thinned to enhance its thermal performance and provide better microwave performance at high frequencies. The thinned substrate 101 of high frequency performance is often used to avoid high order mode propagation. For example, to prevent propagation in modes other than the common quasi-TEM microstrip mode.

Further, in a general wafer design, a plurality of transistors are fabricated on the same substrate. Due to the accumulation nature of the transistor, if only one transistor on the wafer does not function properly, the entire wafer loses its function and cannot be used. Various types of transistors have different manufacturing success rates, called yields. Since multiple transistors are fabricated on the same substrate, the overall yield of the substrate (also known as rolled yield) is the combined probability of making N good field effect transistors on the same wafer. In other words, if the probability of manufacturing a single good field effect transistor is 99%, the probability of fabricating a wafer with M good field effect transistors is 0.99 ^N. For example, a wafer with 46 good field effect transistor elements was fabricated with a yield of 0.99 ⁴⁶ = 63%. In many cases, the single yield of a particular type of field effect is less than 99%. Thus, as the number of field effect transistors on a wafer increases, the probability of producing a functional field effect transistor component is reduced. This straight-through rate problem can significantly limit the size and complexity of the circuit, especially when the yield of a single field-effect transistor is only a few percentage points lower than 99%.

Therefore, there is a need to improve the layout and design of the wafer, and to produce more efficient wafer space utilization for the active components. In addition, there is a need to avoid the problem of straight-through rate when integrating a large number of field-effect transistors in a complex circuit.

In an exemplary embodiment, a field effect transistor cell includes a plurality of single transistors and interconnecting bumps configured to be flip-chip bonded to a substrate. This substrate has a major portion of a matching structure of the field effect transistor unit. In addition, the field effect transistor unit includes a stabilizing circuit that is connected to the ends of the individual transistors and further communicates to the inner connecting bumps described above.

The field effect transistor unit and the separation substrate having the main portion of the above matching structure have the advantage of being able to be used in combination of different materials. Different materials may be used more efficiently in a single efficacy cell, while other materials are suitable for separating substrates. Different considerations when choosing materials include thermal conductivity, manufacturing capabilities, and cost.

In addition, in order to avoid the straight-through rate problem, multiple field effect transistor units can be used in an electronic system. These field effect transistor units can be individually tested and can be discarded when they do not meet the demand or failure of the field effect transistor. Higher overall yields can be achieved by using multiple field effect transistor units and system combinations using modules. In an exemplary embodiment, the electronic system can be at least one power amplifier, a mixer, a low noise amplifier, a switch, a variable attenuator, or a phase shifter. Or other devices suitable for using multiple transistors.

Although the present invention has been described in detail in the present invention, it is understood that the invention may be practiced otherwise, and other embodiments may be practiced without departing from the spirit and scope of the invention. Next, make logical electrical and mechanical changes. Therefore, the following detailed description is for illustrative purposes only.

According to an exemplary embodiment, a field effect transistor unit includes one or more field effect transistors configured to be flip-chip mounted to a substrate. In this exemplary embodiment, the field effect transistor unit includes bumps for flip chip mounting to the next higher assembly level. In various exemplary embodiments, at least some of the passive portion of a typical MMIC is removed from the MMIC to the flip chip substrate. In this illustrative embodiment, the field effect transistor unit primarily includes an active component.

Although referred to as a "field effect transistor" (FET) component, it includes a metal semiconductor field effect transistor (MESFET), a metal-oxide-semiconductor field effect transistor (metal-oxide-semiconductor field effect transistor, MOSFET), and a junction gate field-effect transistor (JFET), the invention described herein can also be applied to a pseudomorphic high electron mobility transistor (PHEMT). ), metamorphic high electron mobility transistor (MHEMT), or any other active component type. Furthermore, these transistors may be either n-type or p-type.

In accordance with an exemplary embodiment of the present invention and with reference to FIG. 2, field effect transistor unit 200 includes a plurality of field effect transistor elements on a wafer. As noted above, this field effect transistor component can include a folded field effect transistor. The folded field effect transistors can be as described in U.S. Patent No. 6,388,528, "MMIC Folded Power Amplifier" and U.S. Patent No. 6,362,689, "MMIC Folded Power Amplifier", the inventors of which are identical to the present invention, and are generally listed as the present invention. Reference. According to an exemplary embodiment, the field effect transistor unit can include a field effect transistor element having more than two interdigital fingers. The preferred embodiment includes two field effect transistor elements, each field effect transistor element having eight interdigitated structures. In another exemplary embodiment, the field effect transistor unit can include a 2-24 interdigitated or 8-16 interdigitated field effect transistor. Other numbers of field effect transistors can also be used, depending on the field effect transistor unit application. According to various exemplary embodiments, the field effect transistor unit may include a plurality of (eg, 8-16 interdigitated) field effect transistors.

Moreover, in an exemplary embodiment, field effect transistor unit 200 further includes conductive bumps. 2 is a top view of the surface of the field effect transistor unit and the conductive bumps. The configuration of these conductive bumps provides contacts to facilitate connection to the next higher assembly level. In an exemplary embodiment, the field effect transistor unit 200 includes a gate inner connection bump 211, a source inner connection bump 212, and a drain inner connection bump 213. The number of such bumps can vary with the design of the field effect transistor unit 200. For example, in one exemplary embodiment, four gate inner connection bumps 211, eighteen source inner connection bumps 212, and nine drain inner connection bumps 213 are used. In an exemplary embodiment, the bumps can be about 65 microns square. In other exemplary embodiments, the bumps can be of any suitable size and shape. The layout of these bumps can also vary with the design constraints of the next higher assembly level and the field effect transistor component 200 itself.

In an exemplary embodiment, the surface area of the field effect transistor unit 200 is defined by the area of the planar surface of the component. In an exemplary embodiment, this surface area is about 1 mm ² . In other exemplary embodiments, the dimensions and dimensions of such elements can be any suitable size and scale. In an exemplary embodiment, a substantial portion of the surface area of the component is occupied by field effect transistor elements, interconnect bumps, interconnects, or other active components. In another embodiment, at least 50% of the wafer is occupied by field effect transistor elements and associated components. According to another embodiment, the field effect transistor unit 200 includes 20%-90% of the area occupied by the active elements. The active component portion of the field effect crystal includes a drain and a source interdigital finger, and an inner connection pad thereof. Moreover, in an exemplary embodiment, these active components also include appropriate spacing between the ends of the field effect transistors. For example, the spacing can be about 60-90 microns around the field effect transistor interdigital fingers.

According to an exemplary embodiment, the conductive bumps may be larger in size than the individual field effect transistor vias. In this exemplary embodiment, the distance between the individual field effect transistors can be greater than the field effect transistor spacing among the prior art MMICs to match the design of these conductive bumps. Although this will occupy a larger surface area of the component, this combination is possible because space can be saved by removing some passive components from the device. In another exemplary embodiment, the surface area of the field effect transistor unit is a function of process constraints, as is known to those skilled in the art. In addition, these intervals provide better thermal performance.

For example, but not limited to, a particular field effect transistor unit 200 is as shown in FIG. In this example, the field effect transistor unit 200 has a substrate size of about 800 microns x 1300 microns. The figure shows a circumference of about 1.4 mm, although the circumference can be changed. In an exemplary embodiment, each field effect cell system of the field effect transistor unit 200 is located within 10% of the perimeter of the field effect transistor. Moreover, in this embodiment, the conductive bumps are squares having a length of about 65 microns. As described in this embodiment, the field effect transistor unit 200 includes eighteen source conductive bumps, nine drain conductive bumps, and four gate conductive bumps. In another embodiment, the conductive bumps are square or include relatively rounded edges.

In an exemplary embodiment, the field effect transistor unit 200 further includes a stabilization circuit 220. An illustration of one of the stabilization circuits 220 is illustrated in FIG. According to this exemplary embodiment, the field effect transistor 300 includes a gate 301, a source 302, and a drain 303, and a gate inner connection bump 311, a source inner connection bump 312, and a turn. The bumps 313 are connected in the poles. The field effect transistor unit 300 can further include a signal input bump 314. According to an exemplary embodiment, the gate 301, the source 302, and the drain 303 can be interconnected and electrically connected to the gate inner connection bump 311, the source inner connection bump 312, and the drain inner connection. Bump 313. These connections are used to provide separate field effect transistor interdigital parallel electrical connections, as well as electrical connections to the inner connecting bumps.

In an exemplary embodiment, the stabilization circuit 220 is coupled between the gate and drain terminals of the field effect transistor 300 and the corresponding internal connection bumps. Moreover, in another exemplary embodiment, field effect transistor 300 further includes some matching components that are located adjacent gate 301. By placing the position of some matching components close to the gate 301, a wider bandwidth can be achieved after adding other matching structures.

For example, the stabilization circuit 220 includes a resistor between the gate 301 and the source 302, and includes a resistor and a capacitor connected in parallel with each other between the gate 301 and a node, and is connected in the node and the gate 311. A resistor is included therebetween, and another capacitor is included between the signal input bump 314 and the node. In an exemplary embodiment, the stabilizing circuit can be a parallel R-C network. In addition, any stabilizing circuit 220 configured to provide unconditional stability to the field effect transistor device and substantially reduce low frequency out-of-band gain may be used, which may cause problematic oscillation or non-essential Pseudo performance.

According to other exemplary embodiments, field effect transistor unit 200 includes a portion of passive components. In particular, some passive components perform better when placed close to field effect transistors. For example, field effect transistor unit 200 can include an input DC blocker. The field effect transistor unit 200 can further include a DC bias circuit, and an interconnect feature. In an exemplary embodiment, field effect transistor unit 200 includes a gate bias connection configured to The daisy chained provides an internal connection to an additional similar field effect transistor unit. Similarly, daisy chain connections contribute to drain mode suppression resistors. In an exemplary embodiment, the pressing resistor helps to suppress the divergence mode of the odd mode energy. The odd mode energy may be due to the reaction to combine a plurality of field effect transistors in parallel to produce a small amplitude. symmetry.

In another exemplary embodiment, field effect transistor unit 200 does not include any matching structures. Thus, in embodiments where there is no matching structure over field effect transistor 200, a large portion of the area of field effect transistor element 200 can be utilized. In this illustrative embodiment, all of the matching structure circuits are off-chip, such as on another substrate. According to an exemplary embodiment, the matching structure includes elements that are grouped together and dispersed to provide impedance matching to the field effect transistor unit. In an exemplary embodiment, the matching structure can include capacitors, inductors, transmission lines, or other components suitable for impedance matching. In an exemplary embodiment, this matching structure includes only output power matching and bonding networks.

In yet another exemplary embodiment, field effect transistor unit 200 includes a partially matched structure associated with a field effect transistor in field effect transistor unit 200, but does not include all associated matching structures. In an exemplary embodiment, the matching structure circuit is between an inner connecting bump and a field effect transistor terminal on the field effect transistor unit 200. However, the main portion of the matching and internal connection structure of the field effect transistor unit 200 is located on another substrate. In an embodiment, the major portion of the matching structure is defined by the area of the matching structure. In a second embodiment, the major portion of the matching structure is defined by an overall impedance transformation. Moreover, in the exemplary embodiment, substantially all of the internal connections between the field effect transistor unit 200 and associated matching structures, power supply combinations, and power supply dispersions are performed on another substrate.

As described above, in an exemplary embodiment, the field effect transistor unit 200 is bonded to another substrate using flip chip technology. Flip chip technology involves assembling electronic components onto a substrate, board, or other component in a side-down configuration. In an exemplary embodiment, the connection between the electronic component and a substrate is achieved by interconnecting the bumps. In an exemplary embodiment, the inner connecting bumps are constructed of gold or solder. In addition, other materials can also be used as the inner connecting bumps. In contrast, according to an exemplary embodiment, the field effect transistor unit 200 is not bonded to the next higher assembled layer substrate using wire bonds. The wire is tied in the side-up configuration, and the wires are used to connect between the components.

In a flip chip connection, also known as Direct Chip Attach (DCA), electronic components (such as a wafer) are directly connected to the substrate without conventional wire bonding. Thus, the field effect transistor unit 200 is flipped and bonded directly to another substrate that is configured to aid in matching, biasing, and providing internal connections. In an exemplary embodiment, field effect transistor unit 200 is reflow bonded to a substrate. In another exemplary embodiment, the field effect transistor unit 200 is configured to pick-and-place with surface-mount technology (SMT) during assembly. In an exemplary embodiment, a system (e.g., a power amplifier system) can be fabricated using a fully surface bonded assembly process, at least in the field effect transistor unit 200. Thus, in various exemplary embodiments, field effect transistor unit 200 is configured to eliminate wafer and wire processes, while substantially reducing overall assembly cost and improving reproducibility of the assembly process.

As discussed previously, gallium arsenide substrates are typically thinned to improve their thermal performance and provide better microwave performance at high frequencies. In an exemplary embodiment, the use of flip chip technology to connect a field effect transistor unit to a substrate can eliminate the need to thin the substrate or provide an electrical via through the gallium arsenide substrate for grounding, since all internal connections are It is carried out by the inner connecting bumps. Moreover, in an exemplary embodiment, the substrate to which the field effect transistor unit is to be connected is configured to control and determine the mode of transfer in the internal connection medium. Once the need for thinned wafers (to provide thermal performance and high frequency electrical performance) is eliminated, the complexity and cost of manufacturing field effect transistor units can be further reduced compared to conventional technology MMICs.

According to an exemplary embodiment and with reference to FIGS. 4A and 4B, a power amplifier system 400 includes a first field calibrating crystal unit 401, a second field calibrating crystal unit 411, and a substrate 450. In another exemplary embodiment, power amplifier system 400 further includes at least one capacitor 420 that can be a standard surface mount capacitor. In an exemplary embodiment, field effect transistor cells 401, 411 are directly bonded to substrate 450, which has a matching structure 460. The field effect transistor units 401, 411 can be mounted to the substrate 450 such that the field effect transistor units are in the same plane as one another but in a different plane than the substrate 450. These field effect transistor units can be further mounted in a plane parallel to the plane of the substrate 450. In an exemplary embodiment, the number of transistors in the field effect transistor unit 401 may be the same as or different from the number of transistors in the field effect transistor unit 411. Meanwhile, the type of transistor in the field effect transistor unit 410 may be different from the transistor in the field effect transistor unit 411. Moreover, the number of field effect transistor units used in a particular power amplifier system 400 can also vary. Figures 4A and 4B show two of the above described field effect transistor units, but the number of field effect transistor units connected to system 400 can be any number greater than two. In different designs, performance and efficiency can be improved by using different numbers or types of field effect transistor units. However, the use of only one or two sizes or types of field effect transistor units may result in manufacturing economics in part due to the economics of the range.

In the exemplary method, an integrated circuit design uses a specific number of transistors. For example, a power amplifier design might use four parallel field-effect transistor units to achieve the desired 2 watt power level and possibly use four gain stages to achieve the desired 25 dB gain level. In this example, the first and second stages may utilize only one field effect transistor unit, while in the third stage two parallel field effect transistor units are used, and in the final stage four parallel field effect units are used. Crystal unit. The number of transistors required can be included in one or more field effect transistor units. In addition to the number of transistors, the space for an integrated circuit design should also be considered. For example, if 64 transistors are required in an integrated circuit, a single field effect transistor unit with more than 64 transistors can be used. However, three field effect transistor units each having 24 transistors can also be used and leave some unused transistors in the final device.

According to the method for manufacturing an electronic device, the electronic device is manufactured by selecting and bonding a field effect transistor unit from a standard field effect transistor unit. In addition, this method has its uses when manufacturing or testing new designs in small quantities. For example, in such an embodiment, only the substrate needs to be designed, and by omitting a specific MMIC and substrate design step, significant time and expense are saved. In different exemplary embodiments, the same type of field effect transistor unit can be used from start to finish in an integrated circuit, which is more cost effective.

Moreover, in an exemplary embodiment, an integrated circuit design is configured to incorporate a field effect transistor unit into the device by performing a modular approach to have a better yield number. In an exemplary embodiment, the number of field effect transistors in each cell is limited to improve the passthrough rate to better than the passthrough rate of placing all field effect transistors into a single MMIC. In an exemplary embodiment, instead of printing the entire complex circuit on a single substrate, the design is dispersed into a modular field effect transistor unit. In this exemplary embodiment, a plurality of field effect transistor units are used, and if one of the transistors fails, only the field effect transistor unit is discarded, rather than the entire integrated circuit is discarded. In one implementation, the field effect transistor unit is tested for compliance before being bonded to the substrate. In a second embodiment, a failed field effect transistor unit is removed from the substrate after initial bonding.

According to another exemplary embodiment, advantages are obtained with materials that are more suitable for their use. For example, according to an exemplary embodiment, one type of material is used in the field effect transistor unit and another type of material is used in the separate substrate, and the field effect transistor unit is bonded in the separate substrate.

In an exemplary embodiment, the field effect transistor cell 200 is fabricated on a gallium arsenide (GaAs) or gallium nitride (GaN) substrate. Other materials can also be used. As mentioned previously, these types of substrates have important high quality performance characteristics for operating field effect transistor devices at high frequencies. If the signal carried at signal input 314 is a high frequency signal or a high frequency radio frequency, then this field effect transistor device can be referred to as a high frequency. In an exemplary embodiment, the high frequency refers to a millimeter wave frequency or higher. In an exemplary embodiment, high frequency refers to 20 GHz or higher. In another exemplary embodiment, the high frequency refers to 15 GHz or higher. In another exemplary embodiment, the high frequency system is between 15 GHz and 45 GHz.

In contrast, passive components such as mating structures can be fabricated with any suitable different substrate material. More specifically, in an exemplary embodiment, the passive component can be moved to a substrate that includes a material other than gallium arsenide or gallium nitride. In an exemplary embodiment, a suitable substrate material comprises aluminum nitride (AlN), alumina, or low temperature co-fired ceramic (LTCC). This material can be used in a film substrate. The film substrate can use thermo-sonic bump attach methods. In another exemplary embodiment, a suitable substrate material may comprise a ceramic material or a Teflon-based circuit board material such as Rogers RO4003. This material can be shared with standard printed circuit board (PCB) materials. Standard printed circuit boards can use solder reflow as a method of bonding. In addition, other suitable substrate materials that would be used by those skilled in the art can be used.

In an exemplary embodiment, an electronic device including a substrate and a flip chip-connected field effect transistor unit is configured to improve thermal conductivity. In an embodiment, the substrate material contributes to improved thermal conductivity. For example, an aluminum nitride substrate has better thermal conductivity than gallium arsenide. According to an exemplary embodiment, the substrate 450 is selected to have better thermal conductivity properties. Thus, in an exemplary embodiment, substrate 450 comprises aluminum nitride. Additionally, substrate 450 can include any material that preferably conducts heat away from field effect transistor units 410, 411. In addition, the material of the matching structure may be selected to preferably conduct heat away from the field effect transistor unit 401, 411.

In another embodiment, the layout of the field effect transistor unit contributes to the improvement in thermal conductivity. According to an exemplary embodiment, the field effect transistor unit 200 is configured to improve thermal performance by dispersing at least some of the field effect transistors above the field effect transistor unit. The spacing between the field effect transistor units in an electronic device is set to be farther than the spacing of the transistors in the conventional integrated circuit, and better thermal performance can be achieved because the field effect transistor elements have a mutual Less thermal interaction, so there is less mutual heating. At the same time, additional substrate space can be used as heat conduction, resulting in lower overall thermal resistance. To achieve this effect, it is not necessary to increase the size of the field effect transistor unit, since some passive components have been compensated for differences in size after being removed from the field effect transistor unit.

The illustrative embodiments described herein can be implemented in different devices and systems. A one-line power amplifier would include 9-16 interdigital field effect transistors, resulting in a straight-through rate problem in a typical design. In an exemplary embodiment, and in contrast to FIG. 4, a power amplifier 400 is designed and fabricated using field effect transistor units 401 and 411. In another exemplary embodiment, power amplifier 400 includes a substrate and a power supply, an MMIC coupled to the substrate having a wireless RF input and a wireless RF output, and a matching structure coupled to the MMI wireless RF output. The MMIC is flip-chip connected to the substrate such that the MMIC is electrically connected to the power supply. According to an exemplary embodiment, the bias injection structure is formed on a printed circuit board.

In addition to a power amplifier, the field effect transistor unit can also be effectively used in mixers, low noise amplifiers, switches, variable attenuators or phase shifters, and those familiar with this memory should know Other suitable devices. Moreover, in an exemplary embodiment, the field effect transistor unit is used in the prototype and initial testing of the circuit design. Another advantage of applying a field effect transistor unit to a circuit is that it can be based on a substrate design rather than a complete MMIC design to produce a custom product.

In an exemplary embodiment, a utility cell unit is designed using standard MMIC models and layout techniques. This field effect transistor unit is stabilized and partially matched for a particular frequency band. This field effect transistor unit is then fabricated and characterized for use in a variety of applications. Once characterized, the field effect transistor unit is then used in conjunction with its standard footprint to design the internal connection, matching and bias injection structures of the substrate in a manner that is associated with the structures on a gallium arsenide substrate. The design is the same. Moreover, in an exemplary embodiment, the field effect transistor unit is tested and functioning properly prior to bonding to a high assembly level.

Although not necessarily so limited, the invention described in the specification can be most practically used in high frequency devices, such as devices configured to operate in or above the millimeter frequency range. Moreover, the systems, methods and components disclosed herein may have the highest value when the throughput of an MMIC is less than 80%. In addition, the disclosed subject matter may have the highest value when the cost per unit area of the substrate carrying the field effect transistor is much lower than the cost per unit area of the substrate to which the passive structure is applied. For example, "below" may mean 50% or less. In other words, in one embodiment, the substrate carrying the field effect transistor may have a value per unit area, perhaps 100 to 1000 times that of a substrate suitable for passive structures. For example, a gallium arsenide MMIC device region typically costs $1-$5 per square millimeter, while a Rogers RO4003 may cost less than 0.1 cents per square millimeter. As a further example, a ceramic substrate such as aluminum nitride (AlN) or alumina may take only about 1 to 5 cents per square millimeter.

The present invention may be embodied in other specific forms without departing from the spirit and scope of the invention. The aspects of the specific embodiments are to be considered as illustrative and not restrictive. Accordingly, the scope of the invention is indicated by the appended claims rather All changes that fall within the meaning and scope of the patent application are deemed to fall within the scope of the patent application. In the present specification, "including", "comprising" or other synonym is intended to cover a non-limiting inclusion, such as a process, method, article, or device that includes a list of elements, and includes not only those elements but Other elements not specifically listed or implied in such processes, methods, articles or devices. Furthermore, the elements recited in the specification are essential to the practice of the invention unless specifically referred to as "essential" or "critical".

100. . . Epistar

101. . . Substrate

110. . . Matching structure

120. . . Field effect transistor component

121. . . region

200. . . Field effect transistor unit

211. . . Gate connection bump

212. . . Source connection bump

213. . . Bump inner connecting bump

220. . . Stable circuit

300. . . Field effect transistor

301. . . Gate

302. . . Source

303. . . Bungee

311. . . Gate connection bump

312. . . Source connection bump

313. . . Bump inner connecting bump

314. . . Signal input bump

400. . . Power amplifier system

401. . . First field effect transistor unit

411. . . Second field effect transistor unit

420. . . capacitance

450. . . Substrate

460. . . Matching structure

In order to immediately understand the advantages of the present invention, the present invention briefly described above will be described in detail with reference to the specific embodiments illustrated in the accompanying drawings. The invention is described with additional clarity and detail with reference to the accompanying drawings in which: FIG.

1 is a prior art single crystal microwave integrated circuit (MMIC) on a single substrate;

Figure 2 is an illustration of an embodiment of a utility cell;

3 is a schematic view showing an example of a field effect transistor and an inner connecting bump;

4A-4B are illustrative embodiments of a power amplifier system including a plurality of field effect transistor units, and corresponding exploded views.

400. . . Power amplifier system

401. . . First field effect transistor unit

411. . . Second field effect transistor unit

420. . . capacitance

450. . . Substrate

460. . . Matching structure

Claims (35)

A field effect transistor (FET) unit is formed on a first substrate, the field effect transistor unit includes: a plurality of single transistors integrated on the first substrate; and a plurality of inner connecting bumps (bumps) The system is configured to flip-chip the field effect transistor unit to a second substrate, the plurality of inner connecting bumps including at least one signal input bump, and a gate connection bump a source connection bump and a drain connection bump, each of the plurality of single field effect transistors comprising a gate terminal, a source terminal and a drain terminal as terminals; and a stabilization circuit It is in communication with the ends of the plurality of single field effect transistors and is further in communication with the plurality of inner connecting bumps. The field effect transistor unit of claim 1, wherein the plurality of interconnecting bumps are configured to be directly connected to one of the matching structures on the second substrate. The field effect transistor unit of claim 1, wherein the field effect transistor unit is located in a plane, and the second substrate is not located in the plane. The field effect transistor unit of claim 1, wherein the first substrate comprises at most only one portion of one of the matching structures associated with the plurality of single transistors. The field effect transistor unit of claim 1, wherein the plurality of single transistors and the plurality of interconnecting bumps cover at least fifty percent of a major surface of the first substrate. The field effect transistor unit of claim 1, wherein the first substrate is formed of a first material, and the second substrate is formed of a second material, and wherein the first material is This second material is different. The field effect transistor unit of claim 6, wherein the first material is at least one of gallium arsenide (GaAs) and gallium nitride (GaN), and wherein the second material is not arsenic. Gallium or gallium nitride. The field effect transistor unit of claim 1, wherein the plurality of interconnecting bumps are located within 10% of the periphery of the field effect transistor unit. The field effect transistor unit of claim 1, wherein the field effect transistor unit is configured to receive a radio frequency (RF) input signal directly from a matching structure on the second substrate. The field effect transistor unit of claim 9, wherein the field effect transistor unit is configured to directly transmit a wireless RF output signal to the matching structure on the second substrate. The field effect transistor unit of claim 1, wherein the field effect transistor unit is configured to be flip-chip bonded to a next higher assembly level having a matching structure. A power amplifier comprising: at least one field effect transistor unit as described in claim 1 and further comprising a second substrate; wherein the at least one effect transistor unit is permeable to the electrical connection At least one flip-chip connection of the transistor unit to the second substrate is coupled to the a second substrate; and wherein the at least one effect transistor unit has a radio frequency input and a radio frequency output, the radio frequency output is in communication with a matching structure, at least a portion of the matching structure is located on the second substrate on. The power amplifier of claim 12, wherein the at least one effect transistor unit is located on a plane, and the second substrate is not located on the plane. The power amplifier of claim 12, wherein the first substrate comprises at least one of a gallium arsenide material and a gallium nitride material. The power amplifier of claim 12, wherein there is no matching structure on the at least one effect transistor unit. The field effect transistor unit of claim 1, wherein the stabilizing circuit is connected to a gate and a source end of a transistor and a corresponding inner connecting bump. The field effect transistor unit of claim 1, further comprising a gate bias connection configured to provide an internal connection to an additional similar field effect transistor unit in a daisy chained manner and The inclusion of a drain mode suppression resistor is configured to suppress the concurrent odd mode energy, which produces a small amplitude asymmetry in response to the combination of multiple field effect transistors in parallel. An electronic system comprising: a plurality of field effect transistor units, each field effect transistor unit further comprising: a plurality of field effect transistors each comprising an end, wherein the plurality of field effect transistor systems are located on a semiconductor substrate on; a DC blocker (DC) is disposed on the semiconductor substrate; a gate connection bump is located on the semiconductor substrate; a source connection bump is located on the semiconductor substrate; and a drain connection bump is disposed Positioned on the semiconductor substrate, wherein the gate, source and drain interconnect bumps are configured to flip-chip the plurality of field effect transistor units to a printed circuit board (PCB) a substrate; and a stabilization circuit, wherein the stabilization circuit is in communication with each of the gates and the drain connection bumps, wherein the stabilization circuit further comprises a gate stabilization circuit; the printed circuit board substrate includes at least one a matching structure in which the gate inner connection bump or the drain inner connection bump is in communication, wherein the matching structure on the printed circuit board substrate comprises a dispersed matching component; wherein at least two of the plurality of field effect transistor units The parallel interconnects form a parallel field effect transistor unit, wherein the parallel field effect transistor unit comprises a daisy chain gate bias internal connection between the two field effect transistor units. The electronic system of claim 18, wherein the semiconductor substrate comprises one of gallium arsenide or gallium nitride materials, and wherein the printed circuit board substrate does not include the gallium arsenide or the gallium nitride material . The electronic system of claim 19, wherein the semiconductor substrate comprises a film substrate. The electronic system of claim 18, wherein when the yield of the single field effect transistor is less than 97%, the electronic system has a rolled yield of 90% or higher, and all fields The total number of effect transistors is at least 4. Such as the electronic system described in claim 18, wherein the plurality of field effects At least 50% of the area of the transistor unit is covered by the plurality of field effect transistors, the stabilizing circuit, and the gate, source and drain interconnect bumps. The electronic system of claim 18, wherein there is no matching structure above the plurality of field effect transistor units. The electronic system of claim 18, wherein the semiconductor substrate is located in a first plane, and the printed circuit board substrate is located in a second plane, the second plane is not common to the first plane Plane, and wherein the first plane is parallel to the second plane when connected to the second plane. The electronic system of claim 18, wherein the semiconductor substrate comprises a first material and the printed circuit board substrate comprises a second material, the first material being different from the second material. The electronic system of claim 18, wherein the gate, source and drain interconnect bumps are configured to be directly connected to a matching structure of the printed circuit board substrate. An electronic system comprising: a plurality of field effect transistor units, each field effect transistor unit further comprising: a plurality of field effect transistors each comprising an end, wherein the plurality of field effect transistor systems are located on a semiconductor substrate a DC blocker (DC) is disposed on the semiconductor substrate; a gate connection bump is located on the semiconductor substrate; a source connection bump is located on the semiconductor substrate; and a drain is connected a bump on the semiconductor substrate, wherein the gate, The source and drain internal connection bumps are configured to connect the plurality of field effect transistor units to a printed circuit board (PCB) substrate; and a stabilization circuit, wherein the stabilization circuit is associated with each gate, and The drain inner connecting bumps communicate; the printed circuit board substrate includes a matching structure in communication with at least one of the gate inner connecting bumps or the drain inner connecting bumps. The electronic system of claim 27, wherein the matching structure on the printed circuit board substrate comprises discrete component matching. The electronic system of claim 27, wherein the stabilization circuit further comprises a gate stabilization circuit. The electronic system of claim 27, wherein at least two of the plurality of field effect transistor units are interconnected in parallel to form a parallel field effect transistor unit, and wherein the parallel field effect transistor unit comprises A daisy chain gate bias connection between the two field effect transistors. The electronic system of claim 27, wherein the semiconductor substrate comprises at least one of gallium arsenide (GaAs) or gallium nitride (GaN) materials, and wherein the printed circuit board substrate does not comprise gallium arsenide. Or gallium nitride. The electronic system of claim 27, wherein when the yield of the single field effect transistor is less than 97%, the electronic system has a rolled yield of 90% or higher, and all fields are The total number of effect transistors is at least 4. The electronic system of claim 27, wherein at least 50% of the area of the plurality of field effect transistor units is the plurality of field effect transistors, the stable electricity The road, and the gate, the source and the drain are covered by the connection bumps. The electronic system of claim 27, wherein the plurality of field effect transistor units have no matching structure. The electronic system of claim 27, wherein the semiconductor substrate is located in a first plane, and the printed circuit board substrate is located in a second plane that is not common to the first plane Plane, and wherein the first plane is parallel to the second plane when connected to the second plane.