TWI518879B - Integrated circuit module and manufacturing methods and application thereof - Google Patents

Description

Integrated circuit module and its making method and application

The invention relates to an integrated circuit module, a manufacturing method thereof and an application thereof, and particularly to an integrated circuit module including a transistor having a reverse short channel effect (RSCE) and an application thereof method.

With the increasing complexity of integrated circuits, feature size and wiring space are increasingly limited, in order to meet the ever-increasing requirements for performance and bulk density of super large scale integration, increase process density, reduce components, and semiconductors. Processes and designers are still a constant challenge.

However, since the feature size of the current process is approaching the physical limit of the optical tool, it is impossible to achieve the desired precision in many steps such as positioning, development, etching, chemical mechanical polishing, and the like. Therefore, when the circuit design is performed, if the process limit is not considered at all, the Short Channel Effect (SCE), the Threshold Voltage (Vth) drift, and the Punch-Through effect may be induced. And problems such as an increase in leakage current increase, which in turn leads to a decrease in yield.

In order to improve the short channel effect, a pocket implant structure is a commonly used method. It is implanted in a p-type metal-oxide-semiconductor element (eg pMOS) with an n-type dopant (nMOS is the opposite). The implantation position is at the periphery of the source and the drain near the gate, and the source and the drain are surrounded, so that the piercing effect can be suppressed, and the critical voltage of the component can be increased to reduce the leakage current.

However, when the semiconductor component is operated at the sub-threshold voltage, it will cause a negative anti-short channel effect of the component. This is because the ring-shaped implant reduces the effect of Drain Induce Barrier Lowing (DIBL), causing the ring-shaped implant to over-compensate the component's threshold voltage, resulting in weaker component drive capability and increased power consumption. Timing violation.

In order to solve these problems, it has been possible to comprehensively increase the length of the element channel to dilute the threshold voltage increase caused by the complementary metal-oxide-semiconductor element. However, increasing the component channel length in a comprehensive manner will increase the critical size at the same time, which is contrary to the design goal of reducing the process density.

Another conventional method is to reduce the size of the transistor by using the effect of the anti-short channel effect by fixing the operating voltage of the integrated circuit to the sub-critical power to save the layout area and reduce the drain and source. Capacitive load to improve circuit power performance. However, this practice severely limits the design space and application range of the logic circuit.

Therefore, there is a need to provide an advanced integrated circuit module and its application method, which can be applied to any range of operating voltages, and reduce process density and manufacturing cost while taking into account the operating speed of the integrated circuit and saving power consumption.

An object of the present invention is to provide an integrated circuit module including: a first transistor having a first channel and a first threshold voltage absolute value, and electrically connected to the first transistor The second transistor. Wherein the second transistor has a second channel having a length greater than a length of the first channel and having a second threshold voltage absolute value less than an absolute value of the first threshold voltage, and the first transistor has the same critical value as the second transistor Threshold Voltage implant (Vt implant) concentration.

In an embodiment of the invention, the source of the second transistor is grounded. In an embodiment of the invention, the second channel length is twice the length of the first channel. In an embodiment of the invention, the first transistor and the second transistor each have a pocket implant structure.

In an embodiment of the invention, the integrated circuit module operates under a sub threshold voltage. Among them, the operating voltage is substantially no more than 0.5V. In an embodiment of the invention, the integrated circuit module has an operating voltage substantially above, below or equal to ranging from 0.9V to 1.2V.

In an embodiment of the invention, the integrated circuit module further includes a third transistor electrically coupled to the first transistor and the second transistor. Wherein the third transistor has the same threshold voltage doping concentration as the second transistor, and has a third channel having a length smaller than the second channel, and a third threshold voltage absolute value greater than the absolute value of the second threshold voltage.

Another object of the present invention is to provide a method of fabricating an integrated circuit module comprising the steps of: first providing a substrate; and sequentially forming a gate dielectric layer and a gate material layer on the substrate. Next, a threshold voltage doping process is performed on the gate material layer to define a threshold voltage doping region in the substrate. Then, a first transistor and a second transistor electrically connected to each other are formed on the substrate to define a first channel and a second channel respectively in the threshold voltage doping region, wherein the length of the second channel is greater than The length of the first channel.

In an embodiment of the invention, the forming of the first transistor and the second transistor includes the steps of: first patterning the gate dielectric layer and the gate material layer to form the first gate and the second gate . Next, at least one ion doping process is performed to define a first source/drain and a second source/drain in the substrate adjacent to the first gate and the second gate.

In an embodiment of the invention, the method for manufacturing an integrated circuit module further includes performing a ring-shaped implant process to form a first ring-shaped implant region and a second ring under the first channel and the second channel, respectively. A type of implanted region adjacent to the first source/drain and the second source/drain. In an embodiment of the invention, the method further includes forming a ground loop to ground the source of the second transistor.

In an embodiment of the invention, the second channel length is twice the length of the first channel.

In an embodiment of the invention, the first transistor and the second transistor are formed, and further comprising: forming a third transistor electrically connected to the first transistor and the second transistor, and having a smaller than the second The length of the third channel of the channel length.

Another object of the present invention is to provide a method for designing a logic circuit comprising the steps of: first simulating and designing a logic circuit composed of a plurality of standard integrated circuit modules. Next, analyze this logic circuit to determine the critical path. An anti-short channel effect integrated circuit module is then provided to replace at least one standard integrated circuit module in the critical path. The anti-short channel effect integrated circuit module includes: a first transistor having a first channel and a first threshold voltage absolute value, and a second transistor electrically coupled to the first transistor. Wherein the second transistor has a second channel having a length greater than a length of the first channel and having a second threshold voltage absolute value less than an absolute value of the first threshold voltage, and the first transistor has the same critical value as the second transistor Voltage doping concentration.

In an embodiment of the invention, the source of the second transistor is grounded. In an embodiment of the invention, the anti-short channel effect integrated circuit module operates under a sub-threshold voltage and has an operating voltage substantially no greater than 0.5V. In an embodiment of the invention, the anti-short channel effect integrated circuit module has an operating voltage substantially higher than, lower than or equal to ranging from 0.9 V to 1.2 V.

In an embodiment of the invention, the first transistor and the second transistor each have a ring-shaped implant structure.

In an embodiment of the present invention, the anti-short channel effect integrated circuit module further includes a third transistor electrically coupled to the first transistor and the second transistor and having the same threshold as the second transistor. And a voltage doping concentration, and having a third channel length that is less than a second channel length, and a third threshold voltage absolute value that is greater than an absolute value of the second threshold voltage.

In accordance with the above, embodiments of the present invention are in the same semiconductor process in which an integrated circuit module is fabricated that includes at least two different channel lengths and has an anti-short channel effect. When it is applied to the design of the logic circuit, only some circuit modules of the critical path need to be selected, and low voltage operation is performed to increase the circuit performance, thereby improving the problem of clock deviation; without the power in the logic circuit The crystals are all replaced by transistors with anti-short channel effects; there is no need to fix the operating voltage of the logic circuit under the sub-critical power, so the degree of freedom in circuit design can be retained. Moreover, due to the integrated circuit module, the intrinsic transistor process is utilized to lengthen the channel length of a part of the transistor, which does not change the critical size of the transistor and does not reduce the process density. On the contrary, because the length of the channel is elongated, the resistance to the variation of the transistor process is relatively increased, and the process cost can be saved. Therefore, the conventional problem can be solved and the above object of the invention can be achieved.

SUMMARY OF THE INVENTION The object of the present invention is to provide an integrated circuit module and a method and a manufacturing method thereof, which can be applied to any range of operating voltages, and take into account the operating speed and power consumption of the integrated circuit, and reduce the process density and manufacturing cost. The above and other objects, features and advantages of the present invention will become more apparent and understood. The formula is described in detail below.

Referring to FIGS. 1A to 1F, FIGS. 1A to 1F are diagrams showing a complementary metal-oxide semiconductor inverter having an anti-short channel effect according to a preferred embodiment of the present invention. CMOS inverter) 100 process profile.

The manufacturing method of the complementary metal-oxide semiconductor inverter 100 includes the steps of: firstly providing a substrate 101, and sequentially forming a gate dielectric layer 102 and a gate material layer 103 on the substrate 101 (as shown in FIG. 1A is shown). Next, a threshold voltage doping process 104 is performed on the gate material layer 103 to define a threshold voltage doping region 105 (shown in FIG. 1B) in the substrate 101. In a preferred embodiment of the present invention, the threshold voltage doping process 104 is performed by a doping process on the surface of the substrate 101 using a p-type dopant (but not limited to), such as boron, to form a surface down from the substrate. An extended threshold voltage doping region 105.

Then, the gate dielectric layer 102 and the gate material layer 103 are patterned to form a first gate 106 and a second gate 107 (as shown in FIG. 1C). Then, the first gate 106 is used as a mask to selectively perform a light doping process, thereby forming a P-type first lightly doped region 111a in the substrate 101; and using the second gate 107 as a mask. Another lightly doping process is used to form an N-type second lightly doped region 111b among the substrates 101, and in the threshold voltage doping region 105, a first channel 113 and a second channel 114 are respectively defined (as shown in the figure). 1D is shown). The length of the second channel 114 is greater than the length of the first channel 113; the second channel 114 is preferably twice the length of the first channel 113.

Thereafter, the ring-shaped implant process is selectively performed to form an N-type first ring-shaped implant region 115a and a P-type second ring under the first lightly doped region 111a and the second lightly doped region 111b, respectively. Type implant area 115b (as shown in Figure 1E). Next, spacers 112 are formed on the sidewalls of the first gate 106 and the second gate 107 by a deposition and/or thermal oxidation process. Then, using the first gate 106, the second gate 107 and the spacer 112 as a mask, an ion implantation process 108 is performed to define a P-type first source/drain 109 and an N-type second source/汲The pole 110 forms a first transistor 116 and a second transistor 117 (as shown in FIG. 1F).

Subsequent to the subsequent process, a wire, such as an interconnect 118, is formed to electrically connect the first transistor 116 and the second transistor 117 to complete the complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect. Preparation.

Referring to FIG. 1G, FIG. 1G is a structural top view of a complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect according to the above preferred embodiment. The first transistor 116 and the second transistor 117 share the same gate line; the width of the first gate 106 of the first transistor 116 is substantially the width of the second gate 107 of the second transistor 117. Half. In addition, the source 110a of the second transistor 117 is electrically connected to the ground circuit 119. The drain 110b of the second transistor 117 is electrically connected to the drain 109a of the first transistor 116 via the interconnect 118.

It is noted that since the first transistor 116 and the second transistor 117 are produced using the same fabrication process, the same substrate 101, the gate dielectric layer 102, and the gate material layer 103 are patterned. Therefore, the first transistor 116 and the second transistor 117 can have the same absolute value of the threshold voltage doping concentration. According to the anti-short channel effect, when the length of the component channel increases, the critical voltage value of the component decreases, and a higher driving current can be obtained. Therefore, when the length of the first channel 113 of the first transistor 116 is relatively shortened without changing the critical dimension of the entirety of the complementary metal-oxide semiconductor inverter 100 having the anti-short channel effect, the first The length of the channel 113 is relatively smaller than the length of the second channel 114 of the second transistor 117, and the absolute value of the second threshold voltage of the second transistor 117 is less than the absolute value of the first threshold voltage of the first transistor 116. That is, the threshold voltage value of the second transistor L17 is relatively lowered, and the current passing through the second transistor 117 is relatively increased.

By using the anti-short channel effect, and since the first transistor 116 and the second transistor 117 share the same gate line, the second gate can be shortened without changing the original critical dimension of the first gate 106. The size of 107 is to achieve the purpose of lengthening the length of the second transistor 117 channel. Therefore, two kinds of transistors having different channel lengths can be formed without adding an additional mask or etching step. In addition, the length of the second transistor 117 is elongated, which relatively increases the resistance of the transistor process to variation. For example, the length of the channel is lengthened, and the doping step can be used to counteract the influence of Random Dopant Fluctuation (RDF) on the critical voltage of the transistor, so that a certain degree of process yield can be increased. In addition, by using the integrated circuit module provided by the present invention for the logic circuit, the component driving capability is reduced, the power consumption is increased, and the clock deviation problem is significantly improved. Due to the two adjacent transistors stacked in the logic circuit, parasitic capacitance is usually generated between the metal wires, which causes the transistor switching speed to be delayed, resulting in a decrease in the response speed of the logic circuit. For example, in the present embodiment, the use of the anti-short channel effect provided by the second transistor 117 helps to lower the threshold voltage of the second transistor 117 and increase the operating current flowing through the second transistor 117. The reaction of the complementary metal-oxide semiconductor inverter 100 is accelerated.

In general, the integrated circuit module provided by the present invention is applied to the transistor closest to the ground line. Referring to FIG. 1H, FIG. 1H is a transistor-level diagram of a complementary metal-oxide semiconductor inverter 100 having an anti-short channel effect according to the above preferred embodiment. In the present embodiment, the second transistor 117 of the integrated circuit module having the anti-short channel effect is the transistor closest to the ground line. Because of such a design method, it is not necessary to change the channel length of each transistor in the logic circuit, and only the channel length of the second transistor 117 closest to the ground line needs to be relatively increased, thereby speeding up the switching of the logic gate. speed. It can save the layout area and improve the clock skew of the logic circuit.

However, in order to highlight the anti-short channel effect of the complementary metal-oxide semiconductor inverter 100, the complementary metal-oxide semiconductor inverter 100 is preferably below the sub-critical voltage, for example, the operating voltage is substantially no more than 0.5V. , to operate.

This is because the anti-short channel effect changes the critical voltage value of the component, and the threshold voltage is exponentially affected by the sub-critical current, so the drive current continues to increase to the saturation point with the channel length. If the complementary metal-oxide semiconductor inverter 100 is operated under a general voltage ranging from 0.9 V to 1.2 V, the threshold voltage value changed due to the anti-short channel effect is greater than the transistor channel size change for saturation. The influence of the current of the zone is small, so the anti-short channel effect may be less obvious. However, in some embodiments of the invention, the integrated circuit module can still operate at substantially higher, lower or equal to the normal operating voltage.

It should be noted that the above embodiments are merely used to illustrate the features of the present invention. The integrated circuit module with anti-short channel effect can still be applied to other integrated circuit modules, such as standard logic gates. Please refer to FIG. 2. FIG. 2 is a circuit diagram of a transistor level of an AND gate 200 having an anti-short channel effect according to another preferred embodiment of the present invention.

The gate 200 includes a plurality of third transistors 120 electrically coupled to the first transistor 116 and the second transistor 117 in addition to the first transistor 116 and the second transistor 117. The channel length of the third transistor 120 is smaller than the channel length of the second transistor 117. In some embodiments of the invention, the third transistor 120 and the first transistor 116 and the second transistor 117 are completed by the same process step. The channel length of the third transistor 120 is preferably equal to the channel length of the first transistor 116. However, in other embodiments, the third transistor 120 and the first transistor 116 and the second transistor 117 are completed by different process steps, and the channel length of the third transistor 120 is smaller than that of the second transistor. The channel length of 117, but the channel length of the third transistor 120, is not equal to the channel length of the first transistor 116.

In addition, the above-mentioned integrated circuit module with anti-short channel effect can be integrated into the standard cells of the circuit design for analog design of the logic circuit.

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a logic gate circuit 300 according to another preferred embodiment of the present invention. The logic gate circuit 300 is a logic circuit diagram designed according to product requirements through a laboratory. It is composed of a plurality of standard components, such as NAND gates 301, 302 and 303, or OR gate 304, XOR gate 305, and inverters 306, 307, 308, 309. , 310 and 311.

In order to improve the problem of improving the clock skew of the logic gate circuit 300, the logic circuit 300 is first analyzed by a simulation tool, such as an Electronic Design Automation EDA tool, to determine a critical path (as indicated by the arrow). This is the longest delay path formed by inverters 306, 307, 308 and 309 and gates 301 and 303 and OR gate 304. Then, from the standard cells library, at least one integrated circuit module with an anti-short channel effect is selected to replace the general standard components in the critical path, such as the sluice gates 301 and 303 and or the gate 304. . By the anti-short channel effect, the gap between the long delay path and the short delay path is shortened, thereby improving the fastest operating frequency value limited by the longest delay path and reducing the clock deviation.

Although, in order to highlight the anti-short channel effect, the standard integrated circuit module having an anti-short channel effect is preferably operated below the sub-threshold voltage, for example, the operating voltage is substantially no more than 0.5V. However, in some embodiments of the invention, logic circuit 300 can still operate at substantially higher, lower, or equal normal operating voltages ranging from 0.9V to 1.2V.

In accordance with the above, embodiments of the present invention are in the same semiconductor process in which an integrated circuit module is fabricated that includes at least two different channel lengths and has an anti-short channel effect. When it is applied to the design of the logic circuit, only some circuit modules of the critical path need to be selected, and low voltage operation is performed to increase the circuit performance, thereby improving the problem of clock deviation; without the power in the logic circuit The crystals are all replaced by transistors with anti-short channel effects; there is no need to fix the operating voltage of the logic circuit under the sub-critical power, so the degree of freedom in circuit design can be retained. Moreover, due to the integrated circuit module, the intrinsic transistor process is utilized to lengthen the channel length of a part of the transistor, which does not change the critical size of the transistor and does not reduce the process density. On the contrary, because the length of the channel is elongated, the resistance to the variation of the transistor process is relatively increased, and the process cost can be saved. Therefore, it is possible to solve the conventional problem and achieve the above object.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Complementary metal-oxide semiconductor inverter

101. . . Substrate

102. . . Gate dielectric layer

103. . . Gate material layer

104. . . Threshold voltage doping process

105. . . Threshold voltage doping region

106. . . First gate

107. . . Second gate

108. . . Ion doping process

109. . . First source/dip

109a. . . Bungee

110. . . Second source/dip

110a. . . Source

110b. . . Bungee

111a. . . First lightly doped region

111b. . . Second lightly doped region

112. . . Clearance wall

113. . . First channel

114. . . Second channel

115a. . . First ring type planting area

115b. . . Second ring type planting area

116. . . First transistor

117. . . Second transistor

118. . . Internal connection

119. . . Ground loop

120. . . Third transistor

200. . . Gate

300. . . Logic gate circuit

301. . . Gate

302. . . Gate

303. . . Gate

304. . . Gate

305. . . Mutual exclusion or gate

306. . . inverter

307. . . inverter

308. . . inverter

309. . . inverter

310. . . inverter

311. . . inverter

1A through 1F are process cross-sectional views of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, in accordance with a preferred embodiment of the present invention.

1G is a structural top view of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, according to a preferred embodiment of FIGS. 1A through 1F.

1H is a transistor-level circuit diagram of a complementary metal-oxide semiconductor inverter having an anti-short channel effect, according to a preferred embodiment of FIGS. 1A through 1F.

2 is a circuit diagram of a transistor level of a gate having an anti-short channel effect, according to another preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of a logic gate circuit according to another preferred embodiment of the present invention.

100. . . Complementary metal-oxide semiconductor inverter

106. . . First gate

107. . . Second gate

109a. . . Bungee

110a. . . Source

110b. . . Bungee

113. . . First channel

114. . . Second channel

116. . . First transistor

117. . . Second transistor

118. . . Internal connection

119. . . Ground loop

Claims (7)

An integrated circuit module includes: a first transistor having a first channel and a first threshold voltage absolute value; and a second transistor electrically coupled to the first transistor Having a second channel length that is twice the length of the first channel, and a second threshold voltage absolute value that is less than the absolute value of the first threshold voltage, and the first transistor has the same one as the second transistor Threshold Voltage implant (Vt implant) concentration. The integrated circuit module of claim 1, wherein a source of the second transistor is grounded. The integrated circuit module of claim 1, wherein the integrated circuit module operates under a sub threshold voltage. The integrated circuit module of claim 3, wherein the integrated circuit module has an operating voltage substantially no greater than 0.5V. The integrated circuit module of claim 1, wherein the integrated circuit module has an operating voltage substantially higher than, lower than or equal to ranging from 0.9V to 1.2V. The integrated circuit module of claim 1, further comprising a third transistor electrically coupled to the first transistor and the second transistor and having the same shape as the second transistor The threshold voltage doping concentration and has a small a third channel length of the second channel length, and a third threshold voltage absolute value greater than the second threshold voltage absolute value. The integrated circuit module of claim 1, wherein the first transistor and the second transistor each have a pocket implant structure.