CN105870060B

CN105870060B - Electronic device and system and method for manufacturing and using the electronic device and system

Info

Publication number: CN105870060B
Application number: CN201610252340.2A
Authority: CN
Inventors: 斯科特·E·汤普森; 达莫代尔·R·图马拉帕利
Original assignee: Triple Fujitsu Semiconductor Co Ltd
Current assignee: Triple Fujitsu Semiconductor Co Ltd
Priority date: 2009-09-30
Filing date: 2010-09-15
Publication date: 2019-07-16
Anticipated expiration: 2030-09-15

Abstract

The system and method for disclosing the power consumption in a kind of reduction electronic device, a kind of electronic device and system and method and a kind of semiconductor devices for manufacturing and using the electronic device and system.Mainly implement the structures and methods by reusing block CMOS process flow and manufacturing technology.The structures and methods are related to deepdepletion channel (DDC) design, and CMOS based devices is allowed to have reduced Sigma V compared to traditional block CMOS_T, and the threshold voltage V of the FET with dopant on channel region can be allowed_TMore accurately set.DDC design also has strong bulk effect compared to traditional block CMOS transistor, allows to carry out power consumption important dynamic control.

Description

Electronic device and system and method for manufacturing and using the electronic device and system

The application be the applying date be September in 2010 15, application No. is 201080054379.4, entitled " electronics The divisional application of the application for a patent for invention of device and system and method for manufacturing and using the electronic device and system ".

Related application

The U.S. Provisional Application No.61/247 submitted this application claims on September 30th, 2009,300 priority, this is interim The full content of application is hereby incorporated by reference.This application claims the U.S. Provisional Applications submitted on November 17th, 2009 No.61/262,122 priority, entire contents of the provisional application are hereby incorporated by reference.The application also requires 2010 The U.S. Provisional Application No.12/708 that year submits for 18 days 2 months, 497 priority, all the contents of the application are tied by reference Together in this.

Technical field

A kind of method the present invention relates to electronic device and system and for manufacturing and using the electronic device and system, with And a kind of semiconductor devices, more particularly to a kind of semiconductor devices comprising deepdepletion channel (DDC) design.

Background technique

Electronic device has unprecedentedly become an inalienable part of daily life.Such as personal computer and How the system of mobile phone has substantially worked to us, how we play and how we communicate and be transformed.Every mistake 1 year new equipment that can all introduce such as digital music player, E-book reader and plate is removed, and to already existing production Strain column improve.These new products show growing innovation, and how such innovation constantly gives birth to us Work is changed.

Electronic system is to world economy and modern cultural so far and adhering to Moore's Law to semi-conductor industry very big Increasing importance is generated on part.What Gordon mole by looking first at the founder of the Intel of the phenomenon named rubs Your law states become the number of cheap transistor as the time is steady on integrated circuit (or chip) in same area Surely increase.Some industry specialists quantify the law, such as illustrate that the number of transistor in same area is probably every two years turned over Times.In the case where functional increase that no Moore's Law provides reduction related to cost and size, today extensively may be used The practice or can afford that many electronic systems cannot be paid.

For a period of time, semi-conductor industry is manufactured the circuit in chip by using block CMOS technology and successfully protected Hold Moore's Law.Block CMOS technology is verified especially " (scalable) that can reduce ", means and is making at existing manufacture While reason and equipment are optimized and reused in order to maintain acceptable product cost, block CMOS transistor can be made It is smaller and smaller.Historically, as the size of block CMOS transistor reduces, power consumption also reduces, facilitates the industry and protecting The transistor density increased is provided while holding Moore's Law with reduced cost.Thus, semi-conductor industry can be with them Size reduction block CMOS power consumption, reduce operation transistor and they where system cost.

However, in recent years, the power consumption that block CMOS is reduced while reducing their size has become to be increasingly difficult to.It is brilliant Body pipe power consumption directly affects chip power-consumption, and influences the cost of operating system, and in some cases, influences the effect of system With.For example, if transistor while the power consumption of each transistor keeps identical or increases on identical chip area Number it is double, the power consumption of chip will turn over more times.This is partly due to needing to cool down obtained chip, thus need more Energy.As a result, this, which will use, turns over more times in the cost of energy of terminal temperature difference for operating the chip.The power consumption of this increase is also The usability that the electronic product of consumer for example can be reduced significantly by reducing the battery life of mobile device.There are also other Effect such as increases the generation of heat, needs to radiate, and potentially reduces the reliability of system and negatively affects environment.

Had extensive understanding in semiconducter engineering Shi Dangzhong: constantly the power consumption of reduction block CMOS is infeasible, In part because it is believed that the operation voltage V of transistor_DDNo longer reduce with the reduction of the size of transistor.CMOS transistor Conducting or shutdown.The state of CMOS transistor is by being applied to threshold voltage of the voltage relative to transistor of the grid of transistor V_TValue determine.While transistors switch is conducting, consumption can be by the dynamic power of following formula expression:

P dynamic=CD_DD ²f

Wherein, V_DDIt is the operation voltage for being supplied to transistor, C is the load electricity of the transistor when transistors switch is conducting Hold, and f is the frequency of transistor operation.While transistor shutdown, static power is consumed, can be by formula: P be static =I_OFFV_DDTo indicate, wherein I_OFFIt is leakage current when the transistor is off.Historically, which mainly leads to Cross drop low operating voltage V_DD(it reduces dynamic and both static powers) reduces the power consumption of transistor.

Low operating voltage V drops_DDPart ability depend on can accurately set threshold voltage V_T, but with transistor Size has become more and more difficult since various factors (including such as Random Dopant Fluctuation (RDF)) reduces.For using block The transistor that CMOS processing is formed, set threshold voltage V_TMajor parameter be the amount of dopant in channels.Influence V_TOther Factor is cyclic annular injection, source electrode and drain electrode extends and other factors.Theoretically, this can be accurately performed, so that in identical chips On identical transistor by V having the same_T, but in reality, threshold voltage can change significantly.This means that these are brilliant Body pipe will not all switch simultaneously in response to identical grid voltage, and some will not be switched to conducting.For with 100nm Or the transistor of smaller channel length, RDF are V_TVariation (commonly referred to as Sigma V_TOr σ V_T) main decision because Element, and σ V caused by RDF_TAmount with channel length reduce and increase.As shown in Figure 1, the Fig. 1 is based on by Intel's public affairs The information provided is provided, the experimental data of estimation, together in IEEE International Solid State Circuits Conference in 2009 by Kiyoo Itoh, The keynote that Hitachi Ltd is carried out shows that the conventional wisdom of semiconducter engineering teacher has been found that the σ increased in nanoscale block CMOS V_T1.0V is set as positive operation voltage V_DDActual lower limit.VDD is illustrated as with the work for reducing the region TARGET The decline slop function (downward-sloping function) of industry target.However, being used for σ V_TCurve with reduction Device feature size and increase, wherein RDF practically causes V_minIncrease.Dynamic and static power work function be power= CV_DD ²f+IV_DD.Thus, entire power increases.

Due to these and other, the engineer of semi-conductor industry widely believes must in the processing node in future Block CMOS must be abandoned, but regardless of there are many well known σ V for reducing in short channel device_TTechnology.For example, a reduction σ V in block CMOS_TTraditional mode, which is related to providing, increases ditch as channel vertical extends downwardly (towards substrate far from grid) The non-uniform doping profile of concentration of dopant in road.Although the retrogressing doping profile of this type does not reduce the spirit to doping variation Sensitivity, but it increases the sensitivity to short-channel effect, to negatively affect the operation of device.Because of short-channel effect, These doping parameters do not reduce generally for nanoscale devices, so that this mode generally is not suitable for use in nanoscale short channel crystal Pipe.Using the technology mobile towards the short channel device formed at 45nm or even 22nm processing node, in this device The benefit of fallback mode is considered limited.

Work is to overcome the semiconducter engineering teacher of these technology barriers to be intended to using super steep retrogressing trap (SSRW) to solve With the relevant performance issue of nano-area is narrowed down to compared with.Such as the retrogressing doping for nanoscale devices, SSRW technology makes With special doping profile, heavily doped layer is formed below lightly doped channel.SSRW profile is to adulterate with doping difference is retreated Agent level has very steep increase so that channel doping is reduced to alap level.This steep dopant profile can cause The reduction of short-channel effect, the mobility and smaller parasitic capacitance of the increase in channel region.However, being used for when manufacturing these When the device that high volume, nanometer-grade IC are applied, highly difficult these structures of realization.This difficulty is partly due to retreat trap Diffusion and SSRW dopant species enter in channel region, especially for the p trap device of such as NMOS transistor.In addition, making Random doping agent density fluctuation will not be eliminated with SSRW, and (it can be by σ V_TIncrease to unacceptable level) the problem of.

The trial for the shortcomings that overcoming existing piece of CMOS to implement in addition to these and other, the industry have become emphasis and have focused on The not no CMOS transistor structure of dopant in channels.This transistor arrangement is for example including fully- depleted silicon-on-insulator (SOI) and various FINFET or omega gated device.SOI device usually has the crystal being limited on thin top silicon layer Pipe, the thin top silicon layer pass through glass or the thin dielectric layer (being known as buried oxide layer) and silicon substrate point of silica It opens.FINFET device controls the electric field in silicon channel using multiple grids.This can by in silicon channel have low-mix Miscellaneous dose and have reduced σ V_T.The atomic level of this quantity for inject dopant atom in channels or position becomes Change inessential.However, the types entail chip of device and relevant processing are more more complicated and expensive than used in the block CMOS.

The manufacturer of given substantially cost and risk relevant to new technology is transitioned into, semiconductor and electronic system is Muchly seek a kind of method of extension block CMOS used.These effort are proved to be unsuccessful so far.Constantly reduce block Power consumption in CMOS is increasingly considered impassable problem in the semiconductor industry.

Summary of the invention

To solve the above-mentioned problems, the present invention provides a kind of electronic device and system and for manufacturing and using electronics dress It sets and the method for system and a kind of semiconductor devices.

According to an aspect of the present invention, a kind of semiconductor devices includes:

First cmos circuit and the second cmos circuit, are formed in corresponding trap, and including multiple deepdepletion channels (DDC) field effect transistor (FET)；

Each DDC transistor includes shielding area, is electrically connected to each corresponding trap；Undoped channel layer, Above the shielding area；Gate stack, is located above the undoped channel region, is located at the grid pile to control Electric conductivity between the drain electrode and source electrode of folded two sides；Wherein

The trap of first cmos circuit is subjected to the first noumenon bias, and the trap of second cmos circuit is subjected to not It is same as the second body bias of the first noumenon bias.

According to another aspect of the present invention, a kind of semiconductor devices includes the first circuit module and second circuit module,

First circuit module includes the first field effect transistor,

First field effect transistor includes:

First dopant well has the first concentration of dopant；

First grid is located above first dopant well, to control the conduction between the first drain electrode and the first source electrode Property；

First, undoped with channel, has and is less than 5x10¹⁷Atom/cm³The second concentration of dopant, described first undoped with ditch Road is located between first drain electrode and the first source electrode and is located at below the first grid；

First shielding area has third concentration of dopant, and it is undoped that the third concentration of dopant is greater than described first Ten times of second concentration of dopant of channel, and it is greater than first concentration of dopant；

First threshold voltage adjustment region is located at described first undoped between channel and first shielding area, uses To change the threshold voltage of first field effect transistor, the first threshold voltage adjustment region, which has, is less than the third 4th concentration of dopant of concentration of dopant；And

The first noumenon interconnecting piece is electrically connected to first dopant well, so that first dopant well is provided with first Body bias；

Second circuit module includes the second field effect transistor,

Second field effect transistor includes:

Second dopant well has the 5th concentration of dopant；

Second grid is located above second dopant well, to control the conduction between the second drain electrode and the second source electrode Property；

Second, undoped with channel, has and is less than 5x10¹⁷Atom/cm³The 6th concentration of dopant, described second undoped with ditch Road is located between second drain electrode and the second source electrode and is located at below the second grid；

Secondary shielding region has the 7th concentration of dopant, and it is undoped that the 7th concentration of dopant is greater than described second Ten times of 6th concentration of dopant of channel, and it is greater than the 5th concentration of dopant；

Second threshold voltage adjustment region is located at described second undoped between channel and the secondary shielding region, uses To change the threshold voltage of second field effect transistor, the second threshold voltage adjustment region, which has, is less than the described 7th 8th concentration of dopant of concentration of dopant；And

Second ontology interconnecting piece is electrically connected to second dopant well, so that second dopant well is provided with second Body bias；

Wherein first dopant well is isolated with second dopant well, and the first noumenon bias is by with described second Body bias is mutually provided independently, and first circuit module works in first mode, the second circuit module work In second mode, the first mode is different from the second mode.

In accordance with a further aspect of the present invention, a kind of semiconductor devices includes multiple circuit modules,

Each circuit module includes field effect transistor,

The field effect transistor includes:

Dopant well has the first concentration of dopant；

Grid is located above the dopant well, to control the electric conductivity between drain electrode and source electrode；

Undoped with channel, has and be less than 5x10¹⁷Atom/cm³The second concentration of dopant, the undoped channel is located at institute It states between drain electrode and the source electrode and is located at below the grid；

Shielding area, has third concentration of dopant, and the third concentration of dopant is greater than the of the undoped channel Ten times of two concentration of dopant, and it is greater than first concentration of dopant；

Threshold voltage adjustments region, be located at it is described undoped between channel and the shielding area, to change the field The threshold voltage of effect transistor, the threshold voltage adjustments region have the 4th doping less than the third concentration of dopant Agent concentration；And

Ontology interconnecting piece is electrically connected to the dopant well, so that the dopant well is provided with body bias；

The dopant well that wherein each circuit module has is isolated with other circuit modules, the multiple circuit module Each body bias be independent from each other, and each circuit module works in mode different from each other.

The present invention relates to deepdepletion channel design (DDC) designs, allow CMOS based devices compared to traditional block CMOS With reduced Sigma V_T, and the threshold voltage V of the FET with dopant on channel region can be allowed_TMore accurately set It is fixed.DDC design also has strong bulk effect compared to traditional block CMOS transistor, allows to carry out power consumption important dynamic control System.

Detailed description of the invention

Fig. 1 is shown for the power limit and σ V for devices scale_TThe example of the trend of limitation.

Fig. 2A shows the view of the field effect transistor according to one embodiment with deepdepletion channel (DDC).

Fig. 2 B shows the view of the channel with deepdepletion region according to one embodiment.

Fig. 2 C shows another example for the trizonal channel for having different levels of doping according to one embodiment.

Fig. 2 D shows another example for the channel for having deepdepletion region according to one embodiment.

Fig. 3 shows the figure according to one embodiment doping concentration and channel depth.

Fig. 4 shows the variation according to one embodiment concentration of dopant and the figure of device depth.

Fig. 5 shows the different threshold voltages from various devices drawn to supply voltage as background according to one embodiment Refinement figure example.

Fig. 6 is illustrated according to an exemplary improved σ V_TExample.

Fig. 7 A shows the example of the block CMOS transistor formed according to conventional process and structure.

Fig. 7 B shows the DDC transistor according to one embodiment, has compared with the conventional block cmos device of Fig. 7 A Deep many depleted regions.

Fig. 8 A shows the example of FET corresponding with the conventional block CMOS structure illustrated in Fig. 7 A.

Fig. 8 B shows the example of FET corresponding with the novel deep trap structure of Fig. 7 B diagram.

Fig. 9 shows the example of the universal mobility curve for NMOS device.

Figure 10 shows the example of the comparison between DDC structure and the threshold voltage and body bias of uniform channel.

Figure 11 shows the σ V of DDC structure and uniform channel_TCompared between body bias.

Figure 12 shows showing for the comparison between the profile of novel DDC structure and the profile of the conventional block CMOS with SSRW Example.

Figure 13 shows example of traditional cmos device compared with the structure constructed according to disclosed embodiments.

Figure 14 A-I shows the example of the process flow of the device for manufacturing the channel with DDC doping profile.

Figure 15 shows the multi-mode that the mechanism of ontology is applied to high doped shielding area and by body bias voltage The example of device.

Figure 16 shows threshold voltage V between n-channel DDC device and traditional n-channel device_TWith bias voltage V_BSComparison Example.

Figure 17 A is shown how the variation of threshold voltage causes the wide diffusion of delay time between device in traditional devices Example.

Figure 17 B shows the example of the improved delay-time characteristic for DDC device according to the embodiment.

Figure 18 is shown for the static V set according to the device of one embodiment_TFigure.

Figure 19 shows the example of the multiple groups transistor with respective ontology according to one embodiment.

Figure 20 shows the example being laid out according to 4 terminal resistor of n-channel of one embodiment.

Figure 21 shows the example of 4 terminal resistor of channel according to one embodiment with shallow p-well (SPW).

Figure 22 shows the example for the dynamic multi-mode transistor for having ontology access transistor according to one embodiment.

Figure 23, which is shown, according to one embodiment there is the another of dynamic multi-mode transistor of local trench isolations (PTI) to show Example.

Figure 24 shows the example of 4 terminal resistors according to one embodiment with PTI.

Figure 25 shows the example for 3 terminal resistors for having local interlinkage portion according to one embodiment.

Figure 26 shows another example that ontology is connected to according to one embodiment with PGC 3 terminal resistors of grid.

Figure 27, which is shown, has the ontology formed in the active region that the lower section that grid extends extends according to one embodiment Another example of 3 terminal resistors of contact portion.

Figure 28 shows another example for 3 terminal resistors for having body contacts portion according to one embodiment.

Figure 29 shows the example according to programmable 4/3 terminal resistor of one embodiment.

Figure 30 is shown can showing using the circuit for carrying out dynamic mode switching according to 4 terminal resistors of one embodiment Example.

Figure 31 shows the example for using the dynamic mode switching according to 4 terminal resistors of one embodiment.

Figure 32 A shows the example that can be carried out the circuit of dynamic mode switching according to one embodiment.

Figure 32 B shows the example of the cross section for the circuit module in Figure 32 A.

Figure 33 A shows the example that can be carried out the circuit of dynamic mode switching according to one embodiment.

Figure 33 B shows the example of the cross section for the circuit module in Figure 33 A.

Figure 34 A shows the example for being configured with the circuit of component of different public uses.

Figure 34 B shows the example according to one embodiment using the transistor group of ontology access polysilicon.

Figure 34 C shows the example according to one embodiment using the transistor group of ontology access transistor.

Figure 34 D, which is shown, uses the transistor group for having the ontology access transistor of independent interconnecting piece according to one embodiment Example.

Figure 34 E shows the example of viewgraph of cross-section corresponding with Figure 34 D.

Figure 35 shows the multi-mode switching circuit of the old-fashioned device using mixing and the new device according to one embodiment Example.

Figure 36 shows the example of another multi-mode switching circuit based on old-fashioned mode.

Figure 37 shows the example that the multi-mode switching circuit of local depletion (PD) SOI technology is based on according to one embodiment.

Figure 38 shows the example of the 6T sram cell according to one embodiment.

Figure 39 shows the example of the layout example of the 6T SRAM for Figure 38.

Figure 40 A shows the example of the cross section of the layout of Figure 39.

Figure 40 B shows the example of the three-dimensional view of 6T sram cell corresponding with Figure 39.

Figure 41 A shows the example of the top view of trap corresponding with Figure 39.

Figure 41 B shows the example that the 6T sram cell to form 2x2 array is stacked up according to one embodiment.

Figure 42 shows the layout example of the interconnecting piece trap used in combination with embodiment described herein.

Figure 43 shows the example of viewgraph of cross-section corresponding with Figure 42.

Figure 44 shows the example of the top view of the interconnecting piece trap of Figure 42.

Figure 45 shows the example that 2x2 SRAM is formed according to one embodiment.

Figure 46 shows the example that the 4x4 SRAM of the interconnecting piece unit for SPW isolation is used according to one embodiment.

Figure 47 is shown according to one embodiment for every row V_SS6T SRAM array example.

Figure 48 shows the example of the layout of sram cell corresponding with Figure 47.

Figure 49 A shows the example of the SPW and SNW of SRAM layout corresponding with Figure 48.

Figure 49 B, which is shown, has every row V according to one embodiment_SSTechnology 2x2 SRAM array.

Figure 49 C, which is shown, has every row V according to one embodiment_SSTechnology 4x4 SRAM array.

Figure 50 shows another example of the layout of sram cell corresponding with Figure 47.

Figure 51 A shows the example of the SPW and SNW of SRAM layout corresponding with Figure 50.

Figure 51 B, which is shown, has every row V according to one embodiment_SS2x2 SRAM array example.

Figure 51 C, which is shown, has every row V according to one embodiment_SS4x4 SRAM array.

The system application of Figure 52 to Figure 54 diagram the DDC device discussed herein and embodiment.

Specific embodiment

A kind of novel structure and method are provided, the wide electronic device of array and the power consumption of system are reduced.These structures and Some in method can mostly be implemented and reusing existing piece of CMOS process flow and manufacturing technology, to permit Perhaps semi-conductor industry and broader electronics industry have avoided into and have been switched to replacement technology local and riskyly.

As by discuss, some structures and methods are related to deep exhausting channel (DDC) design.DDC can allow cmos device with Traditional block CMOS, which is compared, has reduced σ VT, and can allow the threshold voltage V of the FET with dopant on channel region_T It is set to more accurate.DDC design can also have strong body effect compared with traditional block CMOS transistor, so as to allow pair Power consumption in DDC transistor carries out important dynamic control.It there is many ways in which and construct DDC to realize different benefits, and The additional structure and method presented herein can be used in combination to generate additional benefit individually or with DDC.

Also provide for transistor to be integrated in advantageous approach and structure on chip, for example including can utilize DDC with The implementation of improved chip power-consumption is provided.In addition, transistor and integrated circuit can have various other benefits in some embodiments Place, including low heat emission, improved reliability, miniaturization and/or more favorable manufacturing cost.It there are various ways with static and dynamic Some or all advantages of the prominent new transistor arrangement in ground.Many research and development at integrated circuit level are not even having this Locate also to provide advantage in the case where the novel transistor discussed.Many method and structures can be other than block CMOS transistor Type of device in use, for example, in channel and/or ontology with dopant other kinds of transistor.

Also provide in systems (such as in electronic product) combine and using innovation described herein method and Structure includes the improved power consumption for being in system level, improved system performance, changes in some implementations to provide following benefit Into system cost, improved system manufacturing capacity and/or improved system reliability.As will be shown, innovation can be advantageous Ground be used in wide scope electronic system in, including in some embodiments such as personal computer, mobile phone, TV, Digital music player, on knee and palm type calculation device, E-book reader, digital camera, GPS system, is put down at set-top box The consumer goods device of plate display, portable data storage devices and tablet computer and in various other electronic devices.? These implement in it is some in, transistor and integrated circuit can substantive Shangdi improve the operation of electronic system as a whole, And thus, improve the business suitability of the electronic system.In some embodiments, transistor is innovated, comprising described herein The integrated circuit and system of transistor can also carry out more environmentally friendly implementation than the mode of replacement.

In one embodiment, a kind of novel field effect transistor (FET) structure is provided, compared to traditional short channel device Part has the threshold voltage accurately controlled.Can also have improved mobility and other important transistor characteristics.This structure It can allow the FET transistor compared with traditional devices that there is low operation voltage with the method for manufacturing the structure.It additionally or can Selection of land, they can allow the threshold voltage of this device to be in operation controlled dynamically.FET can be in some implementations Designer provides the ability that design has the integrated circuit of FET device, quilt while which can be in circuit be in and operates Dynamically adjust.FET structure in integrated circuit can design nominal identical structure in some embodiments, and add Ground or optionally can by control, modulate or be programmed to respond to different bias voltages and grasped under different operation voltage Make.These structures can make circuit statically specify and/or dynamically change operation mode with effective and reliable way.In addition, In some implementations, these structures can be configured to manufacture after carrying out for the different application in circuit.

These and other benefits provide changing for the digital circuit for meeting many needs of designer, manufacturer and consumer Into.These benefits can be provided by that can be had to the system of integrated circuit continued and further improved novel structure forms There are the device and system for improving performance.In some implementations, block CMOS can continue the additional period, fixed to keep up with mole Rule, and based on block CMOS circuit and system in further innovation can persistently be improved with advanced performance rate.Implement Reference crystal pipe, integrated circuit, electronic system and correlation technique are described herein as by example and example, and will emphasize novel knot The feature and benefit that structure and method provide at each level of manufacture processing and trade chain (terminal user including electronic product) Place.Will demonstrate that in these examples to the application of the intrinsic principle for the structures and methods for generating integrated circuit and electronic system is It can reduce.Thus, it will be appreciated that the spirit and scope of the present invention are not limited to these embodiments and example, but only thus Locate the additional claim limitation there are also in related and commonly assigned application.

Nanoscale field-effect transistor (FET) with the grid length less than 90 nanometers is provided with than traditional nanoscale The more accurate controllable threshold voltage of FET device.Additional benefit is included improved carrier mobility and is dropped due to RDF The variation of low threshold voltage.One embodiment includes the nanoscale FET structure for being operable to have depleted region, the depletion region The depth that domain extends to below grid is set to the half greater than grid length.FET structure has at least two different doping dense The region of degree, to help to limit DDC in depleted region square under the gate.In one example, the first area near grid With the lower concentration of dopant of second area than grid following distance is separated and be located at from first area.This is provided The first pairs of low-doped channel region (in general, substantially undoped with epitaxial growth channel layer) with the second doping shielding area, The second doping shielding area can by threshold voltage or terminate when being applied to grid more greatly from the electric field of grid emission come Limit DDC.Deep depletion area can be alternatively referred to as DDC or deep depletion area, and will depend on transistor arrangement and electronics Operating condition and change in spatial dimension and characteristic.There are many having in the precise geometrical size and position of these structures and region Variation, and some be described more particularly below.

These structures and the method for manufacturing the structure allow FET transistor to have low operation compared with Conventional nano grade device Both voltage and low threshold voltage.Moreover, they allow the threshold voltage of this device to be controlled dynamically in operation. Finally, the method for these structures and manufacture structure provides the integrated circuit that design has FET device, which can be in circuit It can be dynamically adjusted while in operation.Thus, nominally the transistor in integrated circuit can design identical knot Structure, and can by control, modulate perhaps be programmed to respond to different bias voltages and in different operation electricity pressing operation or It is operated in different modes of operation in response to different bias voltage and operation voltage.In addition, these can be configured to be directed to Different application in circuit then manufactures.

Some embodiments and feature are described herein for transistor, and emphasize that novel structure and method provide transistor Feature and benefit.However, applying principle intrinsic in these examples to the structures and methods for generating integrated circuit is that can reduce , however it is not limited to transistor or block CMOS.Thus, this field will be appreciated that the spirit and scope of the present invention are not limited to these realities The claim that example is adhered in related and commonly assigned application to example or herein and also is applied, but can be advantageously It applies in other digital circuit contents.

In the following description, many concrete details are provided with the preferred embodiment that the present invention can be implemented.It is apparent that of the invention It can practice without these specific details.In other cases, well known circuit, component, operation and processing not yet It is illustrated in detail, is either not yet shown in the form of signal or block diagram with of the invention in terms of unnecessary details in order not to make It is fuzzy.Additionally, for major part, the details about material, tool, processing time, circuit layout and mold design has been saved Slightly, as long as these details need not obtain complete understanding of the invention, because they think the general technology in correlative technology field Within the scope of the understanding of personnel.Using certain terms to refer to particular system component in following entire described and claimed.Class As, it is to be understood that component can be referred to by different titles, and description herein be not intended to distinguish nominally rather than Component functionally.In following discussion and claims, term " includes " is used in a manner of open end, thus for example It is construed as meaning " including but not limited to ".

There has been described the various embodiments and example of above-mentioned method and structure.This detailed description will be recognized Only n-lustrative is not intended to be limiting in any way.Other embodiments are for being benefited the one of this field publicly disclosed herein As technical staff be easy.It reference will now be made in detail to the embodiment illustrated in the accompanying drawings.Identical reference label will be in entire attached drawing With middle use described in detail below, to refer to same or similar component.

For purposes of clarity, it is not shown and describes all general characteristics of implementation and embodiment described herein. It will be appreciated, of course, that arriving.In researching and developing any actual implementation of the invention, in order to realize the specific objective of developer, it could be made that perhaps Implement specific decision more.Furthermore, it is to be understood that arriving, this development efforts can be complicated and time-consuming, but whether how, it is pair In those of ordinary skill in the art publicly disclosed herein of being benefited be conventional engineering duty.

Will in terms of physics and functional area or layer description in the substrate or silicon layer of semiconductor injection or with The concentration that other modes exist to modify the atom of the physically and electrically characteristic of semiconductor.These can be by those skilled in the art Member is interpreted as the three dimensional mass with the material of specific mean concentration.Alternatively, they can be understood as having different or space The subregion or sublayer of the concentration of variation.They are also used as group's dopant atom, substantially similar dopant atom etc. Region or other practical embodiments and exist.Limit shape, accurate is not intended to the description in the region based on these characteristics Position or orientation.They are also not intended to for these regions or layer to be restricted to any specific type or number of processing step Mesh, the type of layer or number (for example, compound or single), semiconductor deposition, etching technique or the growth skill utilized Art.These processing may include be epitaxially formed region or atomic layer deposition, doping method for implanting or it is specific vertically or Person's transverse direction doping profile including linear, monotone increasing, retrogressing or other suitable spaces change concentration of dopant.Embodiment and The example being included therein can show particular procedure technology or used material, all as described below and in Figure 14 A- The extension illustrated in I and other processing.These examples are intended only as illustrative example, and should not be construed restricted 's.Dopant profile can have one or more different region of concentration of dopant or layer.Regardless of processing, concentration Variation and the region or layer how to limit can or cannot via include infrared spectroscopy, Rutherford backscattering (RBS), The optical technology of Secondary Ion Mass Spectrometry (SIMS) determines its of methodology using different basis weights or qualitative concentration of dopant His dopant analysis tool and detect.

Fig. 2A shows the field effect transistor (FET) configured according to one embodiment.FET100 includes gate electrode 102, source electrode 104, drain electrode 106 and the gate stack portion 108 above channel 110.Channel 110 can be looked like with deepdepletion Refer to generally from gate stack to shielding area measure channel depth it is deeply more many than traditional channel depth, this it is following more It describes in detail.In operation, bias voltage 122V_BSIt can be applied to source electrode 104, and P+ terminal 126 connects in junction 124 P-well 114 is connected to close circuit.Gate stack 108 includes grid 102, grid contact portion 118 and gate dielectric 128.Including between grid Every device 130 to separate grid from source electrode and drain electrode.Source/drain extends (SDE) 132 and extends source electrode in the lower section of medium 128 And drain electrode.

FET 100 is shown as the N-channel transistor with the source electrode and drain electrode made of N type dopant material, and shape At in the substrate as p-type doped silicon substrate, which provides the p-well 114 being formed on substrate 116.It is appreciated, however, that It arrives, by the change suitable to substrate or dopant material, substrate can be suitble to be formed with by other of such as gallium arsyl material Non-silicon P-type semiconductor transistor replace.

Source electrode 104 and drain electrode 106 can inject processing and material using traditional dopant to be formed, and may include for example Such as stress induction source/drain structures, raised and/or recessed source/drain, asymmetric doping, to doping or brilliant The source/drain of body structural modification or the repairing to the injection doping of source/drain etc. according to HDD (high doped drain electrode) technology Change.Elongated area 132 is typically incorporated in substrate, and convenient for absorbing some current potentials relevant to drain electrode.Can also use it is various its The technology of his modification source/drain operating characteristic, including source drain channel extend (end) or by source/drain (S/D) be formed about localized doping agent distribution and convenient for reducing the cyclic annular injection of the length of device channel, wherein distribution can be with Extend in the lower section of channel.In some embodiments, xenogenesis dopant material can serve as compensation dopant to modify electrical characteristic.

Gate electrode 102 can be formed by traditional material, including but not limited to certain metals, metal alloy, metal nitride and Metal silicide and its sandwich and its compound.Gate electrode 102 can also be formed by polysilicon, including for example highly doped more Crystal silicon and polycrystalline germanium-alloyed silicon.Metal or metal alloy may include containing aluminium, titanium, tantalum metal or metal alloy, or Its nitride of person, the compound containing titanium including such as titanium nitride.The formation of gate electrode 102 can include silicide method, change Learn vapor deposition method and physical gas-phase deposite method, such as, but not limited to vaporization method and sputtering method.In general, gate electrode 102 have from about 1 to about 500 nanometer of integral thickness.

Gate dielectric 128 may include traditional dielectric material of such as oxide, nitride or nitrogen oxides.It is optional Ground, gate dielectric 128 can generally comprise higher dielectric constant dielectric material, including but not limited to hafnium oxide, hafnium suicide, oxygen Change zirconium, lanthana, titanium oxide, barium strontium titanate and lead zirconium titanate, metal-based medium material and the other materials with dielectric property. It include preferably HfO containing hafnium oxide₂, HfZrOx, HfSiOx, HfTiOx, HfAlOx etc..Depending on ingredient and available heavy Product processing equipment, gate dielectric 128 can pass through such as hot or plasma oxidation method, nitriding method, chemical gaseous phase Deposition method (including Atomic layer deposition method) and physical gas-phase deposite method are formed.In some embodiments, it can be used Multiple or composite layer, laminated body or composite construction.For example, gate dielectric can by with thickness between about 0.3 and 1nm SiO₂The hafnium oxide based insulation body of based insulation body and thickness between 0.5 and 4nm is formed.In general, gate dielectric has from about 0.5 To about 5 nanometers of integral thickness.

Below gate dielectric 128, channel region 110 is formed in the top of shielded layer 112, and channel region 110 contacts source Pole 104 and drain electrode 112 simultaneously extend between source electrode 104 and drain electrode 106.Preferably, channel region includes substantially undoped silicon, Perhaps the advanced material such as from SiGe race or it is doped to the silicon of very low level.Channel thickness can usually received from 5 to 50 The range of rice.

Following discussion will focus on block cmos device.In many nanoscale block CMOS FET devices, carrier mobility By set threshold voltage V_TThe high concentration of required channel dopant adversely affects.It can prevent to show in high dopant level While the power leakage of work, when dopant occurs with high concentration, they may be used as greatly reducing the shifting of such as electronics The scattering center of the channel mobility of mobile carriers.In the case, the electron scattering in channel region, and cannot be effectively The mobile space by between source electrode and drain electrode.Effectively, which has limited the maximum amount of electric current (I that channel can carry_dsat).This Outside, very thin grid and the high electric field obtained at gate dielectric/channel interface will lead to serious quantum mechanical effects, the effect It should reduce to the inversion layer charge density under gate voltage, and the reduction of inversion layer charge density and mobility and threshold voltage V_T Size increase it is related, thus, again reduce the performance of device.Due to these characteristics, traditionally by block cmos device It narrows down to the smaller size of expectation and is considered more and more difficult.

As additional benefit, substantially the use undoped with channel region can enhance commonly used to improve transistor performance The validity of certain traditional technologies.For example, the source electrode 104 and drain electrode 106 that are located in the opposite sides of channel region 110 can construct The stress applied on channel region at modification.Optionally, channel region can be by by the SiGe of Lattice Matching and strain (SiGe) crystalline solid film lattice is arranged to cause the strain compressed on direction in the face of channel and modify.This can be caused The variation of band structure, so that the mobility in hole increases compared with intrinsic silicon.Stress condition can be by changing germanium (Ge) ingredient Modification (higher germanium increase strain, and the mobility in hole becomes higher).For elongation strain, channel region Si can be formed On the lattice constant SiGe with bigger lattice constant.This causes the electron mobility compared with unstrained Si channel region All increase with hole mobility.Again, as the germanium ingredient of matrix SiGe increases, dependent variable in the Si channel region of strain and Carrier mobility tends to increase.It arrives as will be appreciated, puts stress upon channel region and do not require continuous stressor layers, and is discontinuous Either compression or drawing force cannot be applied to the various positions along logical channel region by multiple individual stressor layers, including be answered Power layer top, lower section, lateral arrangement or abutting, to effectively allow to carry out bigger control to the stress of application.

In some embodiments, stressor layers can indicate compatibly to apply stress when or abutting adjacent with channel applies It is added to the layer of any material of channel region.As an example, in a particular embodiment, stressor layers may include having and half The material of some or all different coefficient of thermal expansions of the remainder of conductor.In the manufacturing process of this embodiment, with The temperature of semiconductor substrate reduces, and certain parts are differentially shunk, and causes the stretching, extension or contraction of channel region.As a result, ditch At least part in road region can become to strain, and improve the mobility of carrier.In a particular embodiment, stressor layers can be with Including having the material of such as silicon nitride of some or all bigger thermal expansion coefficients than semiconductor substrate.Additionally or Optionally, different stressor layers can be applied to the different piece of FET 100, with selectively improve in channel region hole or The mobility of electronics.For example, in a particular embodiment, in complementary n-type and p-type transistor to via suitable p-type and N-shaped trap knot Structure and in the case where being isolated from each other, stressor layers can be applied to n-type transistor so that tensile stress to be applied to the ditch of n-type transistor Road region.This tensile stress can induce the strain in channel region, which improves mobility of the electronics by channel region. Another stressor layers can be applied to p-type transistor so that compression stress to be applied to the channel region of p-type transistor.This compression stress The strain in p-type channel region can be induced, this strain improves the mobilities in hole.

Being arranged has the advantages that substantially the transistor undoped with channel brings other when applying stress.For example, stress can be with Apply and via the compression or tensile stress of source/drain or the application of channel stress technology.Have with traditional Even or high doped channel nanoscale transistors are compared, and the channel region FET transistor of strain is attached due to gate dielectric The dopant (reducing ionized impurity scattering) of nearly low concentration and lower electric field (reducing surface roughness scattering) will provide bigger Enhanced strain mobility.Due to reduced scattering, stress enhances mobility will be greater than conventional apparatus significantly.Due to strain This obtained mobility advantage will decline with the size scale of transistor and actually increase.

Fig. 2A is the schematic diagram according to the transistor of one embodiment construction.Fig. 2 B, 2C and 2D are that further diagram DDC is brilliant Three exemplary schematic diagrames of difference in body pipe trench road, DDC transistor channel can be exchanged with the channel 110 of Fig. 2A.Different areas Domain may include positioned at gate dielectric (medium 128 shown in such as Fig. 2A), threshold voltage adjustments region and high doped shielding The deepdepletion region of areas adjacent.Fig. 2 B diagram is next to two regions that gate dielectric positions and has doping concentration different DDC transistor channel section an example.The profile of this channels cross-section includes being located at gate dielectric (not shown) and screen Cover the depleted region 202 between region 204.Foreign atom 206 is illustrated, the concentration of dopant in shielding area 204 with compare It is corresponding in the opposite dopant atom density of shielding area 204 exhausted in channel region 202.

Fig. 2 C shows another example of channel region 208, three regions which has concentration of dopant different.? In this example, exhaust dopant channel region 214 have minimum dopant 206, threshold adjustment region domain 212 generally have than The dopant atom of 214 higher concentration of dopant channel region is exhausted, and shielding area 210 has the doping of highest concentration Agent atom.

Fig. 2 D shows another variation, and wherein channels cross-section has the dopant atom increased from top channel to bottom channel Concentration 224.In different applications and embodiment, the dopant range at the top of channel can change, as long as but will usually locate Reason and annealing conditions allow just towards being lower at the top of channel.Dopant range towards the center of channel, which can increase, passes through channel Bottom, with enter have more high dopant shielding area.

In in these construction any one, threshold voltage adjustments region can be formed as the silicon layer of independent epitaxial growth, or Person is formed as further including a part for exhausting the single silicon epitaxy layer of channel region.Threshold adjustment region domain thickness usually can be from 5 To in the range of 50 nano thickness.When substantially undoped with when, be suitble to selection region itself thickness slightly adjusting threshold voltage, together When for many common applications, threshold voltage adjustments region be doped with range in 5x10¹⁷And 2x10¹⁹Atom (atoms)/cm³Between mean concentration.In certain embodiments, the dopant migration barrier layer of carbon, germanium etc. can be coated in threshold The top and/or lower section of threshold voltage adjustment region are to prevent dopant from moving in channel region or optionally, prevent screen It covers region and enters threshold voltage adjustments region.

If provided, then shielding area is that the height being embedded in below channel region and threshold voltage adjustments region is mixed Miscellaneous region.Shielded layer is generally positioned at a certain distance to avoid directly contacting with source electrode and drain electrode.In other certain implementations In example, it can be formed as the plate extended in the lower section of multiple source/drain/channel regions, while in other embodiments, it It can be autoregistration infusion or the layer coextended with channel region.Shielding area thickness is usually from 5 to 50 nanometer In range.Shielding area is relative to channel, threshold voltage regions (if provided) and p-well high doped.In practice, shield Region is covered to be doped to have in 1x10¹⁸And 1x10²⁰Atom/cm³Between concentration.In certain embodiments, carbon, germanium etc. are mixed Miscellaneous dose of migration barrier layer can be coated in the top of shielding area to prevent dopant from moving in threshold voltage adjustments region.

In operation, when the predetermined voltage for being greater than threshold voltage is applied to conductive grid, deepdepletion region is formed in Between gate stack and shielding area.Below conductive grid, deepdepletion region is typically extended down in shielding area, no It crosses in certain high doped embodiments, deepdepletion region can terminate in threshold voltage adjustments region, provided that Words.It arrives as will be appreciated, the accurate depth below the conductive grid of depleted region is true by that can design many factors adjusted by FET It is fixed.For example, depleted region depth can be true by the absolute of the other elements of space orientation and FET or opposite concentration of dopant It is fixed.For example, FET can have between source region and drain region and with grid length L_GGrid below limit Channel.DDC depth (X_d) can be set as than grid length one it is medium-sized may be grid length half multiple, or and its It is proportional.In one example, this DDC depth can be set as the half for being approximately equal to channel length, this allows i.e. in operation Making under the low operating voltage under one volt also can accurately set threshold voltage.It is different depending on the requirement of specific application Depth can provide different beneficial outcomes.It is disclosed down, it will be appreciated that different DDC depth are in different applications, different It is feasible in the various parameters of device geometries and particular design.Depending on the parameter of specific application, DDC crystal is being formed Different zones thickness, concentration of dopant and operating condition used in pipe can provide different beneficial outcomes.

For example, according to another embodiment, depletion depth can be maintained from 1/3 grid length to the depth for being approximately equal to grid length Degree.However, arriving as skilled in the art will appreciate, if transistor structurally and operationally becomes less than depletion depth The half of grid length, then device will run down in the performance of power consumption, and the benefit of DDC will disappear.When exhausting depth Spend X_dWhen between the 1/3 of grid length and 1/2, such as, square depletion depth is set as about DDC transistor under the gate 0.4×L_G, device can also be relative to the improvement of traditional devices realization optimum.In this example, shielding area is suitble to Thickness range is between 5 to 50 nanometers, and dopant concentration range is from 1x10¹⁸To 1x10²⁰Atom/cm³.For threshold voltage tune The suitable thickness range in region is saved 5 between 50nm, and dopant concentration range is from 5x10¹⁷And 2x10¹⁹Atom/cm³.Not Doped channel region is selected to select relatively deeply sufficiently to meet Xd > 1/2 × L_GConstraint, and have be less than 5x10¹⁷Atom/cm³'s Concentration.

There are multiple transistors in fact, provide deepdepletion region for DDC transistor and can allow to tighten setting significantly With the tolerance of the threshold voltage of the circuit of related device, and the variation due to caused by RDF can be further decreased.As a result, can be Setting on multiple devices in integrated circuit more can predict and more reliable threshold voltage.This benefit can be used to reduce device or Power in system, and better overall performance can be caused.

Potential other benefits of this embodiment are adjustable threshold voltages, can be configured with one or more Static settings or dynamically changeable in a described device of transistor arrangement or the operating process of system.Also in fig. 2 Diagram, bias voltage can be applied on transistor source 104, and be applied to the opposite charges dopant material connecting with p-well 114 126.Traditional circuit, which is generally increased by, is biased into supply voltage, so that electric current can be from source electrode when operation voltage is applied to grid Flow to drain electrode.While having proposed to be biased to dynamically set threshold voltage using adjustable body before, it is generally not yet Proof can be practical, thus tends to induce chip area punishment, thus forbids the level integrated on chip.According to this embodiment, electric Road can be configured to change transistor by the bias voltage that change is applied to trap (to be transistor if the trap of share common Group) threshold voltage, constructed in an integrated circuit or system but regardless of them or individually in circuit.As below into One step detailed description is reliably punished by threshold voltage ability of the control in close range and with reduced chip area Ability that is reliable and dynamically changing threshold voltage with leading to device or system dynamic changer during being operated Transistor or the operation mode of transistor group in part or system.

Fig. 3 shows the relationship of dopant atom concentration and gate dielectric lower channels depth to illustrate for according to one Figure 30 0 of various depth bounds dopant concentration ranges in the channel of embodiment.Two curves, a song more practiced are shown Line 308 and an ideal curve 310.As can be seen, three levels are shown: the first 5-20 nanometers channel region, from channel region The shielding area in the threshold voltage adjustments region for the 5-20 nanometer being close to and the 5-20 nanometer being close to from threshold voltage adjustments region. The concentration of different level respectively reaches some level 312,314,316, may still need not be in the figure at respective concentration level Inflection point, and these correspond to channel dopant concentration " d " be less than 5x10¹⁷Certain dopant concentration level 302, threshold voltage Adjustment region concentration " d " is in 5x10¹⁷And 5x10¹⁸Between level 304 and shielding area concentration of dopant be greater than 5x10¹⁸Atom/ cm³Level 306.According to some embodiments, in these dopant concentration ranges, it is able to achieve and is supporting deepdepletion region Some best benefits in the nanoscale FET of operation.

Dopant profile according to various embodiments, which is defined so that, generates three regions.These three regions are in table 1 It limits, region 1 corresponds to the channel region near gate dielectric, and region 2 corresponds to threshold voltage adjustments region, and area Domain 3 corresponds to shielded layer, and wherein, L_GIt is grid length.As can it is understood that grid length is substantially equal to channel length, and And t₁、t₂And t₃It is trizonal respective length.Each of these regions can be via representative thickness and being measured as often standing The dopant dosage of square centimetre of atomicity indicates.The value of these thickness and dosage is given in Table 1.

Table 1

Thickness degree is the technique depending on processing node, and each thickness t₁、t₂And t₃With the grid length of device (L_G) related to processing node of interest.Table 2 includes to be directed to 90 nanometers of representative numbers to 15 nanometered disposal nodes, diagram On the thickness requirement in region reduce L_GEffect.

Table 2

Fig. 4 is different boron dope agent atom/cm of the device depth in being implemented according to example³Variation Figure 40 0.Herein In example, concentration of dopant under from zero to about 20 nanometer (nm) of depth at low-doped dose of region of proximate transistor gates most It is low (to be less than 1x10¹⁷), and in threshold voltage adjustments region (the about 5x10 from about 20nm to 45nm¹⁸) at it is slightly higher.This example exists Higher (about 5x10 is reached from the shielding area of about 45nm to 75nm¹⁹).This particular example shows three different analog device (its It is shown as the stacked figure completed with different processing).One uses annealing in 15 seconds at 975 DEG C, and one makes at 800 DEG C It was annealed with 15 seconds, and third is completely without using annealing.The result of figure is substantially similar, illustrates and adulterates under different disposal environment The reliability of agent concentration.It will be appreciated by persons skilled in the art that different design parameters and application can require doping concentration not The different variations in same region or number.

In practice, the sample of designer and manufacturer from mathematical model and from actual circuit measures collection of statistical data, To determine the variance of the threshold voltage of circuit design.It is obtained in spite of from manufacture variance or RDF, voltage difference between transistor Mismatch is determined as σ V_T.The refinement figure of the relationship of different threshold voltages and supply voltage of the diagram from various devices in Fig. 5 (rendering) a example.In order to operate circuit as a whole, voltage V is operated_DDσ V must be taken into consideration_TTo select.One As, variance is bigger, σ V_TIt is higher, so that operation voltage V_DDMust be higher for transistor setting, compatibly to operate.Benefit It is needed to operate circuit compatibly by V with the multiple devices implemented on circuit_DDIt is set as highest integral value.

The structures and methods of its product are provided, σ V is reduced_T, to reduce the threshold voltage of transistor on the integrated Variance range.Utilize reduced σ V_T, V_TQuiescent value can be set to it is more accurate, and even can be in response to the bias of variation Voltage and change.According to the improved σ V of one embodiment_TThe reflection of one example is in fig. 6 it is shown that by from different devices The lower variance for the threshold voltage that part is taken is evident that the improvement threshold of threshold voltage refinement figure (rendering).On circuit Reduced σ V can be used more accurately for the threshold voltage of nominally identical device_TSetting, thus device is allowed to use lower operation Voltage V_DDOperation, and thus, consume less power.Moreover, using more headrooms with for given transistor or Person's transistor group changes V_T, device can from operated under the corresponding different mode of different bias voltages for AD HOC.This Many devices and system can be increased functional and outstanding in the case where the subtle control to device power mode is useful It is beneficial to device.

Fig. 7 A shows the example of the transistor 700 according to conventional process and structure manufacture.This example is illustrated as N-type FET, With source electrode 702, drain electrode 704 and the gate stack portion including conductive grid 706 and insulating layer 708.In general, grid 706 is by height Degree DOPOS doped polycrystalline silicon is formed, and insulating layer is formed by the gate dielectric of such as silica.706 electric control of gate stack portion is in source The electric current flowed between pole 702 and drain electrode 704.Channel 710 generally includes dopant, and extends downwardly into p-well 712, and can To be wound around source electrode and drain electrode.Channel depth X_d714 be the distance from gate dielectric 708 down to the bottom of channel 720.? In operation, there are many such as E 716 extended downwardly along this channel depth 714 and towards source electrode 702 and drain electrode it is 704 curved Multiple electric field lines.These field wires are not usually straight as illustrated in the drawing, but are bent due to device configuration and operation.It is all Such as electronics e^-The carrier of 718 movement is advanced between source electrode 702 and drain electrode 704 by electric field E 716.Also illustrate grid Spacer 724 and SDE 722.

On the contrary, Fig. 7 B, which is shown, firmly gets the DDC crystalline substance that more depleted regions is operated with the traditional devices 700 compared to Fig. 7 A The embodiment of body pipe 700 '.This provides the feature and benefit of the improved mobility without using stress inducing layer, It is arranged with improved threshold voltage.This example is illustrated as N-type FET, has source electrode 702 ', drain electrode 704 ' and grid 706 '.Crystal Pipe includes the grid 706 ' being formed on gate dielectric 708 ', when grid to source voltage is biased into greater than threshold voltage, Depleted region 710 ' is formed, and controls the electric current flowed between source electrode 702 ' and drain electrode 704 '.Depleted region 710 ' is to downward The shielded layer 720 ' as the layer injection in p-well 712 ' is reached, and as can be seen can be around source electrode 702 ' and drain electrode 704 ' two Person's winding.Gate spacer device 724 ', 720 ' and SDE722 ' are also illustrated.Depletion depth X_d' 714 ' are downward from gate dielectric To the distance of shielding area 720 ', and it is deeply more many than the depleted region of traditional device of Fig. 7 A.It is traditional unlike Fig. 7 A Device, the offer that the shielding area 720 ' in device 700 ' is the electric field E 716 ' for such as extending downwardly into shielded layer are heavily doped It terminates.Deeper exhausting X_dIn the case where ' 714 ', these field wires are generally than electric field E 716 those of in traditional structure 700 It is longer and more straight.Similar to traditional device, when bias, electric current flows to drain electrode 704 ', and electronics e from source electrode 702 '^- 718 ' are advanced between drain electrode 704 ' and source electrode 702 ' by electric field E 716 '.However, electronics is freer compared to traditional devices Ground flowing in these electric fields E 716 ', provides improved electric current flowing and better performance.In addition, this configuration passes through reduction Channelling effect is held, reduces the variation due to caused by the fluctuation of any dopant to improve σ V_T。

The traditional structure corresponding to Fig. 7 A diagram is shown referring to Fig. 8 A, FET800.Leakage occurs in entire transistor arrangement Various positions at, even if when FET do not switch actively when also result in power loss.The specifically depicted source electrode 702 of Fig. 8 A and trap The principle of the leakage occurred between 712.Since cation 802 stays in trap 712, they tend to via leakage paths X_j806 move Move on to hole 804.In the case where relatively short path 804, leak commonplace in traditional nanoscale devices.

Fig. 8 B shows the FET 800 ' operated with the deep depletion area for being similar to Fig. 7 B diagram, and is also shown in source electrode The principle of the leakage occurred between 702 ' and trap 712 '.Cation 802 ' stays in trap 712 '.However, using having more deep trap Innovative construction, path X_j806 ' is significantly longer, and they tend to via leakage paths X_j' 806 ' less move to sky Cave 804 '.In the case where relatively long path 806 ', leak less universal compared to traditional devices here.In addition, new Existing fringing field E 716 ' in clever structure and in the case where the leakage at grid 706 ' and 708 ' place of insulator, the ability of excited electrons It is reduced significantly.The result is that the leakage at grid substantially reduces.Thus, the novel structure with DDC is provided in tradition The significant decrease for the leakage that many positions of device occur.

DDC transistor preferably provides improved carrier mobility, and (it is the spy greatly paid close attention in the sector Sign).Mobility is quantitative measurment when greater than threshold voltage V_TVoltage when being applied to grid carrier from source electrode cross transistor Channel is moved to the transfer ability of drain electrode.One target of best device is that the electric field applied generally according to grid is moved with what is measured Relationship (being known as universal mobility curve) between shifting rate makes electronics or mobile carrier hinder to move from source electrode with the smallest Move drain electrode.This universal mobility curve is carrier mobility and the induction inversion region in the inversion region of channel The visible relationship well established in a mosfet between electric field (or inversion charge).Fig. 9 is shown for NMOS transistor Master curve (solid line), but there is also similar curves for PMOS.In this figure, it depicts for undoped ditch The universal mobility curve in road.Region A corresponds to mobility/electric field operation of the usual current status of technology mosfet transistor Situation, and the mobility for illustrating these devices to deteriorate relative to the mobility in existing fringing field/low power section is in high power It is operated in region.

Second mobility curve (dotted line) be suitable for high doped channel (be frequently necessary to compensation reduce effect) and at The grid voltage of ratio reduced downwards and the nanoscale grid length transistor of consequential existing fringing field.These curves can be It supports to match under the operating condition of the high electric field in channel, because mobility is by the interface phase between gate dielectric and channel silicon The surface roughness of pass dominates.When operating transistor with low grid voltage (and consequential existing fringing field), the two are bent Line scatters (commonly known as ionized impurity due to the presence of dopant atom and to the channel dopant for being used to reduce electron mobility Scattering) carry out domination and disagreement.This can be visible as region C.Can construct with fall in the C of region electric field operation it is low While power device, required high channel doping due in Fig. 9 with the dopant scattering in the region of region A label and Cause the deterioration of mobility.

The operating point of DDC transistor is arranged as shown in the region B in Fig. 9 along universal mobility curve.DDC transistor is not It is only operated under the low power condition of existing fringing field, and benefits to become and scatter with substantially low-doped dose to reduce its mobility Deepdepletion device.DDC transistor is thus able to achieve height relative to traditional high-power component in some preferred embodiments Up to 120% Enhanced mobility.

Using these novel structures and the method for forming them, circuit, which can be produced now and is configured with, dynamically changes V_T's Ability.Compared to traditional devices, which is preferably configured with small σ V_T, assigning the device not only has low nominal threshold voltage V_T With low operating voltage V_DDAbility, also have can change in response to bias voltage it is accurate be adjusted V_TAbility.It is grasping In work, bias voltage can be arranged in operation to raise and reduce the V of device_TTransistor on.This enable circuit with effectively and Reliable way is (especially if operation voltage V_DDAlso it is controlled dynamically) statically specify and/or dynamically change operation mould Formula.In addition, V_TAdjusting can be complete on one or more transistor, the different piece of transistor group and circuit or region At.This breakthrough enables designer to use the universal transistor that can be adjusted to play different function in circuit.Additionally, Circuit caused by there are many feature and the benefit as these integrated circuit structures and system level innovation.

In one embodiment, semiconductor structure is provided with the DDC with DDC depth, wherein channel is formed in source area Between domain and drain region.In one example, DDC depth is at least the one medium-sized of the channel length of device.These structure energy In the electric pressing operation lower than traditional devices, do not limited by the effect of the RDF in device channel.Novel structure can also use Traditional block CMOS handling implement and processing step manufacture.

According to one embodiment, the channel region of transistor can be configured with the multiple regions with different dopant concentration. In one example, there are the lower sections of grid at three different zones are made for DDC transistor configurations.It advances deeply from gate dielectric Into substrate, these regions include channel, threshold voltage adjustments region and shielding area.It will be appreciated by persons skilled in the art that The various combination in these regions or arrangement may exist.

Channel region is the region that minority carrier advances to drain electrode from source electrode in the operating process of integrated circuit.This structure At the electric current for flowing through device.The amount of dopant in the region influences device via the mobility of impurity scattering.Lower mixes Miscellaneous dose of concentration causes higher mobility.Additionally, RDF reduces also as concentration of dopant and is reduced.This is undoped with (low-mix It is miscellaneous) channel region can allow DDC transistor realize both high mobility and low RDF.

Threshold voltage adjustments region allows the complementary doping of the P-type dopant in the N type dopant and NMOS of such as PMOS Agent is introduced into the lower section of channel region.Introduce this V of the proximal end and dopant level of being coupled to channel region_TAdjustment region is preferred Ground allows threshold voltage adjustments region to change the depleted region in channel in the case where not direct doped channel.This exhausts control Allow to change the V of device_TTo realize desired result.Additionally, V_TAdjustment region can assist preventing sub-channel from running through and leaking. In some embodiments, this provides improved short-channel effect, DIBL and sub- threshold value slope.

In conventional process, other cope with the measurement of the different performance of transistor by change specific structure and concentration. For example, gate metal alloy or polysilicon can be used to adjust doping concentration to improve short-channel effect or other parameters. The gate dielectric below grid and above channel can also be adjusted.There is also can set in the channel of transistor or surrounding Concentration of dopant other processing.Trial unlike improving the other parameters of short-channel effect and device before these, herein Some embodiments of description not only improve the multiple parameters of device, but also they can also be improved to the essence of device setting threshold voltage Exactness and reliability.In addition, in some implementations, improved device can also carry out dynamic control to the threshold voltage of device to increase Epistasis energy, and the new feature and operation of device or system is also provided when employed.

In one embodiment, transistor device is provided with from the channel top near grid down to the dullness in channel Increase concentration of dopant.In one example, there is the linear increase from gate dielectric dopant.This can be by away from grid At a certain distance from formed shielding area and between shielding area and grid have depleted region and complete.Depleted region can adopt Different forms is taken, one or more region including different dopant concentration.These regions are dedicated to transistor device It is different improve, including improving the reliability of setting particular threshold voltage, improving the mobility of transistor channel, and dynamic tune Threshold voltage is saved to improve and expand the different operation modes of device.These concentration of dopant can be with all as shown in Figure 4 and to device The concentration map that the channel depth of part is described indicates that it passes through different layers since at the top of the structure near grid Pass downwardly through shielded layer.

It exhausts channel region and provides the region for electronics to be freely moved to drain electrode from the source electrode of transistor, thus mention High mobility and overall performance.Threshold voltage adjustments region is used in combination to set the nominal intrinsic threshold of device with shielding area Threshold voltage.Shielding area is the high doped regions for increasing the system number of FET device.Higher system number allow body bias with Change the bigger effect of the threshold voltage of FET with dynamic.These three regions can coordinate for realizing multiple dedicated devices.Two A or trizonal multiple combinations can be used to realize various design benefits.For example, all areas can be with more or belt edge Metal gates are used together to realize with various intrinsic V_TThe low-power device of value (being realized by threshold voltage adjustments doping) Part and the dynamic mode of operation (via body effect).

Channel and shielding area can be used in conjunction with intermediate gap metal gate stacks to realize ultra-low power devices (in wherein, Gap metal is used to fully exhaust channel in the case where the auxiliary in no threshold voltage adjustments region).Channel and blind zone Domain alternately can combine double work function metal gate stack to use to realize ultra-low power devices.In addition, can be in a plurality of ways Realize the formation in these regions.In some implementations, single extension process, thus doped in situ control during the growth process can be used Desired profile is realized in the case where making and being modulated at not additional injection, and undoped with multiple injections after epitaxial region It can be used to realize the profile.It is alternatively possible to use double extension processes with the injection similar to expectation concentration.Alternatively, by The extension of any number of concentration and multiple extension processes of injection composition can be used to realize desired profile.However, such Change the spirit and scope without departing from claims.

In another example of device, other than forming the region DDC on substrate, oxide areas or other grid Pole insulator is additionally formed in the top of channel region on the top of substrate.Device may include being formed in oxide areas Metal gates region.The device obtained in this example is that have the controllable threshold voltage of dynamic but still in channel region The insensitive transistor of RDF.In this example, in operation, the region DDC has very low σ V_T, and low V_DDDepth is consumed Leakage to the greatest extent in region keeps lower.It is furthermore possible to also provide injection so that old-fashioned device can require transistor with one volt with On operated.

In the following example, various device configurations, the system in conjunction with this device and manufacture this device and system side Method is discussed and is illustrated further in attached drawing.These examples with the device, system and manufacture the system and system method neck The illustration diagram that the technical staff in domain is well understood.These examples are together with the feasible and possible operation to following system Characteristic and performance are described to describe the details with illustrated device.

With traditional structure it is further compared with illustrate in Figure 10 and Figure 11.Figure 10 diagram has low-doped channel (about 1x10¹⁷Atom/cm³) DDC transistor and the similarly sized tradition with uniformly doped channel (do not have shielding area) it is brilliant Example between the threshold voltage and body bias of body pipe compares.As can be seen, even if DDC transistor does not have strong ontology coefficient institute It is required that significant channel dopant, by DDC body bias carry out threshold voltage modulation be also comparable to Uniform Doped ditch Road MOS.

Thus, in a particular embodiment, DDC structure can provide current only in long channel device in short channel device The comparable benefit realized in (it is unpractical that it, which replaces short channel device).1, σ V referring to Fig.1_TCompared with body bias Example compared to DDC device is shown for uniform channel MOS device.It is significant to deteriorate for short channel device and long ditch logos and utensils The threshold voltage of part is obvious.In this DDC device, there are the obvious less deteriorations of threshold voltage, and body bias voltage increases Greatly.This reduce is promoted by the high doped shielding area for greatly reducing short-channel effect.

As discussed in the background, certain transistors can be formed having according to super steep retrogressing trap (SSRW) profile and The channel layer of doping.This technology is using specific doping profile to form heavily doped region in the lower section of lightly doped channel. Referring to Fig.1 2, the comparison of the example of DDC structure and the profile of tradition SSRW is shown.As can be seen, SSRW is in, restriction adjacent with channel The transistor gate proximate dielectric at the top of channel (not shown) has very high concentration of dopant.It is attached in channel and gate dielectric Close this high doped concentration typically results in leaking performance poor in traditional devices, and and the method is being narrowed down to nanometer There are exceptional hardships in terms of grade grid length transistor.Thus, it does not give the power for reducing electronic device generally and improves its performance Whole need to provide suitable business solutions.The embodiment of DDC transistor can include the channel of deepdepletion, and further include Shielding area that is heavily doped and being separated from channel.This structure can provide circuit performance significant improvement, and can ratio The circuit for implementing SSRW more simply produces.

Many traditional cmos manufacture processing can be used to manufacture DDC transistor.Figure 13 is the tradition for manufacturing traditional devices CMOS handles compared with the structure constructed according to disclosed embodiments 1300 schematic diagram.The one of novel cmos device In a embodiment, shallow trench isolation (STI) 1302,1302A, trap and Channeling implantation portion 1304,1304A, contact portion 1308, 1308A and the relevant processing step of metal interconnection 1310,1310A can standardize.Only traditional CMOS gate stacking processing 1306 is different from the gate stack 1306A of improved structure.This is provided significantly to introduce the novel CMOS structure of such as DDC device The advantages of.Mainly, the requirement for the dangerous or expensive new processing step that this avoids research and development for manufacturing new device. Thus, existing manufacture processing and the relevant library IP can be reused, cost has been saved and has allowed manufacturer quickly will be this Novel and advanced device brings market into.

It will be formed not on the top in high doped N-type and p type island region domain according to the exemplary DDC transistor processing in Figure 13 Doped epitaxial silicon area is to form DDC doping profile.It can be device performance in some implementations undoped with epitaxial silicon regions thickness Significant factor.In another example, double epitaxial silicon regions have height, moderate and low dosed (or do not mix for providing It is miscellaneous) final gate stack.Optionally, the final heap for having a high doped regions near substrate level can be formed A folded epitaxial silicon regions, subsequently form moderate to the epitaxial growth between low dosed grid and high doped shielding area Layer.Dopant migration or diffusion between layer in order to prevent can stop skill using the migration of various dopants in some implementations Art or layer.For example, carbon doping can be used to reduce boron (B) and spread in p-type epitaxial silicon.However, in N-type epitaxial silicon, carbon Negative effect can be doped with to As.Carbon can be located at entire silicon epitaxy or be restricted to the thin region of each interface.It can be with Use site doped carbon or the carbon of injection.If use site doped carbon, carbon can be appeared in both V-type and p-type.If Carbon injection, in some embodiments, it can solely be used in p-type.

DDC transistor can use available piece of CMOS processing technique and be formed, including stop for depositing dopant migration Technology, advanced outer layer growth, ALD or the advanced CVD and PVD of layer or annealing, these can be in Advanced Integrated Circuits It is used in processing node technology (technology of such as 65nm, 45 your nm, 32nm and 22nm).Although these processing nodes generally for STI isolation, grid processing and annealing have low heat budget, but they remain suitable for the formation of DDC transistor.

Figure 14 A to Figure 14 I shows the process flow of the device for manufacturing the channel with DDC doping profile.These How the example of the manufacture of two devices of drawing illustration is to show NMOS and PMOS transistor respectively configured with DDC and shielding area To provide the advanced and operation of novelty DDC transistor and device.Structure in each step is shown in a sequential manner To illustrate the sample process for forming the two transistor devices.Optionally, other process flows can be used to manufacture DDC device, And this specific processing and correlation step are shown for illustration purposes.Processing is to form, deposit or in other manners Be made further include to form the term in " region " of transistor arrangement and be described, but be intended to different shape, size, depth, The region and different form of width and height or profile or layer.

Firstly, 4A referring to Fig.1, structure 1400 is started with the substrate of such as P type substrate 1406.NMOS or PMOS device It can be formed in P type substrate.For simplicity and in order to describe possible embodiment and example in these and other attached drawings, for NMOS and PMOS device are together with the process flow that the example of the shallow and local trench isolations of certain character separations is described to DDC device Example.In any case, to other disclosed in structure or the relevant corresponding process of device will readily appreciate that.In addition, although not It shows, these processing can be executed with various technologies commonly known in the art, such as be made used in the mask side by side formed in structure For the region of different zones and formation on top of each other.

Selectable N trap injection unit 1402 and p-well injection unit 1404 are formed on p-substrate 1406.Then, shallow p-well injection Portion 1408 is formed on N trap 1402, and shallow N trap injection unit 1410 is formed in p-well 1404.These different regions can lead to Then the injection of the first N trap will be carried out to N trap 1402 using photoresist in oxide pad formation to substrate P 1406 first by crossing carrys out shape At.P-well 1404 can be injected with another photoresist.Shallow N trap 1410 can be formed by being injected with another photoresist. Then shallow p-well 1408 can be injected with another photoresist.Then, processing heel is with annealing.

Proceed to Figure 14 B, NMOS RDF shielding area 1412 is formed in the continuation of the processing in shallow p-well 1408.According to this reality Apply example, the region NMOS RDF 1412 be such as before in order to reduce RDF and provide improved threshold voltage setting and reliability The shielding area of many benefits and the high dopant described to can be carried out the threshold voltage of dynamic regulation transistor.This Shielding area can be formed as the RDF carried out using another photoresist shielding injection.The formation of PMOS RDF shielding area 1414 In the top of shallow N trap 1410.This region can be formed as the PMOS RDF carried out using another photoresist shielding injection.

Referring next to Figure 14 C, after initial oxide removal, NMOS threshold voltage adjustments region 1416 uses photoresist It is formed on shielding area 1412, wherein the method for epitaxial growth or other similar technology can be used to deposit this threshold value electricity Press adjustment region.Similarly, PMOS threshold voltage adjustments region 1418 is formed in PMOS RDF shielding area using photoresist 1414 top.The every of threshold voltage adjustments region is subsequently deposited upon undoped with region or low dosed region 1420,1422 On a, threshold voltage adjustments region is entrained in NMOS V_TAdjustment region 1416 and PMOS V_TThe top of adjustment region 1418.It can These undoped or low dosed regions are deposited to use the method for epitaxial growth or other similar technology.By above Step forms the channel for meeting DDC.Although forming the phase using two epitaxial regions in these examples to be directed to each transistor The DDC profile of prestige, but single epitaxial region may be also used on each to form DDC device.

Device is prepared and forming channel for subsequent two transistors of manufacture for the above process flow or other are more multiple The processing on strays road.However, following process flow discloses the n-channel and p-channel for being used to form and illustrating in Figure 14 D to Figure 14 E The example of remaining step of transistor.

4D referring to Fig.1, then by applying shallow trench isolation (STI) processing with shape from adjacent transistor isolated transistor At STI transistor boundary.Herein, the depth of each STI 1424,1426 and 1428 is compatibly set, so that STI will enter p-well In.As can be seen, sti trench slot extends below each shallow p-well and shallow N trap 1410.This allows to improve the isolation between transistor.

Furthermore, it is possible to can be selectively connected using local trench isolations (PTI) 1430,1434 with forming trap interconnecting piece Region.PTI1430,1434 depth be set such that PTI will be partially into shallow p-well.As shown in fig. 14e, it such as aoxidizes The insulator of object area 1438,1422, which is subsequently deposited upon, to be formed in the region of channel.Herein, silica may be used as insulating Body, it is also possible to use other kinds of insulator.Gate electrode 1436,1440 is then mounted to each gate insulator, To enable supply grid voltage in operation.

4F referring to Fig.1, spacer 1446 are formed on each side in each of NMOS and PMOS grid and insulating regions.Source Polar region domain and drain region 1448,1450 are then injected on each area of grid in lower section on the surface of chip, wherein source area Domain and drain region are adulterated by N-type and p-type respectively.Optionally, NMOS and PMOS ring-type injection processing can be described below Old-fashioned mode device on execute.In addition, body contacts portion region 1444 and 1464 is respectively by the doping of p+ type and the doping of n+ type With the contact of the ontology of shape pair transistor.Thus, as shown in figure 14g, NMOS and PMOS transistor are then formed, and can mention For contact portion necessary voltage is supplied to source region and drain region with operated device.Also second is shown in Figure 14 G Spacer 1452 is connected with using photoresist to 1448,1450 NMOS with pmos source/drain electrode.Then source electrode and leakage are formed Polar region domain 1454,1456,1458,1460.Then contact portion and metal are formed using photoresist, so that being in electrical contact with device.It takes Wherein by source electrode and drain electrode positioning certainly in processing, electric field can greatly be influenced.

It may include other optional steps, with further although above description manufactures certain steps of DDC device The performance of device is improved, or meets different application specification.For example, as shown in figure 14g, it can be using in the prior art as source Pole/drain electrode extends well known technology to reduce leakage current.It will be appreciated by persons skilled in the art that many differences can be carried out Region combination, and region combination can rearrange, and be replaced with the consistent different zones of introduction herein.

Threshold voltage adjustments region and shielding area doped level are limited to the area below channel between spacer edges Domain.In a method, using hard on mask and grid as defined by the spacer around each grid 1436 and 1440 Mask etches silicon to outside spacer 1452.The silicon depth being etched is greater than the depth of shielding area.In this example, identical Or silicon is etched to both NMOS and PMOS in different steps.After silicon etching, as shown in fig. 14h, 1466 extension of silicon is raw Grow to the level of slightly above gate dielectric.As shown in Figure 14 I, the doping of epitaxially grown silicon can in situ or use source/drain Pole injecting mask is completed with forming regions and source/drain 1468,1470,1472 and 1474.Firstly, gate dielectric 1438 and The stacking of two gate dielectrics 1437.Layer 1435 and 1436 is the metal gate electrode with suitable N+ P+ work function design.Scheming In 14I, the polysilicon metal gate electrode displacement for being combined with gate dielectric.In order to use metal gates displacement polysilicon, it is desirable that tool There are two different metals of suitable work function.Need about 4.2 and the workfunction metal of about 5.2eV mixed with adjusting with N+/P+ The V of miscellaneous polysilicon (it is conventionally used in CMOS processing) NMOS being mutually compatible with and PMOS device_T.Spacer around grid 1452 and grid on hard mask formed self-aligned source/drain region.This causes lower source/drain to the electricity of ontology Hold.In another method, compensating source electrode/drain electrode injection can be executed.In this method, on the spacer and grid around grid Hard mask allow grid autoregistration.

It arrives as will be appreciated, it is expected that with multiple power modes effectively operation circuit.In addition, can different power modes it Between quickly and to effectively switching can significantly improve transistor and the chip manufactured using this transistor, also implement it is this The power-saving capability and overall performance of the system of chip.Using effective ability for changing operation mode, when needed, device can be exported High-performance, and electric power is being saved by entering sleep pattern to the used time.According to one embodiment, each sub-circuit and each The mode of device can be controlled dynamically.Utilize the ability for the threshold voltage for dynamically changing device, moreover it is possible to dynamically change device The mode of part.

Deepdepletion channel device can have a nominal threshold voltage of wide scope, and can use wide scope operation voltage and Operation.Some embodiments can be implemented in the Current standards block CMOS operation voltage from 1.0 volts to 1.1 volt, and also It (can be operated under such as 0.3 to 0.7V) in much lower operation voltage.These provide circuit structure for low-power operation.This Outside, DDC device can due to they strong body effect and more have responsiveness than traditional device.In this regard, strong ontology effect Device should be able to be allowed substantially to be directly connected to other devices and via shared trap and influence the variation of circuit.Show at one In example, shared trap may include the common p-well or N trap below device group.In operation, these devices pass through modification device Respective body bias voltage and/or operate voltage setting and can change pattern.This makes it possible to quickly switch single device Part or one or more device group, and less energy is used than traditional devices.It thus, can rapidly emergence pattern Dynamic change, and system energy management perfection electric power is saved and overall system performance.

In addition, in some applications, the back compatible to existing environment can be required, enable DDC base device and tradition Device more seamless operation.For example, the new DDC base device and traditional devices run under 1.1 volts of voltage of operation can be mixed. Level conversion can be needed to be implemented, in order to DDC base device to be connect with traditional devices.It is highly desirable to DDC base device and old-fashioned device Part more seamless operation.

Shielding area provides high body effect, this has lever for responsiveness multi-mode switching in transistor (leverage) it acts on.The response of transistor with shielding area can change to the change of body bias in wider range Change.More specifically, high doped shielding area can allow device current conducting and switch off current under various body bias more Broadly change, and thus dynamic mode can be promoted to switch.This is because DDC device can be configured with σ V more lower than traditional devices_T、 The lower variance of set threshold voltage.Thus, threshold voltage can be set as different value V_T.In addition, device or device group energy Body bias, in order to change threshold voltage, thus V_TItself can in response to variation body bias voltage and change.Thus, Lower σ V_TLower minimum operation voltage V is provided_DDAnd the available nominal characteristic value V of wider range_T.The body effect of increase Permission dynamically controls V in that wider range_T。

In addition, if needing, moreover it is possible to which device is configured to maximum performance by expectation, even if this performance can cause power to disappear The increase of consumption.In an alternative embodiment, when device is not under the operating condition of high-performance activation, it may be desirable that device arrangements exist In the mode (sleep pattern) of significant low power.When circuit utilizes DDC transistor, mould is arranged with sufficiently fast switching time Formula switching, not influence the total system response time.

It is expected that in transistor or transistor group according to different DDC embodiments and example arrangement illustrated and described here In can have several different types of modes.One mode is low-power mode, wherein the bias between ontology and source voltage V_BSIt is zero.In this mode, device is with low operating voltage V_DDWith active/passive power more lower than non-DDC device but with Any comparable capability operation of traditional devices.Another mode is to reinforce (turbo) mode, wherein the bias voltage V of device_BSIt is Forward bias.In this mode, device is with low Vcc and substantially low Passive Power operation.In old-fashioned mode, process flow quilt Modification is to allow non-DDC MOSFET element substantially to operate identically as old-fashioned device.

Although the device of DDC construction provides very big performance advantage relative to traditional devices, due to shielding area There is provided strong body effect and can also enhance dynamic mode switching.Ontology interconnecting piece allows using the expectation ontology for being applied to device It is biased to realize desired mode.This can be with as described above with the DDC or optional of low dosed channel and shielding area It is realized with the DDC with concentration of dopant different multiple regions or layer on ground.When multi-mode switching is used for such as memory , can be unrealistic using each transistor controls of traditional block CMOS technology when the transistor group of module or logic module, And substantive make somebody a mere figurehead can be caused to control circuit.Need to implement additional control circuit, for controlling different components or difference The extensive Special wiring of device group and one highly necessary significant is added in the entire cost of integrated circuit.

Accordingly, it is desirable to research and develop can be used to formed for dynamic mode switching one group or multiple groups transistor sub-circuit or Person's unit.Furthermore, also it is desirable to a kind of scheme be provided, body bias control technology can be provided to old-fashioned device, so that only Individually (standing) or in mixed environment, old-fashioned device may also benefit from dynamic control.

Additionally, with shielding area transistor relatively high body effect make its in certain embodiments regardless of It is still dynamically adapted to use body bias as controlling for being operated in each mode in Static Design Device, meanwhile, traditional block cmos device can require physical Design to replace.

It is shown in FIG. 15 with high doped shielding area and body bias is applied to the substantially more of the mechanism of ontology Mode device is reproduced from Fig. 2A together with the corresponding table of diagram different mode.Such as Fig. 2A is combined to discuss, bias voltage V_BSIt can be with It is applied between trap interconnecting piece and source electrode, with the electric field of control device, including the field between source electrode and device body.Figure 15 diagram The composition of sample of 4 terminal MOSFET of n-channel.Terminal 106 is appointed as draining, and terminal 104 is appointed as source electrode.In operating process In, electric current flows between the two terminals.Terminal 102 is known as gate electrode, and voltage is often applied to this terminal to control Electric current flowing between the drain and source.Terminal 126 provides the company to the ontology (being p-well 114 in this example) of transistor It connects.The voltage for being applied to drain electrode is positive supply voltage (referred to as V_DD), and the voltage for being applied to source terminal is low supply voltage. The characteristic of electric field influence device.According to various embodiments described herein, device can be by being appropriately selected bias voltage V_BSWith Supply voltage V_DDAnd it is configured to multiple and different modes.

In conventional block cmos device, substrate is usually connected to source electrode to maintain identical source-body voltage.Thus, this Body-bias is usually identical for all devices on substrate.Be similarly to DDC device used in above-described normal low-power/ The situation of low-leakage mode wherein applying normal operation voltage, and applies zero-bias voltage, so that V_BS=0.However, according to The multi-mode device of various embodiment constructions described herein can provide effective scheme control means instead of ontology interconnecting piece. This includes the case where heavily doped shielding area especially in this way in device as described above at a certain distance from away from grid.Unlike exhausted Silicon biased device (it is with low body effect) on edge body, DDC biased device, which can be constructed, has height originally to generate on block silicon The device of bulk effect.Thus, the device of DDC construction can be using the body bias of variation as the means for carrying out multi-mode operation. The multi-mode transistor as shown in the example of fig. 15 has n-channel above p-well.P+ type region is formed in p-well.Ontology Interconnecting piece (still following discussion is not shown) is coupled to the region P+ so that with p-well (it is the ontology of n-channel device) conductive contact. Since ontology interconnecting piece is p+ doping, the connection with ontology interconnecting piece will be connect with the p-well (that is, ontology of device) of device. Then body bias voltage can be applied between source electrode and ontology interconnecting piece, body bias voltage can efficiently control n-channel The operation mode of device.As in n-channel device, dynamic mode handoff technique can be applied to the p-channel device above N trap Part, wherein form the region n+ to accommodate ontology interconnecting piece.In addition, the novel structure energy with strong body bias described herein Being applied to wherein n-channel and p-channel device, there are the cmos devices in same substrate or trap.The example of this embodiment with Lower diagram and description.

The behavior of cmos device can effectively be changed by being applied to the device bias voltage between source electrode and ontology.For aforementioned Device with ontology interconnecting piece can apply source-body voltage independently of gate-source and drain source voltage.Use this Body-bias is that device can connect as it is traditional devices as an advantage of the control means controlled for multi-mode It connects, for example, grid-source voltage and dram-source voltage are constructed in the same manner in traditional devices.In the case, Model selection can be carried out in response to body bias.Thus, device can normally operate under zero-bias, this and traditional devices phase Together.When it is expected higher performance mode (enhancement mode), forward bias voltage can be applied between trap interconnecting piece and source electrode, That is, V_BS>0.Operation voltage for enhancement mode can be identical as the operation voltage of normal mode or be slightly above the operation voltage. On the other hand, when desired sleep pattern, reverse bias voltage can be applied between trap interconnecting piece and source electrode, that is, V_BS<0.With In sleep pattern operation voltage can it is identical as the operation of normal mode or slightly below the operation voltage.

When applying zero body bias, multi-mode device operates under normal low-power mode.Body bias can add forward direction Bias, positive voltage are applied to the performance for increasing device between ontology and source electrode as shown in the example of Figure 15.This forward bias pressing mold Formula be known as being used to increase high driving current in terms of performance " reinforcement " mode.However, the enhancing of performance is the leakage with increase Electric current is cost.In deep sleep mode, ontology is added reverse biased, and negative voltage is applied to ontology as shown in the example of Figure 15 To reduce leakage current between source electrode.When device is in idle condition or when dormant state it is expected this mode.

Figure 16 is shown in threshold voltage V between the example and traditional n-channel device of n-channel DDC device_TWith bias voltage V_BSComparison.Curve 1610 indicates DDC device, and curve 1612 indicates traditional devices.Figure 16 shows the threshold voltage of DDC device In some implementations than traditional devices more in response to bias voltage.DDC device can also be provided to be prolonged in response to the wide of body bias Slow range.For traditional devices, threshold voltage causes the extensive expansion of delay time from the variation of device-to-device as shown in Figure 17 A It dissipates.The bias voltage V for respectively indicating -0.5V, 0.0V and+0.5V with 1702,1704 and 1706_BSDelay variation, wherein delay Time with in V_DD=1.1V, V_BS=0.0V, σ V_TTraditional devices in the case where=0.0V and temperature=85 ° are normalized to 1 Delay time relative scale show.Trunnion axis corresponds to 3 σ V_TValue.The σ V of traditional devices_TTypically about 15mV, this causes 3 σ V_T =45mV.As shown in Figure 17 A, three bands 1702,1704 and 1706 are substantially overlapped, and make it difficult to distinguish mould according to delay time Formula.Figure 17 B shows the exemplary improvement delay time of DDC device.In Figure 17 B, three bands are not overlapped not only, but also are had Much smaller diffusion.In three different bias voltage -0.5V, 0.0V and+0.5V (reverse biased, zero-bias and forward bias) Under, DDC device illustrates the band 1708,1710 and 1712 of three a great differences.Three visibly different bands are shown in some implementations DDC device in example very effectively uses under multiple operating mode.

Reduced σ V can be provided_TAnd thus provide the V that can be more accurately controlled_TOne of transistor other benefits It is dynamically to control V_TAbility.In traditional devices, σ V_TIt is so greatly, so that needing to consider V_TAcross wide range.According to Embodiment described herein can dynamically change V by adjusting body bias voltage_T.It is mentioned by the body effect of increase For V_TDynamic regulation, and dynamic control range by reduced σ V_TIt provides.Referring to Fig.1 8, an illustrated example is illustrated, Static V for device setting is shown_T, V_T0, the multiple V for being adjustable device are further illustrated_T.Each there is corresponding △ V_T, Or it is used for each corresponding V_TThe independent △ V of value_T.According to embodiment described herein, device, which can be configured with, is requiring voltage Body bias voltage is adjusted in range and there is the adjustable V of dynamic of suitable voltage adjustment speed_T.In some embodiments In, voltage adjusting or voltage adjusting can be carried out with predetermined step continuously to be changed.

According to another embodiment, although Figure 15 diagram can in the sample multi-mode device that various modes are operated, For transistor group, device includes that the structure of isolation ontology is also useful.It is effective in each mode that this can provide device The ability of ground independent operation.If the ontology of multi-mode transistor group is connected, entire group will switch simultaneously, limit promotion mould The ability of formula switching.On the other hand, if the ontology of two groups of multi-mode transistors is not connected, two groups can be controlled individually. Thus, basic multi-mode transistor shown in Figure 15 can further provide for capable of being divided into every group it is multiple with independent body bias The transistor group of module.These will be described below.

Thus, DDC structure (such as Figure 14 A to Figure 14 I is illustrated and in transistor arrangement discussed above) construction can be utilized Improved system.The integrated circuit and system for having obvious advantage in aspect of performance can be implemented in the variation of these structures.? It is shown how the structure is configured to reduce transistor, and will show how these structures are used as module to reduce now Wider integrated circuit and system.Utilize DDC structure, STI, PTI, the shallow well being incorporated in such as integrated circuit and system And/or shared trap, integrated circuit and system can be constructed for new and improved system performance.In addition, being connected using ontology The new innovation of portion and/or ontology access transistor can be evenly spaced apart use with DDC structure, to mention for integrated circuit and system For new feature and benefit.Thus, these blocks CMOS can be used to the innovation of other novel structures and processing to greatly improve Operation construct the integrated circuit of new diminution.

Although transistor embodiment described so far can provide the continuous power of block CMOS transistor and other devices etc. It reduces, but the place and route by compatibly modifying circuit module according to the transistor embodiment discussed herein, sufficiently It can also be done so using the expectation of some benefits and feature of the DDC structure in chip level.For example, as previously discussed, Know and adjust the body bias voltage of transistor dynamically to adjust the principle of their threshold voltage, but the principle is in nanometer Not yet it is proved implementable in grade device.The reason is that in some implementations, (1) conventional block CMOS nanoscale devices it is big σV_TEnough differences between transistor about existing nanoscale devices will not be provided；(2) conventional block CMOS nanoscale devices Relatively low ontology coefficient will not provide switch fast enough between operation mode to avoid influence chip operation ability； And body bias line is routed to each transistor or circuit module by (3) to reduce the crystalline substance that can be integrated on chip significantly The quantity of body pipe, thus forbid being reduced with chip level.Some DDC transistor embodiments can solve first liang by following A problem (1) is by providing significantly reduced σ V_T, so that the identical transistor for allowing to be designed is not only with different threshold voltages work Make and with different operation voltage power supplies；And/or the ontology coefficient that (2) are significantly increased by offer, to allow transistor And circuit module quickly and to effectively switches between operation mode.DDC transistor can be used as chameleon in some embodiments Shape (chameleon-like) field programmable transistor (FPT) processing, some of or whole nominal configurations having the same And characteristic, but can independently be configured as must in conventional block CMOS the transistors of different manufactures and operate.This The improved wiring of body-bias line is another element of following discussion, provides and how to be shown using other of multi-mode transistor Example.

Figure 19 is the simplification figure for illustrating the principle of multi-mode operation of transistor group, wherein each module or circuit can be with It is operated in different modes based on the body bias voltage and operation voltage supplied.In some implementations, to modules Applying individual body bias can allow by dynamically adjusting its threshold voltage, and the component for allowing to connect jointly is in common mode The lower component or system for operating and allowing individually to connect operates under the mode individually controlled carrys out control system.It is described in Figure 19 Sample situation in, device 1900 be divided into five group transistors with independent body bias contact portion or circuit module 1910, 1920,1930,1940 and 1950.According to embodiment described herein, the ontology of five circuit modules is isolated from each other, so that different Body bias can be applied independently to each module.In this example, each circuit module, which has, organizes the sheet being isolated with other Body, and ontology is connected by each ontology interconnecting piece (1915,1925,1935,1945 and 1955).Five modules are intended to figure Show the needs for promoting the isolation between transistor group to form isolation module.Figure 19 also illustrate each module be connected respectively to it is each Body bias V_B1、V_B2、V_B3、V_B4And V_B5.Such as those skilled in the art, it is to be understood that, each module will also require other supplies Voltage, the V such as to drain_DD, source electrode V_SS, grid V_GWith other models.Additionally, different operation voltage V_DDIt can be single Solely it is applied to each circuit module.The mode of each circuit module can be by design (for example, by by different circuit modules Different body bias voltage and operation voltage are connected to establish their operation mode independently of one another) and static settings, And/or it can adjust the body bias and/or operation electricity of each circuit module by control circuit and in operation Pressure is dynamically set with setting the operation of its operation mode.Utilize low σ V_TWith adjusting threshold voltage V_TAbility, in value Than in wider range, the operation mode of each transistor and transistor group can be individually controlled.

In the following example, various transistors will be described.These transistors are intended to serve as module to form transistor group Into the module with isolation ontology.Such as referring again to Figure 14 G, it is brilliant that a pair of CMOS for being configured with novel DDC structure is shown One embodiment of body pipe, the transistor have ontology interconnecting piece, and wherein n-channel device and p-channel device be on the same substrate. These structures can be used to research and develop the circuit and system that performance is greatly improved, including embodiment described below.Other are brilliant The transistor combination that body pipe can be constructed with novel DDC utilizes, and some embodiments herein can be in no DDC construction It is constructed in the case where transistor.

The example that there is Figure 20 diagram 4 terminal resistor of n-channel of well structure to be laid out, wherein single p-well 2060 is served as a contrast in P On bottom 2080.The layout 2000 of 4 terminal resistors shows source/drain to 2020 and 2030, grid 2040 and ontology interconnecting piece 2050.The cross section at position 2010 is also shown, wherein 2070 depth of shallow trench isolation (STI) is less than p-well depth.P-well 2060 It is public for all n-channel transistors in substrate P 2080.Thus, 4 terminal resistors will not provide n-channel transistor Between isolation.As shown in this example, ontology interconnecting piece is P+ doping simultaneously close to transistor lateral arrangement (referring to shown by Gate orientation).In addition, ontology interconnecting piece is by STI2070 from transistor isolation.

Figure 21 diagram has the example of 4 terminal resistor of n-channel of novel shallow trench p-well (SPW), wherein SPW depth is small In STI depth.The layout 2100 of this 4 terminal n-channel transistor show source electrode and drain electrode to 2020 and 2030, grid 2040 and this Body interconnecting piece 2050.2180 shown position 2110 of section view, and 2190 shown position 2112 of section view.Shallow well can be carried out Ontology isolation, and as a result, can allow to be directed to device group (such as memory cell or other digital circuits) in certain implementations Dynamic mode switching is carried out, thus, reduce the number for the body bias pressure-wire that must be routed on integrated circuit.Such as Shown in viewgraph of cross-section 2180 and 2190, transistor has shallow p-well 2160 on complementary N trap 2164.Due to p-n junction, N trap 2164 It is not conductively connected to shallow p-well 2160, and N trap is not conductively connected to substrate P 2080.Thus, transistor can be in phase It is isolated on substrate with other n-channel transistors on N trap 2164 with shallow p-well 2160.Active region Fang Yan under the gate It stretches.Minimum active region critical dimension (CD) is used for the active part just extended under the gate.Extending active area edges can be with It is arranged between spacer edges to avoid short-circuit due to silication.It can be carried out ontology above extension active region outside grid to connect Touching.N+ injection edge can extend the lower section in (end cap) region in grid.Although the example illustrates to form 4 terminal crystal of n-channel One method of pipe, layout can also be applied to form 4 terminal resistor of p-channel.As shown in figure 21, in some implementations, STI energy It is deeper than SPW.In some implementations, if two adjacent transistors do not have public SPW, they can independently of one another partially Pressure.Optionally, adjacent transistor group can be with the SPW of share common, and can be by applying identical body bias with identical Mode operation.

In the another embodiment of dynamic multi-mode transistor, as shown in figure 22, ontology access transistor can be formed in reality Between border transistor and ontology interconnecting piece.Figure 22 illustrates 4 terminal resistor of n-channel layout 2200 and relevant viewgraph of cross-section 2280, wherein shallow p-well (SPW) 2160 is isolated by STI2070.Ontology access transistor can by ontology interconnecting piece from transistor every From.Ontology access transistor can be formed as seeming to be used as the grid for ontology access transistor in the presence of a kind of wherein grid 2041 And ontology interconnecting piece is as the processed transistor of source/drain.This can simplify processing, and reduce and carry out ontology interconnecting piece company Connect required region.The module for becoming useful is applied in combination in ontology access transistor and shallow well, with can with subtle granularity into Mobile state pattern switching.For the transistor group or circuit group to switch together, they can be arranged to share identical shallow well. In addition, forming one or more by using ontology access transistor to provide the connection with ontology and supply body bias Grid interconnecting piece.

As described above, local trench isolations (PTI) are another preferred embodiments by ontology interconnecting piece from transistor isolation.Root According to another embodiment that Figure 23 is illustrated, example layout 2300 and viewgraph of cross-section 2380 for 4 terminal resistor of n-channel include Shallow p-well (SPW) and local trench isolations (PTI).Viewgraph of cross-section 2380 corresponds to the cross section at position 2310.SPW depth STI depth can be less than.PTI oxide can prevent suicide shorts between n-type source/drain electrode and p-type block interconnecting piece.PTI depth Shallow well depth can be less than, so that maintaining continuity of the shallow well in transistor.PTI mode can provide prevent in some implementations Due to the excellent protection of the possible short circuit of silicide between ontology interconnecting piece and source/drain.However, PTI is also in device One or more additional treatment step is required in manufacturing process.PTI depth is preferably more than source/drain in some embodiments Pole is tied to separate P+ block interconnecting piece and N+ source/drain, thus makes N+/P+ junction leakage minimum.

It the opposite plan-position of active region for the active region of source/drain and for trap interconnecting piece can be different Ground arrangement, to form the deformation of 4 terminal resistors 2400 as shown in the example in Figure 24 with PTI.Viewgraph of cross-section 2480 Position 2410 and 2412 is corresponded respectively to 2490.As indicated, shallow p-well is isolated by STI.

Although above example diagram setting ontology interconnecting piece is used to apply 4 terminal resistors of body bias voltage, The case where in the presence of the forth terminal for body bias can not needed.For example, when CMOS transistor has on public N trap Shallow p-well and N trap, the p-channel transistor with shallow N trap on N trap will always have public N trap.It, can be in this implementation It does not need to provide the individual forth terminal for being connected to ontology.As a result, illustrating several examples of 3 terminal resistors herein, and will These examples are used as module to form the transistor group with ontology isolation module.In another case, transistor can be at it Described in transistor be intended to on the floating complimentary wells operated of ontology have shallow well.In this implementation, do not need using Four terminals.

For an example of 3 terminal structures 2500, local interlinkage portion is connected grid with ontology with by the number of terminal Three are reduced to from four, as shown in figure 25, viewgraph of cross-section 2580 and 2590 corresponds respectively to position 2510 and 2512.? 2580, local interlinkage portion (LI) contact portion 2551 is used to for being connected in body contacts portion the grid of extension.In this example, it uses Metal contacts carry out the contact of grid to ontology in the top of the active region of extension.The rectangle used in sram cell connects Contact portion can also be used to grid being connected to ontology.

In another embodiment, 3 terminal dynamic multi-mode transistors are by using body contacts portion in the lower section of polysilicon And it is formed.The oxide below grid is removed using GA (grid to active layer) contact mask.Region is removed in gate dielectric Top can form polysilicon gate contact (PGC) injection, have polarity identical with SPW.Such as 2600 institute of structure of Figure 26 Show, ontology is connected to grid using PGC2650.Viewgraph of cross-section 2680 and 2690 corresponds to position 2612 and 2614.This office Portion's scheme can have the advantages that several are potential, the ability, and/or progress autoregistration contacted including the self-aligning grid with ontology The ability of GC (gate contact) injection.Due to GC injection can have with SPW (P+ doping) identical polarity, in some embodiments In, it is not bent in the active areas, this is the design (DFM) of friendly manufacture.Being attached using PGC can cause to ontology Higher contact resistance.However, controlling for the static schema in some embodiments, contact resistance is not crucial.Thus, when When needing static cost control, PGC can be used.

Optionally, as shown in figure 27,3 terminal single gate transistors 2700 are similar to, body contacts can extend in grid Lower section extend active region in carry out.Viewgraph of cross-section 2780 and 2790 corresponds to position 2712 and 2714.Minimum active Region critical dimension (CD) can be used for the active part extended.The lower section that the active area edges of extension can be located at grid is active Between the spacer edges in region.Oxide below grid can be used GA contact mask and remove.It is removed in grid Region top, can be formed with being injected with the GC of SPW identical polar, and be used to ontology being connected to grid by rear ontology Pole.In some implementations, this mode can provide similar advantage, contact with the self-aligning grid of ontology or including using from right The ability of quasi- GC injection, this is because GC injection has polarity identical with SPW (P+ doping).

Although as shown in the example in Figure 27 difference can be located at along polysilicon for the contact portion of grid and trap interconnecting piece At position, they can be as shown in the structure 2800 in Figure 28 with identical position orientation.Viewgraph of cross-section 2880 and 2890 is distinguished Corresponding to position 2812 and 2814.

In another embodiment, layout will allow programmable 4 terminal/3 terminal resistors.Such as 2900 institute of structure of Figure 29 Show, grid and ontology, which can be used metallic region 2950 and disconnect perhaps connection, respectively obtains 4 terminals or 3 terminals.Cross section view Figure 29 80 and 2990 corresponds respectively to position 2912 and 2914.As a result, metallic region connection facilitates programmable 4 terminal/3 ends Sub- transistor layout.

Various transistors are described here, and the different structure energy described in various embodiments and example To form useful system in different combination and minor structure, has relative to traditional system change in many cases Into performance.These transistor arrangements are also used as being used to form the transistor group for being divided into multiple modules and have for dynamic The module of each body bias connection of pattern switching.Some examples are described below.

A preferred advantages according to the transistor of some embodiment constructions described herein are the energy of dynamic mode switching Power.This can be carried out by applying controlled body bias voltage with setting or adjusting variable operation voltage.Figure 30 diagram Can use 4 terminal resistors carry out dynamic mode switching circuit 3000 an example, wherein show each bias voltage and Operate voltage.Circuit module a1-a4 corresponds respectively to the low leakage of standard and two enhancement modes.Each circuit module uses A pair of 4 terminal resistors, 4 terminal resistor 3020 of 4 terminal resistor 3010 of p-channel and n-channel, wherein 4 terminals are appointed as S (source electrode), D (drain electrode), G (grid) and B (ontology).In module a1,4 terminal resistors with ontology interconnecting piece, which are used as, to be passed System transistor.Ontology for n-channel device (shown in lower transistor) is connected to source voltage V_SS.For p-channel device (institute The upper transistor shown) ontology be connected to operation voltage V_DD.In module a2, when device is not activated in use, device is added instead To being biased to realize low leakage.Reverse biased can be used for the reversed inclined of n-channel by the way that the ontology for being used for n-channel device to be connected to Piezoelectricity presses V_BBNIt realizes, the V_BBNLower than V_SS, and the ontology for p-channel device is connected to the reverse biased for p-channel Voltage V_BBP, the V_BBPHigher than V_DD.If it is desire to higher performance, then the device as shown in module a3 and a4 can be placed in forward bias press strip In part.In a3 (i), p-channel ontology and n-channel are connected respectively to dedicated forward bias voltage V_FBPAnd V_FBN, wherein V_FBPIt is small In V_DD, and V_FBNHigher than V_SS.Optionally, by eliminating as the required accessory supplied of positive bias voltage, source electrode and leakage Pole can be used for forward bias to save system cost.As shown in a3 (ii), the ontology of p-channel is connected to V_SS, and it is used for n-channel The ontology of device is connected to V_DD.A4 (i) and circuit in a4 (ii) are in addition to high operation voltage V_DDHA3 (i) is similar to except being connected With the circuit in a3 (ii).

As shown in figure 31, there are also other several variations in switching at runtime environment using 4 terminal devices.In Figure 31, The ontology that circuit module a1 illustrates 4 terminal devices is not connected to form the floating situation of ontology.There are Figure 31 of two forms The floating body 3100 of diagram, Neutron module a1 (i) use V_DDAs operation voltage, and submodule a1 (ii) uses V_DDHMake To operate voltage.This will convey medium performance.In circuit module a2, the ontology and drain electrode of p-channel and n-channel device all connect It is connected together to realize enhancement mode.Identical dynamic mode handoff features can extend to tool according to one embodiment described herein There is the large-scale circuit of more multiple transistor.

The implementation that Figure 32 A diagram is switched using the dynamic mode for simplifying shell.Figure 32 A shows circuit 3200, wherein two A circuit module 3220 and 3230 has the ontology of isolation, makes it possible to apply independent body bias.It can be via body contacts portion 3225 apply the body bias for being used for circuit module 3220, and can apply via ontology interconnecting piece 3235 and be used for circuit module 3230 Body bias.The power bay for being similar to and being used for other voltages shown in Figure 30 is not shown.However, those skilled in the art It is readily appreciated that the implementation of the power bay for system in Figure 32.Example cross-section 3250 for this circuit module exists It is shown in Figure 32 B, the n on N trap 3264 with shallow p-well 3260 and 3261 is correspondingly described with circuit module 3220 and 3230 Channel device.Shallow p-well 3260 and 3261 is isolated to be formed and be used for two circuit moulds between two circuit modules by STI3263 The individual shallow well of block.Two shallow p-wells 3260 and 3261 are not located at the lower section N of 3266 top of substrate P due to p-n junction effect Trap 3264 connects.Ontology access transistor is used to form interconnecting piece, and also by interconnecting piece from the active transistor of shared SPW trap every From.P-type contact region 3210 is for body contacts portion to provide the connection with shallow p-well.Example in Figure 32 B illustrates shallow channel STI3262 is used together to be formed and multimode modules are isolated for dynamic mode switching with ontology interconnecting piece.Although the example It is illustrated for n-channel device, but it can be easily applicable to p-channel device.

Moreover, the example that it can also be extended in Figure 33 A with p-channel and n-channel device in structure 3310 is schemed The device 3300 shown.Figure 33 B indicates that cmos device tool has there are two shallow p-well 3260,3261 and also with each body contacts The case where shallow N trap 3360 in portion 3325,3335 and 3345.It is all on N trap 3264.Three circuit modules: circuit mould are shown Block 3320 and circuit module 3330 are n-channel devices, and circuit module 3340 is p-channel device.Each circuit module can be total to With identical N trap 3264.Due to p-n junction effect, the shallow p-well for circuit module 3320 and 3330 is total in some embodiments It is from p-channel device isolation.There can be more than one p-channel circuit module.However, since shallow N trap is permanently attached to lower section N trap, each p-channel device can body bias having the same.Thus, in some applications, such as p-channel device 3360 shallow N trap cannot share public N trap with other shallow N trap devices.In this application, when using public trap, N trap device The shallow well of isolation cannot be divided into.Thus, from the point of view of dynamic power mode switches viewpoint, do not need to be formed for p-channel device Each circuit module.In some embodiments, in the case where single N trap, only n-channel device can via body bias and It is individually controllable.When following transistor configurations have high body effect transistor described herein, the use of ontology can become At the effective means for promoting dynamic mode switching.For p-channel device, the shallow N trap in N trap is optional.

The following drawings illustrates a certain number of examples of circuits that multiple method and structures can be used and formed, and can use Make the module for integrated circuit according to embodiments discussed herein.The discussion will start to have used currently to be made in the industry The example of some resume modules and structure.Diagram is used the module being substantially improved than traditional mode by aftermentioned attached drawing The example of structure and processing.

Figure 34 A shows the example for being configured with the circuit of different common circuit components, which will be used in aftermentioned Attached drawing in illustrate dynamic mode switching implementation.In figure 34 a, combinational circuit 3410 is shown with NAND gate NAND2 3402, inverter INV 3403 (inverter) and ontology interconnecting piece TAP 3406.These useful structures can be according to retouching herein The various embodiments stated are come using to provide more preferable construction and the useful circuit with new and enhanced feature.

In Figure 34 B, layout 3420 is shown using virtual polysilicon 3428 implementation transistor group with by 3427 He of interconnecting piece 3429 form to the traditional approach in each trap.Ontology interconnecting piece provides and is public trap or substrate for all devices Connection.Figure 34 B shows the ontology interconnecting piece extended in trap.The lower part of layout shows the n ditch on N trap with shallow p-well This part for the device implemented in road.Shallow p-well by STI from adjacent device isolation because the depth of shallow p-well is less than STI depth. The top of layout shows this part for the device implemented in the p-channel in p-well with shallow N trap.Again, shallow p-well is by STI from phase Adjacent device isolation.Due to using two individual traps (p-well and N trap) and each shallow well, full complementary device to allow to n-channel device And individual each dynamic control of p-channel device.It is including NAND gate NAND2 3433, inverter INV 3434 and TAP In 3426 Figure 34 B, the upper and lower part of device has each ontology interconnecting piece 3427 and 3429.The lower part of layout is shown in P This part for the device implemented in n-channel on trap with shallow p-well.The top of layout shows the p ditch on N trap with shallow N trap This part for the device implemented in road.Including NAND gate NAND2 3433, inverter INV 3434 and ontology access transistor TAP Other than 3426 Figure 34 C is implemented in addition to single ontology interconnecting piece 3437 and 3439 is based on novel ontology access transistor 3438 Similar to Figure 34 B.These novel ontology access transistors provide the innovative construction for allowing to access transistor body.Unlike Conventional device designs, these structures provide device and circuit significant operational capacity.

Figure 34 D diagram includes NAND gate NAND2 3433, inverter INV 3424 and ontology access transistor TAP3446 The example of circuit layout 3440, using ontology access transistor 3450 to form two ontology interconnecting pieces being divided to out by STI 3437 or 3439, to provide the connection with each trap.For Figure 34 D, ontology access polysilicon is used to implement the company with ontology It connects.There are two the ontology access transistors of individual ontology interconnecting piece to be isolated by STI for tool；The left and right side of STI has isolation Shallow well to allow each body bias to be connected to left and right side.Figure 34 E respectively illustrates corresponding with position 3482 and 3484 Viewgraph of cross-section 3490 and 3495.In viewgraph of cross-section 3490, n-channel transistor (for example, 3460) is in two sides by STI In the shallow p-well 3462 of 3464 and 3465 isolation.Shallow p-well 3462 is on N trap 3466, and N trap is in substrate P 3468.Ontology connects Socket part 3439 is connected to shallow p-well 3462.The top of device 3440 is on the shallow N trap 3472 being isolated by STI 3474 and STI 3475 Including p-channel transistor (for example, 3470).Shallow N trap 3472 is in p-well 3476, and p-well 3476 is in identical substrate P 3468.This Body interconnecting piece 3437 provides the connection with shallow N trap 3472.The diagram of device 3449 has showing for the embodiment of complete complementary multiple transistor Example, the multiple transistor have the isolation shallow well with the individual ontology interconnecting piece (3439 and 3437) for dynamic mode control (3462 and 3472).

Although Figure 34 D shows the dynamic mode based on the transistor for being configured with DDC, switching is implemented, which cuts Changing can also be applied in the hybird environment with old-fashioned device and new device.Figure 35 illustrates use for by NAND gate NAND2 3502, the same circuits that INV 3504 and TAP 3506 is formed use the example for mixing the implementation of old-fashioned device and new device, It includes STI 3524 and 3534 to separate shallow well.Again, using both N trap and p-well.However, both NAND2 and TAP make Implemented with old-fashioned mode of the wherein shallow well on the trap of identical doping type.NAND2 3502 and TAP 3506 always has Public trap on N trap or in p-well.Thus, it cannot be isolated by STI for the shallow well of NAND2 3503 and TAP 3506.This cloth The shallow well that setting only can be used in INV 3504 can be isolated.Depending on design, 3504 physical efficiencys of INV are floating (that is, not mentioning It is not connected for the ontology interconnecting piece or ontology interconnecting piece for being connected to each shallow well) or it is connected to body bias.However, by In using two individual traps, two individual body bias voltages can be applied to the p ditch on the n-channel device in p-well and N trap Road device.

Figure 35 is also shown in the example of the viewgraph of cross-section 3550 and 3560 at position 3510 and 3512 respectively.Cross section view Figure 35 50 shows both n-channel transistor and interconnecting piece 3516 in shallow p-well 3522 and 3521.Shallow p-well 3522 and 3521 liang Person is in p-well 3526, and p-well 3526 is in substrate P 3528.Ontology interconnecting piece 3516 provides and the sheet for n-channel transistor The connection of body.Shallow N trap 3532 in lower part for p-channel is isolated floating with a left side.Cross section 3560 shows shallow 3533 He of N trap Both p-channel transistor and interconnecting piece 3514 on 3535.Both shallow N traps 3533 and 3535 are on N trap 3536, and N trap 3536 is in P On substrate 3538.Ontology interconnecting piece 3514 provides the connection with the ontology of p-channel transistor.The shallow p-well of n-channel is used in top 3523 be isolated it is floating with a left side.Ontology interconnecting piece for the n-channel device in the p-channel device and shallow p-well in shallow N trap 3523 It can be added with ontology access transistor as described above.

The example of implementation of Figure 36 diagram based on the old-fashioned mode for wherein using two individual traps.N-channel transistor exists In the shallow p-well 3622 being isolated by STI 3623 and 3624.Since the shallow p-well 3622 for all n-channel transistors is in p-well 3626 On, shallow p-well 3632 is isolated by the adjacent circuit between STI 3624 and STI 3625, because p-well provides n in other shallow p-wells Electric conductivity between channel transistor.Both p-well 3636 and N trap 3636 are in deep N-well 3628, and deep N-well 3628 is in substrate P 3630 On.Ontology access contact portion 3612 and 3614 is also shown.

Aforementioned exemplary diagram is switched using the various dynamic modes of block CMOS and is implemented.In any case, novel ontology interconnecting piece Design can also be applied to the semiconductor devices using non-CMOS block device.For example, ontology interconnecting piece can be formed in as shown in figure 37 Local depletion (PD) SOI technology including NAND2 3722, INV 3724 and TAP 3746 on.Circuit 3700 is similar to wherein Ontology access transistor is used to be formed Figure 34 D of individual ontology interconnecting piece 3712 and 3714.Figure 37 is also shown and along position The corresponding viewgraph of cross-section 3740 and 3760 of 3716 and 3718 layout.The lower part of circuit 3700 with by STI 3743 and 3745 N-channel device in the p-well 3744 of isolation is associated.Thus, it can allow the p-well of multiple isolation to be formed on SOI, so that this Body-bias can be applied independently to each circuit module.The top of circuit 3700 in the N trap being isolated by STI 3747 and 3749 On p-channel device it is associated.Thus, it can allow multiple isolation N traps to be formed on SOI, enable body bias independently It is applied to each circuit module.Both p-well 3744 and N trap 3764 are in buried oxide (BOX) 3748.According to described herein Various embodiments, this construction promote the ability of individually bias transistor group or related switchable device.

Static random access memory be widely used in such as central processing unit (CPU), microprocessor/microcontroller, In the various digital processing units of digital signal processor (DSP), field programmable gate array (FPGA) and other devices or therewith Relatively use.There are several widely used device architectures in the industry.In them, 6T-SRAM (6- transistor SRAM) unit is the most frequently used, thus it can use that universal CMOS is handled to implement.As a result, it can be readily embedded in In any digital processing unit.Using novel structure discussed above, improved SRAM can be configured with better performance and reduction Circuit area.By implementing novel ontology interconnecting piece, ontology access transistor and/or novel DDC structure, can use known Processing equipment and facility generate significantly improved SRAM.In addition, can be used the transistor of novel DDC construction there are also with it is new The other kinds of transistor of the transistor combination of clever DDC construction is some in these SRAM circuit embodiments to be formed.In addition, It is constructed in the case where the transistor that some embodiments herein can be constructed in no DDC, but still benefits from and improve SRAM Energy and feature.

In one embodiment, basic 6T-SRAM unit includes access a data and uses two open gate (PG) crystal Pipe is with two pull-up (PU) transistors and two drop-down (PD) transistors of control bit line and reverse phase bit line.The example is in Figure 38 Structure 3800 in show.Open gate transistors switch can be controlled by wordline, allow to have low operation power consumption and low leakage The SRAM design of electric current.In the example of 6T SRAM in Figure 38, implement PU crystal using 4 terminal resistor 3010 of p-channel Pipe, and other are implemented using 4 terminal resistor 3020 of n-channel.Signal and power supply for 6T SRAM is also shown in Figure 28, packet Include wordline (WL), bit line (BL), bit line negative (BLN), V_SSAnd V_DD.Figure 38, which is also shown, can provide and be used for n-channel transistor The connection of ontology (shallow p-well, SPW) and the ontology (N trap, NW) for p-channel transistor.

Memory access can consume high amount of electric power in electronic system.Have made efforts in technical field research and development for The implementation and system of power consumption are reduced in memory access procedure and during data are kept.SRAM is generally used for for program And in the computer system of data storage.It is executed in program or during data access, a part of memory can be with Initiatively access, and other parts can not work.If the operation mode for SRAM is dynamically switched with subtle granularity, It is then beneficial.In one embodiment, the ontology of each unit can be isolated in structure, enable unit bias individually It is controlled.In practice, by connecting the source voltage for row, row's unit can be controlled together.In addition to above-mentioned base In V_SSThe control of 6T SRAM pattern switching and ontology interconnecting piece and ontology access transistor technology except, there are also another formation is more The mode of mode enabling SRAM.Which for example interrupts the shallow well for being used for unit module by using ontology access transistor technology It spreads and implements in sram.Desired body bias can be applied selectively to the mould of sram cell via ontology interconnecting piece Block, with the desired operation mode of determination.

In order to form dynamic multi-mode SRAM array, the embodiment example using component models is provided.These modules include Various 4 terminals, 3 terminals and programmable 3/4 terminal resistor.These modules can be combined together with various body connection structures To construct the improvement SRAM circuit more effectively operated.For example, ontology access transistor can be by converting the polysilicon on STI Formed at transistor, at the same using ontology interconnecting piece as source/drain to one of handle.Ontology access unit can add The shallow well of SRAM is isolated to peripheral region, body bias is enabled to be applied individually to SRAM array.6T SRAM implements and phase The example of the ontology access transistor of pass is together with connection sram cell and ontology access unit to form SRAM gusts of dynamic multi-mode The processing of column is described as follows.

Layout example of Figure 39 diagram for the 6T SRAM of Figure 38.6T sram cell includes 6 transistors, wherein PG Indicate the position of open gate transistor, PD indicates the position of pull-down transistor, and PU indicates the position to pull up transistor.PD and PG Transistor is n-channel transistor, and is formed in N+ injection zone 3910, and PU transistor is formed in P+ injection zone P-channel transistor in 3920.N-channel transistor is formed in shallow p-well 3940, and p-channel transistor is formed in N trap 3950 On.It the use of shallow N trap is optional in the implementation of this embodiment in N trap 3950.Signal wire and power supply line are in Figure 38 and other It is shown in attached drawing.

The cross section of a preferable layout for SRAM cell structure 3900 is shown in Figure 40 A.Viewgraph of cross-section 4010 Corresponding to the line 4015 where PG transistor and PD transistor.The other end of additional PG and PD transistor towards sram cell is fixed Position, and there is similar viewgraph of cross-section.Transistor is also shown in viewgraph of cross-section 4010 has shallow p-well 3940 on N trap 4040. N trap is in P type substrate 4050.Viewgraph of cross-section 4020 corresponds to the line 4025 where PU transistor.Cross section shows PU crystal Pipe has shallow N trap 3950 on N trap 4040.Shallow N trap 3950 for p-channel transistor is in the dopant with same type On trap (N trap).Thus, shallow N trap and N trap can be conductively connected.Shallow N trap in N trap is optional.However, for n ditch Road device, shallow p-well 3940 can be isolated from N trap 4040 below.The 3D view of 6T sram cell corresponding with Figure 39 is being schemed It is shown in 40B, wherein well structure and transistor types are labeled.

(N trap is not shown the example of the top view of Figure 41 A diagram and a preferred well structure, because it is extended through entirely Unit area).For the 6T SRAM layout of Figure 39, shallow p-well extends to one end from one end in y-direction, wherein x and y is indicated Characterize any direction of the relative bearing of 6T sram cell.Figure 41 B diagram is stacked up mono- to form the 6T SRAM of 2x2 array Member, wherein one of two adjacent cells are formed the mirror image of the unit by upside-down mounting in y-direction on the direction y.Thus, such as Fruit connects a large amount of unit in y-direction, and all units will share identical shallow p-well.It is cut to increase for dynamic mode The granularity changed is needed using the successional structure for interrupting shallow p-well 3940.Interconnecting piece unit, which is used as, is isolated shallow p-well and provides With the continuous purpose of shallow p-well.

The layout example for the interconnecting piece unit that Figure 42 diagram is used in combination with embodiment described herein.Layout designs at It is laid out with sram cell described below.The upper and lower part of interconnecting piece unit has the shallow p-well of isolation, enables them individual Ground is connected to each supply (being shown as VSPW0 and VSPW1) for body bias.Figure 43 is shown in two positions of dotted line expression Set the example of the viewgraph of cross-section at place, wherein attached drawing is rotated.Viewgraph of cross-section 4210 corresponds to the section view at position 4215 Figure.The shallow p-well 3940 in left side can be isolated with 3940 conduction of shallow p-well on the right side of STI.This shallow trench isolation can allow to be applied to this two The different body bias of a shallow well.It is contacted to be formed to shallow p-well, p-type injection is used for ontology access transistor source/drain regions Domain.Due to this p-type source/drain region have doping type identical with shallow p-well, can be formed from p-type source/drain electrode (that is, Ontology interconnecting piece) arrive shallow p-well conduction.Viewgraph of cross-section 4220 corresponds to position 4225.Due to ontology interconnecting piece region doping There is doping type identical with shallow N trap, ontology interconnecting piece forms the connection with shallow N trap.The well structure of cross section 4210 and 4220 It is analogous respectively to the well structure of cross section 4010 and 4020.

The example of the top view of the interconnecting piece unit of Figure 44 pictorial image 42.Unlike wherein shallow p-well 3940 is extended to from one end The sram cell of one end, upside for interconnecting piece unit shallow p-well 3940 can at strapping wires 4480 with those of downside every From.The isolation of shallow N trap 3950 is not a misgivings as before, because shallow N trap is conductively connected to N well region below Domain, and N trap extends through entire unit.Interconnecting piece unit also provides the connection by SPW interconnecting piece 4460 and shallow p-well 3940 With the connection for passing through SNW interconnecting piece 4470 and shallow N trap 3950.Figure 45, which illustrates to be formed, to be embodied according to the dynamic of embodiment described herein The example of the 2x2SRAM array 4500 of morphotype formula controlling feature.SRAM array is by every side on 2x2 sram cell and the boundary y Two interconnecting piece unit compositions are to form SPW interconnecting piece and isolation.Again, the direction x-y is the relative direction for showing array orientation. As shown in figure 45, two neighboring SRAM cells have continuous SPW in y-direction.SPW more than two adjacent lists in y-direction STI in the continuous connection portion unit 4200 of member is terminated.Thus, body bias VSPWn can be applied to 2x2SRAM array, and Body bias VSPW (n-1) can be applied to the adjacent array (not completely shown) on top, and body bias VSP (n+1) energy The adjacent array (not completely shown) being applied on bottom.Figure 46 diagram uses the interconnecting piece unit for SPW isolation The example of 4x4SRAM array 4600.Figure 45 and Figure 46 diagram in y-direction with the internuncial sram cell of SPW use and Terminate the use of the successional ontology access unit (also known as interconnecting piece unit) of SPW.Thus, it can correspondingly form with the phase The dynamic mode of size is hoped to switch SRAM array.

Although Figure 45 and Figure 46 focus on the example of SPW continuity and isolation, many other letters are needed as described above Number and supply voltage to form complete array.Skill of the connection of these signals and supply voltage to SRAM array for this field Art personnel are well known, and its details will be not provided here.In the 4x4 SRAM that is fully connected corresponding with Figure 46, word Line (WL) signal can connect to every row's SRAM array, and bit line (BL) signal can connect to each column SRAM array.

Ontology control signal (VSPWn) can be parallel to wordline and advance.In the operating process of SRAM array, if selection Any word in selected word group, the then body bias of the word group selected can be switched to just.It is read when from specific word group Every other word group when being perhaps written in subarray can have for leakage reduction and the sheet of reverse biased (or zero-bias) Body.

Using ontology interconnecting piece/ontology access unit with promote pattern switching 6T SRAM it is some in use, shallow P This physical efficiency of trap is for dynamically switching, while p-channel ontology (N trap) can be used for static bias voltage.Any word energy selected in the group Switch the shallow p-well ontology of all n-channel transistors in selected word group.It can be set as the bias of p-channel and n-channel Zero, then according to desired mode is positive or oppositely bias.

The above-described dynamic mode switching SRAM array based on ontology access unit is in reducible fine particle size control There is advantage in system.However, this mode will also require ontology access unit other than sram cell.Have do not require it is additional The other methods and system of ontology storage unit.One of these modes use every row V_SS, and in the side based on ontology access unit The public V of all units shareds of SRAM array in formula_SS.If V_SSCan every row individually controlled, unique V_SSCan be applied to Every row thinks that every row forms expectation body bias.In the case, bulk voltage can be uncontrolled.However, V_SSCan individually by Control, to cause different V_SSVoltage (voltage between ontology and source electrode), and realize that dynamic mode switches.

Figure 47 diagram is for being based on every row V_SSMulti-mode switching 6T-SRAM circuit 4700 an example.Again, Sram cell is made of two pull-up (PU) transistors and two drop-down (PD) transistors and two open gate (PG) transistors.Figure 47 A difference between the example of diagram and the 6T SRAM of Figure 38 is that the open gate used in Figure 47 (PG) is that 3 terminal of n-channel is double Gridistor 4710.The layout of 3 terminal double gate transistors and corresponding cross section are shown in Figure 26 and Figure 27.Bigrid Transistor has the grid for being connected to ontology, that is, the grid of PG transistor (that is, WL) is connected to the ontology of unit.PU and PD is brilliant Body pipe is identical type in the example of Figure 38.The example of the layout 4800 of the sram cell of Figure 48 pictorial image 47, wherein show The boundary 4860 of unit out.While p-channel device is used for PU transistor, using for PG the and PD transistor in shallow p-well N-channel device.The well structure of this sram cell is very similar to the structure of Figure 39.It is thus illustrated that viewgraph of cross-section.SPW and Both SNW are on public N trap, and N trap is used throughout unit.

Figure 49 A shows the structure 4900 of the SPW and SNW of the SRAM layout of Figure 48.V_SSContact portion 4910 is directed to this cloth Office is expressly shown.When connecting more sram cells, contact portion is connected commonly using metallic region.Figure 49 B diagram uses Figure 48's The 2x2SRAM array 4920 of sram cell, wherein SPW3940 is discontinuously formed as the SRAM array of Figure 45 or Figure 46.Figure 49B, which is also illustrated, individually connects V for every row_SS(V_SS04921 and V_SS14922).Figure 49 C diagram is based on every row V_SSThe 4x4 of technology SRAM array 4930, wherein use unique V for every row_SS(V_SS04931、V_SS14932、V_SS24933 and V_SS34934)。

In whole layouts of 4x4 SRAM array corresponding with Figure 49 C, similar to based on ontology access unit technology Dynamic mode switches 4x4 SRAM array, can connect wordline (WL) by row, while connecting bit line (BL) column by column.For every The wordline of row may be coupled to SPW (that is, ontology of each device).V can also be connected by row_SS.Thus, it can realize by row Individual body bias.N trap ontology interconnecting piece can occur for every 16 (or 32) wordline.

For 6T SRAM 5000 based on V_SSThe optional implementation of pattern switching be shown in FIG. 50, wherein 3 terminals are double The extension contact portion of gridistor is formed on PG channel, wherein shows elementary boundary 5060.Figure 51 A pictorial image 50 The SPW and SNW of SRAM layout.V is significantly shown for this layout_SSContact portion.Figure 51 B diagram uses the sram cell of Figure 50 2x2SRAM array 5120.Figure 51 B diagram uses the 2x2SRAM array 5120 of the sram cell of Figure 50, wherein SPW3940 does not connect Be formed as the SRAM array of Figure 45 or Figure 46 continuously.Figure 51 B is also illustrated in structure 5100 and is individually connected V for every row_SS (V_SS04921 and V_SS14922).Figure 51 C diagram is based on every row V_SSTechnology 4x4SRAM array 5130, wherein make for every row With unique V_SS0(V_SS04931、V_SS14932、V_SS24933 and V_SS34934).The example of the characteristic and Figure 48 in this element and region It is identical.

According to including V_SS, n-channel bias, wordline (WL) state, bit line (BL) state, V_DDIf with p-channel body bias Dry condition determines the operation mode for being used for unit.V_SS, n-channel bias, wordline (WL) state, bit line (BL) state can be used for dynamic Control, and V_DDStatic schema control can be used for p-channel body bias.For SRAM array, dedicated V is used based on every row_SS (V_SS0、V_SS2、V_SS3).Similarly, shallow p-well is connected to dynamically to control the WL of n-channel body bias also with one WL of every row (WL0-WL3) tissue is carried out.BL and V_DDLine is used to along vertical direction connection unit.As indicated, tissue BL and V_DDThe two with BL and V is provided according to each column_DD.Common SRAM may include read/write, NOP (not operation) and deep sleep mould Formula.The further details of these modes will be described below.

In standby and keeping data mode (corresponding to deep sleep mode), V_SSIt can be by positive bias, with reverse biased n-channel The ontology of device, and reduce effective V_DS.This construction reduces standby leakage.For example, V_SSIt can be set to 0.3V, and V_DDIf It is set to no more than 0.6V, so that V_DS≤0.3V.Reverse biased PG and PD transistor with this condition.P-channel device is by zero-bias Or reverse biased, to keep PU transistor current 1000xPD cut-off current.Under the mode of NOP, PG and PD n-channel device The two there is the bias bulk with reverse biased, and PU p-channel device body is inclined with zero-bias or reverse biased Pressure.As an example, V_DDIt is set as 1.0V, and V_SSIt is set as 0.6V with BL, so that V_DS≤ 0.4V, and realize low standby current.

In read mode, both PG and PD n-channel devices can have forward bias.Dynamic V_DSSwitching can be limited To the word (or row) of selection.For PG device, V_GS=V_BS≤ 0.6V, and V_DS≤0.6V.For PD device, V_GS=1.0V, and And V_BS≤0.6V.Due to bigger PD V_DSIt is able to achieve advantageous PD/PG β ratio.PD device widths can be identical as PD device widths. This is able to achieve advantageous reading quiescent noise surplus and low reading unit electric current.

In write mode, both PG and PD n-channel devices can have forward bias.Dynamic V_SSSwitching can be limited To the word (or row) of selection.For PG device, V_GS=V_BS≤0.6V.Although n-channel PG transistor and PD crystal in shallow p-well Pipe and p-channel PU transistor are used in the above examples, but p-channel PG transistor and PD transistor and n-channel PU in shallow N trap Transistor can also be used to realize identical design object.

Although every row V_SSTechnology does not require the ontology for shallow trench isolation to access, but each sram cell is greater than for base In the SRAM of the technology of ontology access unit.In order to by unit promote from adjacent cell isolation every row based on V_SSOntology is inclined The control of pressure, dead zone domain can be added to around unit.As a result, cell height can increase 130nm in this example.This Increase 38% corresponding to cellar area.All transistors are orientated along the same direction.As design example, the size of transistor It is as follows:

Open gate (PG): W/L=70nm/40nm

Pull down (PD): W/L=85nm/35nm

Pull up (PU): W/L=65nm/35nm

This example obtains x*y=0.72 μm * 0.475 μm=0.342 μm in 45nm processing node²。

Figure 52 shows the system 5200 of a certain number of functional units including using interconnection 5210 to interconnect as needed. For example, in some cases, interconnection 5210 is provided for all functional unit 5204-1,5204-2,5204-3 to 5204-n Between the common path that communicates.In other cases, interconnection provides point to point link between one group of functional unit, provides simultaneously The public communication path between another group of functional unit.Interconnection 5210 can thus be made with being suitable for meeting system designer With for using the communication that available functional unit (including for example wired, radio broadcasting and point-to-point) carries out in goal systems Traditional technology target any mode and construct." n " in 5204-n is meant to indicate to have to be recognized with system designer For more functional units as needing, and there is no suggestion that there are most nine functional units.

According to some embodiments, system 5200 is that have the electronic system of multiple individual packages components and/or sub-component.This Example today of kind of system includes personal computer, mobile phone, digital music player, E-book reader, game behaviour Make platform, portable game system, cable cover top box, TV, stereoscopic device and similar to disclosed technology being proposed from there The increase of the power consumption of confession controls and any other electronic equipment of benefited electronic system.In such a system, functional unit 5201, 5201,5203,5204-1 to 5204-n is the common system unit for this system, and interconnection 5210 is usually used Printing plate or the setting of backplane (not shown).For example, in the case of a personal computer, functional component includes CPU, system The mass storage device of memory access and such as hard disk drive or solid-state disk drive, all of the above can be according to need It to be interconnected by the system interconnection implemented on motherboard.Similarly, mobile phone for example including it is various one or more Chip and display panel, all of the above is usually using one or more printed circuit board that may include flexible connector (PWB) it interconnects.

According to other embodiments, system 5210 is system in package (SIP), wherein each functional unit is integrated circuit, All functional units are encapsulated in together in single multi-chip package.In SIP system, interconnection 5210 can be by such as cable ties Conjunction, wire bonding, soldered ball or gold stud bumps direct chip interconnected to chip, and mentioned by interconnection that package substrate provides For package substrate can be for example including public bus type interconnection, point-to-point interconnection, voltage plane and ground plane.

According to another embodiment, system 5200 is the one single chip of such as system-on-chip (SOC), and functional unit is real It applies as (for example, when block CMOS and soi structure are implemented on soi substrates) common semiconductor substrate or semiconductor upper insulator Transistor group (for example, circuit module or unit) on substrate.In this implementation, interconnection 5210 can be used can be used for by Any technology of circuit module interconnection in integrated circuit provides.

As described above, discussed transistor and integrated circuit technique permission manufacture and use in common semiconductor substrate It can independently specify, statically design and/or dynamically adjust body bias and/or operate the multi-mode transistor of voltage. These identical technologies can also provide identical benefit with system level, even if just one functional unit implements the skill Art.For example, functional unit 5202 may include adjusting the operation mode of DDC transistor dynamically to reduce the logic of power consumption (not It shows).This can for example be completed by the number or analogue technique implemented on functional unit 5202.Optionally, function Unit 5202 can control function in response to the external control signal from another functional unit (for example, functional unit 5201) Consumption.Regardless of each functional unit power consumption be locally controlled by functional unit, controlled by controller function unit center or Person controls in a mixed manner, is able to achieve and more controls power consumption.

Power consumption system level control be it is known, especially in computing systems.For example, advanced construction and power interface (ACPI_) specification is the open standard of the electrical management for the system unit that operating system carries out.Above-described depth exhaust channel, Transistor and integrated circuit technique are controlled by the system of the individual circuit module in each functional unit in permission system Supplement and extend the ability of this electric power management mode.For example, be device level by the control of the ACPI floor level provided, The functional unit (for example, chip or hard disk drive) of multiple component system corresponding to such as personal computer.Offer is provided To the granularity unit control of the power consumption of the individual circuit module in device, many more devices and system power states are feasible 's.

System level electrical management is particularly advantageous in the SOC system using DDC structure.As described above, DDC structure permits Perhaps high-caliber programmability in nanoscale transistors.Because of available nominal threshold voltage V_TRelatively wide range, phase To low σ V_TAnd the relatively high ontology coefficient of DDC structure, difference is used by circuit module bias on circuit module Practical V_TPotentially different practical operation voltage V_DD, in power rise to carry out operating it under apparent operation mode After can construct and be all manufactured with identical intrinsic V_TAnd with identical operation voltage V_DDThe transistor of operation.This flexible permission Identical chip is designed to be used under various goal systems and operating condition, and is dynamically configured to the operation at scene.This is right System is particularly useful, but regardless of be sometimes connected to AC power supplies and other times using battery supply SOC how.

Figure 53 shows a certain number of systems 5301 interconnected including using interconnection 5310 as needed, 5302 and 5303 network 5300.For example, in some cases, interconnection 5310, which is provided, to be communicated for system 5304-1 between 5304-n Common path.In other cases, interconnection provides the communication of point-to-point between one group of system, while providing another group of system Between public communication path.Interconnection 5310 can thus be connected with being suitable for meeting network designer using for use The mesh of the traditional technology communicated to the system of target network (including for example wired, radio broadcasting, point-to-point and end-to-end) Any mode of target and construct." n " in 5304-n is meant to indicate the system that can permit with network as many, and does not have Imply the presence of most nine functional units.

Above-described deepdepletion channel, transistor, integrated circuit and systems technology are provided to being connected to network The ability of the height granularity control of system.There is this high level control to reduce cost of energy to enterprise network networked system It is particularly useful in terms of (it is caused by standby but not used equipment).It is opened regardless of auxiliary control power consumption, depending on subscribing to aspect Open or close system capability, selectively by certain functional unit or its operation mode for being partially disposed in higher execution (for example, " enhancement mode ") to enhance performance.

Figure 54 diagram is such as joined using the exemplary method of such as system referring to described in Figure 52 no matter individually still combining According to network shown in Figure 53.After step 5410 system energization, system in response to provided by network external signal, by being The central mode control signal or the list in each functional unit that can be carried out multi-mode operation that functional unit in system provides The local mode control signal that solely generates and set using the transistor of each type for discussing herein, transistor group and/or Integrated circuit and the power mode of system unit (for example, functional unit) formed.As described above, single component can have structure Cause the different piece operated in different mode；For example, a part of component can be configured to operate in old-fashioned mode, and Another part of same parts can be configured to operate in low-power, low-leakage mode.In step 5430, system monitoring its make To determine whether to change its power mode.Function for monitoring can be executed by a functional unit in center, can be distributed to more A functional unit, each functional unit can carry out the part judgement, or both about mode based on monitoring specified conditions It carries out (for example, a functional unit can should enter sleep pattern based on the standard determination of itself, but regardless of central monitor Not yet determine for whole system to be placed in deep sleep；Similarly, central monitor, which can be determined that, is placed in deep sleep for whole system In, determine for itself to be placed in enhancement mode but regardless of in order to enhance performance in the latter component of initial mode setting). Step 5430 repeats, and the state until being determined as system or functional unit is varied, so that the power mode to be looked for novelty, In this case, executing step 5440.As indicated, system is in step if being judged to that system power is required to decline in step 5440 Rapid 5450 close.Otherwise, depending on which kind of state change required, step 5420 is repeated for one or more functional unit. By this method, it can be benefited from its advantage using the user of the system of technology described herein or chip.

Although having been described and certain example embodiments being shown in the accompanying drawings, it is to be understood that these embodiments are only to show Example property, be not wide invention is limited, and the present invention it is unrestricted in shown and described specific construction with Arrangement, because those skilled in the art is contemplated that various other modifications.Thus, the description and the appended drawings be considered as it is exemplifying and It is not limiting.

Claims

1. a kind of semiconductor devices, comprising:

First cmos circuit and the second cmos circuit, are formed in corresponding trap, and including multiple deepdepletion channel field-effects Transistor (FET)；

Each deepdepletion slot field-effect transistor includes shielding area, is electrically connected to each corresponding trap；Threshold Threshold voltage adjustment region, above the shielding area；Undoped with channel region, in the threshold voltage adjustments overlying regions； Gate stack is located above the undoped channel region, to control the drain electrode and the source electrode that are located at the gate stack two sides Between electric conductivity；Wherein

The trap of first cmos circuit is subjected to the first noumenon bias, and the trap of second cmos circuit is subjected to and is different from Second body bias of the first noumenon bias；And

Wherein, it in the depth profile of dopant, is not deposited between the threshold voltage adjustments region and the shielding area In local minimum.

2. a kind of semiconductor devices, including the first circuit module and second circuit module,

First circuit module includes the first field effect transistor,

First field effect transistor includes:

First dopant well has the first concentration of dopant；

First grid is located above first dopant well, to control the electric conductivity between the first drain electrode and the first source electrode；

First, undoped with channel, has and is less than 5x10¹⁷Atom/cm³The second concentration of dopant, described first undoped with channel position Between first drain electrode and the first source electrode and it is located at below the first grid；

First shielding area, has third concentration of dopant, and the third concentration of dopant is greater than described first undoped with channel Ten times of the second concentration of dopant, and be greater than first concentration of dopant；

First threshold voltage adjustment region is located at described first undoped between channel and first shielding area, to change Become the threshold voltage of first field effect transistor, the first threshold voltage adjustment region, which has, is less than third doping 4th concentration of dopant of agent concentration；And

The first noumenon interconnecting piece is electrically connected to first dopant well, so that first dopant well is provided with the first noumenon Bias；

Second circuit module includes the second field effect transistor,

Second field effect transistor includes:

Second dopant well has the 5th concentration of dopant；

Second grid is located above second dopant well, to control the electric conductivity between the second drain electrode and the second source electrode；

Second, undoped with channel, has and is less than 5x10¹⁷Atom/cm³The 6th concentration of dopant, described second undoped with channel position Between second drain electrode and the second source electrode and it is located at below the second grid；

Secondary shielding region, has the 7th concentration of dopant, and the 7th concentration of dopant is greater than described second undoped with channel Ten times of the 6th concentration of dopant, and be greater than the 5th concentration of dopant；

Second threshold voltage adjustment region is located at described second undoped between channel and the secondary shielding region, to change Become the threshold voltage of second field effect transistor, the second threshold voltage adjustment region, which has, is less than the 7th doping 8th concentration of dopant of agent concentration；And

Second ontology interconnecting piece is electrically connected to second dopant well, so that second dopant well is provided with the second ontology Bias；

Wherein first dopant well is isolated with second dopant well, the first noumenon bias by with second ontology Bias is mutually provided independently, and first circuit module works in first mode, and the second circuit module works in Two modes, the first mode are different from the second mode；And

Wherein, in the depth profile of dopant, in the first threshold voltage adjustment region and first shielding area Between be not present local minimum.

3. semiconductor devices according to claim 2, wherein the first mode or the second mode are static state settings 's.

4. semiconductor devices according to claim 2, wherein the first mode or the second mode are dynamic settings 's.

5. a kind of semiconductor devices, including multiple circuit modules,

Each circuit module includes field effect transistor,

The field effect transistor includes:

Dopant well has the first concentration of dopant；

Undoped with channel, has and be less than 5x10¹⁷Atom/cm³The second concentration of dopant, the undoped channel is located at the leakage Between pole and the source electrode and it is located at below the grid；

Shielding area, has third concentration of dopant, and second of the third concentration of dopant greater than the undoped channel is mixed Ten times of miscellaneous dose of concentration, and it is greater than first concentration of dopant；

Threshold voltage adjustments region, be located at it is described undoped between channel and the shielding area, to change the field-effect The threshold voltage of transistor, the threshold voltage adjustments region have dense less than the 4th dopant of the third concentration of dopant Degree；And

The dopant well that wherein each circuit module has is isolated with other circuit modules, the multiple circuit module it is each Body bias is independent from each other, and each circuit module works in mode different from each other；And

6. semiconductor devices according to claim 5, wherein the mode is static state setting.

7. semiconductor devices according to claim 5, wherein the mode is dynamic setting.