TWI518476B - Synchronization method and clock generating device thereof - Google Patents

Description

Synchronization method and clock generation device thereof

The invention relates to a synchronization method and a clock generation device thereof, in particular to a synchronization method and a clock generation device which can be realized by a hardware and a software.

In an electronic system, the clock signal between the signal transmitting end and the signal receiving end often has a clock deviation. Therefore, when transmitting signals between circuits in an electronic system, it is necessary to synchronize the clock signals of the circuits to make the electronic system work normally.

In general, conventional electronic systems often use phase-locked loops implemented by pure hardware to synchronize clock signals. However, the phase-locked loop implemented by pure hardware takes a lot of time to synchronize the program, and it is impossible to synchronize the signals in real time. In addition, the phase-locked loop realized by pure hardware cannot control the time required for synchronizing signals according to different operating states. From the above, it is known that there is a need for improvement in the prior art.

In order to solve the above problems, the present invention provides a synchronization method that can be implemented together with a hardware and a soft body, and a clock generation device thereof.

The present invention discloses a synchronization method for a clock generation apparatus including a clock generation unit and an operation unit, the synchronization method including a synchronization period in which the synchronization signal is counted by the clock generation unit; a signal, the clock generating unit generates a first interrupt signal to the operation unit, so that the operation unit obtains the synchronization period; according to a control signal, The pulse generating unit generates a pulse width modulation signal, and counts a phase difference between the synchronization signal and the pulse width modulation signal; and according to the pulse width modulation signal, the clock generation unit generates a second interruption signal to The arithmetic unit is configured to cause the arithmetic unit to obtain the phase difference; and the control unit adjusts the control signal according to the synchronization period, a modulation period of the pulse width modulation signal, the phase difference, and a preset value.

The present invention further provides a clock generation device, including a clock generation unit for counting a synchronization period of the synchronization signal, generating a first interrupt signal according to the synchronization signal, and generating a pulse width modulation signal according to a control signal. And counting a phase difference between the synchronization signal and the pulse width modulation signal, and generating a second interrupt signal according to the pulse width modulation signal; and an operation unit for obtaining the synchronization period according to the first interrupt signal And obtaining the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse width modulation signal, and the phase difference.

10‧‧‧ Clock generating device

100‧‧‧ clock generation unit

102‧‧‧ arithmetic unit

40‧‧‧Synchronization method

400~414‧‧‧Steps

CON‧‧‧ control serial number

INC‧‧‧Sum

PER_DIFF‧‧‧cycle difference

PER_SYNC, PER_PWM‧‧ ‧ cycle

PHA_DIFF‧‧‧ phase difference

PWM‧‧‧ pulse width modulation signal

REF‧‧‧Preset value

SYNC‧‧‧sync signal

T1_1~T1_5, T2_1~T2_5, T3_1~T3_5‧‧‧

W1, W2‧‧ ‧ weights

FIG. 1 is a schematic diagram of a clock generation apparatus according to an embodiment of the present invention.

Fig. 2 is a timing chart of the relevant signals when the clock generating device is operated as shown in Fig. 1.

Fig. 3 is another timing chart of the related signals when the clock generating device is operated as shown in Fig. 1.

FIG. 4 is a flowchart of a synchronization method according to an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a clock generating apparatus 10 according to an embodiment of the present invention. The clock generating device 10 is configured to generate a pulse width modulation signal PWM synchronized with the synchronization signal SYNC according to the synchronization signal SYNC generated by the pre-stage circuit (not shown in FIG. 1). As shown in FIG. 1, the clock generation device 10 includes a pulse generation unit 100 and an arithmetic unit 102. The clock generation unit 100 is configured to receive the synchronization signal SYNC and according to A control signal CON generates a pulse width modulation signal PWM. The clock generation unit 100 is further configured to separately calculate a period PER_SYNC of the synchronization signal SYN and a phase difference PHA_DIFF between the synchronization signal SYN and the pulse width modulation signal PWM. In addition, the clock generation unit 100 generates an interrupt signal INT1, INT2 to the arithmetic unit 102 according to the synchronization signal SYNC and the pulse width modulation signal PWM. The computing unit 102 can be a microprocessor or an application-specific integrated circuit (ASIC) for obtaining the period PER_SYNC and the phase difference PHA_DIFF according to the interrupt signals INT1 and INT2. Based on the obtained period PER_SYNC and phase difference PHA_DIFF, the operation unit 102 can adjust the control signal CON to synchronize the pulse width modulation signal PWM with the synchronization signal SYNC. In this case, since the operation flow of adjusting the control signal CON is implemented in the operation unit 102 in a software manner, the user can easily adjust the parameter setting of the control signal CON, thereby controlling the synchronization signal SYNC according to different applications and design concepts. The synchronization process between the pulse width modulation signals PWM (such as the time required to control the synchronization process between the synchronization signal SYNC and the pulse width modulation signal PWM).

In detail, when the clock generation unit 100 receives the synchronization signal SYNC from the previous stage circuit, the period PER_SYNC of the synchronization signal SYNC is also calculated. Through the interrupt signal INT1, the clock generation unit 100 instructs the operation unit 102 to calculate the period PER_SYNC, and the operation unit 102 thus reads the period PER_SYNC of the synchronization signal SYNC. Next, the clock generation unit 100 generates a pulse width modulation signal PWM according to the control signal CON, and simultaneously counts the phase difference PHA_DIFF between the synchronization signal SYN and the pulse width modulation signal PWM. Through the interrupt signal INT2, the clock generation unit 100 instructs the arithmetic unit 102 that the phase difference PHA_DIFF has been calculated, and the arithmetic unit 102 thus reads the phase difference PHA_DIFF. Since the one cycle PER_PWM of the pulse width modulation signal PWM and the start time TS are set by the control signal CON generated by the operation unit 102, the operation unit 102 can know the cycle PER_PWM. According to the period PER_SYNC, PER_PWM and phase difference PHA_DIFF, the operation unit 102 can adjust the control signal CON to synchronize the synchronization signal SYNC and the pulse width modulation signal PWM.

The operation of the arithmetic unit 102 to adjust the control signal CON based on the period PER_SYNC, PER_PWM, and phase difference PHA_DIFF is described below. When the absolute value of the phase difference PHA_DIFF is greater than a predetermined value REF (ie, | PHA_DIFF |> REF ), the operation unit 102 determines that the frequency phase difference between the synchronization signal SYNC and the pulse width modulation signal PWM is too large, and the operation unit 102 performs a coarse adjustment. program. In the coarse adjustment procedure, the arithmetic unit 102 advances or delays the start time TS of the pulse width modulation signal PWM according to the phase difference PHA_DIFF. In this embodiment, when the phase difference PHA_DIFF is greater than the preset value REF (ie, PHA_DIFF > REF ), the operation unit 102 advances the start time TS by a preset time TP; and when the phase difference PHA_DIFF is less than the negative preset value At the time of REF (i.e., PHA_DIFF <- REF ), the arithmetic unit 102 delays the start time TS by the preset time TP. For example, the preset value REF can be set to 2 milliseconds (ms) and the preset time TP can be set to 0.1 milliseconds.

On the other hand, when the absolute value of the phase difference PHA_DIFF is less than or equal to the preset value REF (ie | PHA_DIFF | REF ), the arithmetic unit 102 performs a fine adjustment procedure. In the fine adjustment procedure, the arithmetic unit 102 calculates the period difference PER_DIFF between the periods PER_SYNC and PER_PWM, and adds the product of the period difference PER_DIFF and the phase difference PHA_DIFF to the weights W1 and W2, respectively, as a sum INC (ie INC = PER_DIFF) × W 1+ PHA_DIFF × W 2) . After obtaining the sum INC, the arithmetic unit 102 subtracts the start time INC from the sum INC. Finally, according to the operation result obtained by the above process, the operation unit 102 adjusts the control signal CON before the next pulse of the synchronization signal SYNC according to the interrupt signal INT2, so that the clock generation unit 100 can temporarily according to the next pulse of the synchronization signal SYNC. The control signal CON generates a pulse width modulation signal PWM. In this way, the pulse width modulation signal PWM can be quickly synchronized with the synchronization signal SYNC. In addition, the user can adjust the time required for the synchronization process between the synchronization signal SYNC and the pulse width modulation signal PWM through the design of the weights W1 and W2. For example, the weights W1, W2 can be set to 0.25.

Please refer to FIG. 2, which is a timing chart of related signals when the clock generating device 10 is operated as shown in FIG. 1. As shown in FIG. 2, at time T1_1, the clock generation unit 100 receives the rising edge of the synchronization signal SYNC, and the clock unit 100 instructs the operation unit 102 to acquire the synchronization signal SYNC through the interrupt signal INT1. Period PER_SYNC_1. At this time, the clock generation unit 100 also starts counting the phase difference PHA_DIFF_1 between the synchronization signal SYNC and the pulse width modulation signal PWM. At the time point T2_1, the clock generation unit 100 generates a rising edge of the pulse width modulation signal PWM, and the clock generation unit 100 completes the calculation of the phase difference PHA_DIFF_1, and instructs the operation unit 102 to acquire the phase difference PHA_DIFF_1 through the interrupt signal INT2. The arithmetic unit 102 can adjust the control signal CON according to the obtained period PER_SYNC_1 and the phase difference PHA_DIFF and the period PER_PWM_1 set by itself. Since the phase difference PHA_DIFF_1 is greater than the preset value REF, the operation unit 102 reduces the start time TS of the initial pulse width modulation signal PWM by the preset control time TP by adjusting the control signal CON. It should be noted that the operation unit 102 performs the adjustment of the control signal CON at the falling edge of the pulse width modulation signal PWM (ie, the time point T3_1) according to the interrupt signal INT2.

Similarly, the clock generation unit 100 receives the rising edge of the synchronization signal SYNC at time T1_2, and instructs the operation unit 102 to acquire the period PER_SYNC_2 of the previous period of the synchronization signal SYNC through the interrupt signal INT1. At this time, the clock generation unit 100 also starts counting the phase difference PHA_DIFF_2 between the synchronization signal SYNC and the pulse width modulation signal PWM. At time point T2_2, the clock generation unit 100 generates a rising edge of the pulse width modulation signal PWM, and the clock generation unit 100 completes the calculation of the phase difference PHA_DIFF_2, and instructs the arithmetic unit 102 to acquire the phase difference PHA_DIFF_2 through the interrupt signal INT2. Since the phase difference PHA_DIFF_2 is still greater than the preset value REF, the operation unit 102 reduces the start time TS of the initial pulse width modulation signal PWM by the preset time TP by adjusting the control signal CON, and so on.

Up to the time point T2_4, the arithmetic unit 102 determines that the phase difference PHA_DIFF_4 is smaller than the preset value REF, and the arithmetic unit 102 calculates the sum INC of the period difference PER_DIFF and the phase difference PHA_DIFF multiplied by the weights W1, W2, respectively, and subtracts the start time TS. Sum INC. In this way, the pulse width modulation signal PWM can catch up with the synchronization signal SYNC when the next pulse of the synchronization signal SYNC is generated (ie, time T1_5).

The pulse width modulation signal PWM can be synchronized with the synchronization signal SYNC in two cycles of the synchronization signal SYNC through the appropriate setting preset value REF and the weights W1 and W2. Please refer to FIG. 3, which is a timing chart of the related signals when the clock generating device 10 is operated as shown in FIG. 1. Similar to FIG. 2, the clock generation unit 100 receives the rising edge of the synchronization signal SYNC at time T1_1, thereby instructing the arithmetic unit 102 to acquire the period PER_SYNC_1 of the previous period of the synchronization signal SYNC through the interrupt signal INT1. At this time, the clock generation unit 100 also starts counting the phase difference PHA_DIFF_1 between the synchronization signal SYNC and the pulse width modulation signal PWM. At the time point T2_1, the clock generation unit 100 generates a rising edge of the pulse width modulation signal PWM, and the clock generation unit 100 completes the calculation of the phase difference PHA_DIFF_1, and instructs the operation unit 102 to acquire the phase difference PHA_DIFF_1 through the interrupt signal INT2. In this embodiment, since the phase difference PHA_DIFF_1 is smaller than the preset value REF, the operation unit 102 calculates the sum INC of the period difference PER_DIFF and the phase difference PHA_DIFF multiplied by the weights W1, W2, respectively, and subtracts the start time TS from the sum INC. . By adjusting the control signal CON at time T3_1, the rising edge of the pulse width modulation signal PWM can be aligned with the rising edge of the synchronization signal SYNC at time T1_2. In this way, at time T1_3, the arithmetic unit 102 can know that the phase difference PHA_DIFF is 0, and the pulse width modulation signal PWM and the synchronization signal SYNC have been synchronized.

The flow of the clock generation device 10 to synchronize the pulse width modulation signal PWM and the synchronization signal SYNC can be summarized as a synchronization method 40, as shown in FIG. The synchronization method 40 can be used for a clock generation device including a clock generation unit and an operation unit (such as the clock generation device of FIG. 1) Set 10), and include the following steps: Step 400: Start.

Step 402: Counting, by the clock generation unit, a synchronization period of a synchronization signal.

Step 404: The clock generation unit generates a first interrupt signal to the operation unit according to the synchronization signal, so that the operation unit obtains a synchronization period of the synchronization signal.

Step 406: According to a control signal, the clock generation unit generates a pulse width modulation signal, and counts a phase difference between the synchronization signal and the pulse width modulation signal.

Step 408: According to the pulse width modulation signal, the clock generation unit generates a second interrupt signal to the operation unit, so that the operation unit obtains the phase difference.

Step 410: Determine the magnitude of the phase difference. If the phase difference is greater than the preset value, go to step 412. If the phase difference is less than or equal to the preset value, go to step 414. If the phase difference is 0, go to step 402.

Step 412: Perform a coarse adjustment procedure.

Step 414: Perform a fine tuning procedure.

According to the synchronization method 40, the clock generation device can catch the pulse width modulation signal up to the synchronization signal within 2 cycles of the synchronization signal. That is to say, the clock generation device can synchronize the pulse width modulation signal and the synchronization signal in the two cycles of the synchronization signal at the fastest. The user can flexibly set the time required for the clock generating device to perform synchronization by appropriately designing the preset value and the weights corresponding to the phase difference and the period difference in the fine adjustment program, respectively. The detailed operation process of the synchronization method 40 can be referred to the above. For the sake of brevity, no further details are provided herein.

In summary, the clock generation device of the above embodiment uses the transmission of the interrupt signal to control the calculation of the parameters by the arithmetic unit in the clock generation device through the software, so that the pulse width modulation signal generated by the clock generation device is synchronized. The synchronization signal generated by the previous stage circuit. Accordingly, the time required for the clock generating apparatus of the above embodiment to perform synchronization can be optimized, and the user can root The time required to perform synchronization is flexibly controlled according to different applications and design concepts.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

40‧‧‧Synchronization method

400~414‧‧‧Steps

Claims (16)

A synchronization method for a clock generation device including a clock generation unit and an operation unit, the synchronization method includes: a synchronization period in which the synchronization signal is counted by the clock generation unit; and according to the synchronization signal, The clock generating unit generates a first interrupt signal to the operation unit, so that the operation unit obtains the synchronization period; according to a control signal, the clock generation unit generates a pulse width modulation signal, and counts the synchronization. a phase difference between the signal and the pulse width modulation signal; according to the pulse width modulation signal, the clock generation unit generates a second interrupt signal to the operation unit, so that the operation unit obtains the phase difference; The synchronization period, a modulation period of the pulse width modulation signal, the phase difference, and a preset value are adjusted by the operation unit. The synchronization method of claim 1, wherein the synchronization signal is transmitted to the clock generation unit by a pre-stage circuit. The synchronization method of claim 1, wherein the phase difference is a time difference between a rising edge of the synchronization signal and a rising edge of the subsequent pulse width modulation signal. The synchronization method of claim 1, wherein the step of adjusting the control signal by the operation unit according to the synchronization period, the modulation period of the pulse width modulation signal, the phase difference, and the preset value comprises: When the absolute value of the phase difference is greater than the preset value, a coarse adjustment procedure is performed. The synchronization method of claim 4, wherein when the absolute value of the phase difference is greater than the preset value, the step of performing the coarse adjustment procedure comprises: When the phase difference is greater than the preset value, the control signal is adjusted to reduce a start time of the pulse width modulation signal. The synchronization method of claim 4, wherein when the absolute value of the phase difference is greater than the preset value, the step of performing the coarse adjustment procedure comprises: adjusting the phase difference when the phase difference is less than the negative preset value Controlling the signal to increase the start time of the pulse width modulation signal. The synchronization method of claim 1, wherein the step of adjusting the control signal by the operation unit according to the synchronization period, the modulation period of the pulse width modulation signal, the phase difference, and the preset value comprises: When the absolute value of the phase difference is less than or equal to the preset value, a fine adjustment procedure is performed. The synchronization method of claim 7, wherein when the absolute value of the phase difference is less than or equal to the preset value, the step of performing the fine adjustment procedure comprises: calculating a period difference between the synchronization period and the modulation period Calculating a first product of the period difference and a first weight; calculating a second product of the phase difference and a second weight; adding the first product to the second product to obtain a sum; and adjusting The control signal is such that the start time of the pulse width modulation signal is reduced by the sum. A clock generation device includes: a clock generation unit configured to count a synchronization period of the synchronization signal, generate a first interrupt signal according to the synchronization signal, generate a pulse width modulation signal according to a control signal, and count the a phase difference between the synchronization signal and the pulse width modulation signal, and generating a second interrupt signal according to the pulse width modulation signal; An arithmetic unit configured to obtain the synchronization period according to the first interrupt signal, obtain the phase difference according to the second interrupt signal, and adjust a phase change period of the pulse width modulation signal according to the synchronization period and the phase difference The control signal. The clock generating device of claim 9, wherein the synchronization signal is transmitted to the clock generating unit by a preceding circuit. The clock generation device of claim 9, wherein the clock generation unit obtains a time difference between a rising edge of the synchronization signal and a rising edge of the subsequent pulse width modulation signal. The clock generating device of claim 9, wherein the arithmetic unit performs a coarse adjustment procedure when the absolute value of the phase difference is greater than the preset value. The clock generating device of claim 12, wherein when the phase difference is greater than the preset value, the operation unit adjusts the control signal to reduce a start time of the pulse width modulation signal. The clock generation device of claim 12, wherein when the phase difference is less than the negative predetermined value, the operation unit adjusts the control signal to increase a start time of the pulse width modulation signal. The clock generating device of claim 9, wherein the arithmetic unit performs a fine adjustment procedure when an absolute value of the phase difference is less than or equal to the preset value. The clock generation device of claim 15, wherein the operation unit calculates a period difference between the synchronization period and the modulation period; calculates a first product of the period difference and a first weight; and calculates the phase difference And a second product of a second weight; adding the first product and the second product to obtain a sum; and adjusting the control signal to reduce a start time of the pulse width modulation signal by the sum.