TWI517389B - Gate stack structure with etch stop layer and manufacturing process thereof - Google Patents

Description

Gate stack structure with etch stop layer and method of forming same

SUMMARY OF THE INVENTION The present invention is directed to a method of forming an etch stop layer, and more particularly to a process for improving the growth rate and coverage of an etch stop layer in a gate stack structure.

In the process of forming a complementary metal-oxide-semiconductor volume circuit (CMOS IC), when forming a gate stack structure of a metal-oxide-semi-transistor, it is often found that nitridation as an etch stop layer is performed during work function metal etching. Tantalum (TaN) does not effectively block the etch, which leads to the loss of the bottom linear barrier layer under the etch stop layer, which seriously affects product performance and yield, resulting in reduced product reliability.

The main purpose of the present invention is to form a U-type repair layer having electrical properties and materials similar to the linear barrier layer on the linear barrier layer whose surface structure has been broken, thereby improving the subsequent etching termination layer by using the U-type repair layer. The growth rate and thickness in the trench of the gate stack structure further improve the leakage current of the gate stack structure.

Therefore, in accordance with the purpose of the present invention, the present invention provides a gate stack structure having an etch stop layer comprising a substrate; and a gate stack structure disposed over the substrate and having a spacer in the gate stack structure On the sidewall, the gate stack structure comprises: a gate dielectric layer disposed on the substrate; a linear barrier layer disposed on the gate dielectric layer; and a U-type repair layer disposed on the surface of the linear barrier layer and On one of the inner side walls of the spacer; an etch stop layer disposed on the surface of the U-type repair layer and on the sidewall of the trench; and a metal layer disposed in the etch stop layer.

According to the above gate stack structure having an etch stop layer, the present invention also provides A method for forming an etch stop layer, the method comprising: providing a substrate; forming a gate stack structure over the substrate, the gate stack structure comprising at least a sacrificial polysilicon layer and a linear barrier layer; removing the sacrificial polysilicon layer Forming a trench and exposing a surface of the linear barrier layer in the gate stack structure; forming a U-type repair layer on a sidewall surface of the trench and a surface of the linear barrier layer; and on the sidewall of the U-type repair layer and the trench An etch stop layer is formed.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The direction in which the present invention is discussed herein is a gate stack structure having an etch stop layer and a method of forming the same. In order to thoroughly understand the present invention, a detailed gate stack structure and manufacturing steps thereof will be presented in the following description. Obviously, the practice of the present invention does not limit the specific details familiar to those skilled in the art of the gate stack structure. However, the preferred embodiment of the present invention will be described in detail below. The present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited thereto, and may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of patent protection of the present invention is defined by the scope of the claims appended hereto.

1 is a schematic view showing formation of a gate dielectric layer, a linear barrier layer, and a sacrificial polysilicon layer on a substrate; FIG. 2 is a gate stack structure defined above the substrate and a contact hole etch stop layer formed on the gate stack structure; Schematic diagram of the inner dielectric layer; FIG. 3 is a schematic view showing the formation of a linear barrier layer and an etch stop layer in the gate stack structure; FIG. 4 is a U-type repair layer and etching stop in the trench of the gate stack structure; A schematic diagram of a layer; and FIG. 5 is a schematic diagram showing the formation of an N-type work function metal layer in a trench of a gate stack structure.

Please refer to FIG. 1 , which is a schematic diagram showing the formation of a gate dielectric layer, a linear barrier layer and a polysilicon layer on a substrate. In FIG. 1, a substrate 10 having a plurality of isolation devices 102 is provided first. Then, using a general deposition process such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD, Physical vapor deposition) A gate dielectric layer 12 having a high dielectric constant is formed on the substrate 10. The gate dielectric layer 12 having a high dielectric constant generally has a dielectric constant greater than 4, and the material of the gate dielectric layer 12 may be bismuth oxynitride, metal oxide or metal oxide. Silicon oxide), for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, tantalum oxide or aluminum oxide. In addition, an interfacial layer such as a hafnium oxide layer may be selectively formed under the gate dielectric layer 12.

Next, a linear barrier layer 14 and a dummy polysilicon 16 are formed on the gate dielectric layer 12. The material of the linear barrier layer 14 is titanium nitride (TiN) or tantalum nitride (TaN) or a combination of the two, and is formed on the gate dielectric layer 12 in a thickness ranging from 15 Å to 25 Å. É (Å). A mask layer (not shown) may be selectively formed on the sacrificial polysilicon layer 16, and the material of the mask layer may be tantalum nitride, hafnium oxide, hafnium oxynitride or tantalum carbide.

Referring next to FIG. 2, a gate stack structure is defined over the substrate and a contact hole etch stop layer and an inner dielectric layer are formed on the gate stack structure. First, a patterned photoresist layer (not shown) is formed over the sacrificial polysilicon layer 16 shown in FIG. 1. By patterning the photoresist layer, a complementary gold oxide can be defined on the substrate 10. The position of the gate stack structure of the N-type metal oxide semi-transistor (NMOS) and the P-type metal oxide semi-transistor (PMOS) of the semi-transistor. Then, an etching process is performed, A portion of the sacrificial polysilicon layer 16, the linear barrier layer 14 and the gate dielectric layer 12 are sequentially removed to form a gate stack structure 20 over the substrate 10. It is to be noted that the method of the preferred embodiment of the present invention is mainly for solving the problem of the quality of the etch stop layer required for removing the P-type work function metal in the gate stack structure of the N-type MOS transistor. Therefore, the structure of the P-type MOS transistor and its formation method are not the main inventive features of the present invention, and therefore are not stated in the present invention.

Next, referring to FIG. 2, the gate stack structure 20 and the spacer 22 are used as a mask, and an ion implantation step (not shown) is formed in the substrate 10 adjacent to the gate stack structure 20. Source/drain region 21a/21b; then, a contact etch stop layer (CESL) 24 is formed on the substrate 10 and covered with spacers by deposition. The gate of the 22 is stacked on the structure 20. Next, an interlayer dielectric layer (ILD) 26 is formed on the contact hole etch stop layer 24 which has just been formed. Then, a planarization process is performed on the inner dielectric layer 26 and the contact hole etch stop layer 24 over the gate stack structure 20 to remove portions of the inner dielectric layer 26 and the contact hole etch stop layer 24 to The surface of the sacrificial polysilicon layer 16 of the gate stack structure 20 is exposed.

Next, please refer to FIG. 3, which is a schematic diagram showing the formation of a linear barrier layer in the gate stack structure. First, the sacrificial polysilicon layer 16 in the gate stack structure 20 is removed using an etch process to form a trench 32 within the gate stack structure 20 and expose the surface 14a of the linear barrier layer 14. In this embodiment, the etching process includes: performing a first etching process on the sacrificial polysilicon layer 16, such as a dry etching process, to remove a portion of the sacrificial polysilicon layer 16 of the gate stack structure 20; And continuing to perform a second etching process on the remaining portion of the sacrificial polysilicon layer 16, such as wet etching, completely removing the sacrificial polysilicon layer 16 in the gate stack structure 20 and exposing the linear barrier layer Surface 14a of 14 is formed to form a trench 32 within gate stack structure 20. In this embodiment, the wet etching may remove the sacrificial polysilicon layer 16 of the gate stack structure 20 by using an etching solution as a tetramethylammonium hydroxide (TMAH) solution or an ammonia hydroxide (NH ₄ OH). . However, the present invention is not limited thereto, and the sacrificial polysilicon layer 16 may be completely removed by dry etching alone or by wet etching alone.

However, the inventors have discovered that during the removal of the sacrificial polysilicon layer 16, the surface 14a of the linear barrier layer 14 may be eroded by the etching solution or reacted with the etching solution such that the surface 14a of the linear barrier layer 14 is destroyed, or The sacrificial polysilicon layer 16 is not completely removed, and a portion of the sacrificial polysilicon layer 16 (not shown) remains on the surface 14a of the linear barrier layer 14, so that when the etch stop layer 38 is formed in the linear barrier layer When it is 14 on, its formation speed is slow and its coverage is not good.

Therefore, in order to solve the problem of the growth rate and coverage of the etch stop layer in the trench 32, the present invention is in the gate stack structure after removing the sacrificial polysilicon layer 16 of the gate stack structure 20 and exposing the surface of the linear barrier layer 14. A U-shaped repair similar to the electrical and material properties of the linear barrier layer 14 is formed on the sidewall surface 34 of the trench 32 in the trench 32 (i.e., with respect to the inner sidewall of the spacer 22) and the surface 14a of the linear barrier layer 14. Layer 36, such as titanium nitride or titanium, is formed to a thickness of 7 angstroms (Å) to 15 angstroms, as shown in FIG. Then, an etch stop layer 38 is formed on the surface of the U-type repair layer 36 by means of atomic layer deposition (ALD), wherein the material of the etch stop layer 38 is tantalum nitride (TaN). Therefore, it is apparent that in the prior art, since no U-type repair layer 36 is formed on the linear barrier layer 14, the formation of an etch stop layer (not shown) on the linear barrier layer 14 is formed. The thickness is thin and the thickness is 10 angstroms; and when the U-type repair layer 36 is formed on the linear barrier layer 14, if the etch stop layer 38 is formed under the same conditions, the etch stop layer 38 is formed on the U-type repair layer. The thickness of 36 is from 15 angstroms to 25 angstroms. Therefore, by forming the U-type repair layer 36 on the linear barrier layer 14 of the gate stack structure 20, the etch stop layer 38 can have a better growth rate and thickness. The gate stack structure 20 is preferably Coverage.

In addition, in the present invention, after the etch stop layer 38 is formed, a P-type work function metal layer (not shown), such as titanium nitride (TiN), may be further redeposited; In the case of a semi-transistor (NMOS), the P-type work function metal layer is removed from the gate stack structure which is intended to form an N-type MOS transistor, and then used as an N-type gold via an etching process. An N-type metal work function metal layer 40 of an oxygen semi-crystal, such as titanium, hafnium, tantalum or aluminum or an alloy of the above, is formed in the etch stop layer 38 in the trench 32. The inner side wall is then filled with a metal layer 50 having a low resistance value, such as aluminum, that is, a structure of an N-type MOS transistor which completes a complementary MOS transistor, as shown in FIG.

Therefore, it can be known from the method for forming the etch stop layer and the formed gate stack structure that the etch stop layer can be added to the trench of the gate stack structure by the U-type repair layer formed on the linear barrier layer. The growth rate and good coverage also avoid leakage currents and improve component reliability.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧Substrate

102‧‧‧Isolation components

12‧‧‧ gate dielectric layer

14‧‧‧Linear barrier

14a‧‧‧The surface of the linear barrier layer

16‧‧‧ Sacrificial polysilicon layer

20‧‧‧ gate stacking structure

22‧‧‧ spacers

24‧‧‧Contact hole etch stop layer

26‧‧‧ Inner dielectric layer

21a‧‧‧ source area

21b‧‧‧Bungee Area

32‧‧‧ditch

34‧‧‧ sidewall surface (inside side wall)

36‧‧‧U-type repair layer

38‧‧‧etch stop layer

40‧‧‧N type work function metal layer

50‧‧‧metal layer

1 is a schematic diagram showing formation of a gate dielectric layer, a linear barrier layer, and a polysilicon layer on a substrate according to the disclosed technology; FIG. 2 is a schematic diagram of forming a gate above a substrate according to the disclosed technology. a stacked structure and a schematic diagram of forming a contact hole etch stop layer and an inner dielectric layer on the gate stack structure; 3 is a schematic diagram showing the formation of a linear barrier layer in a gate stack structure according to the disclosed technology; FIG. 4 is a diagram showing the formation of a U-type patch in a trench of a gate stack structure according to the disclosed technology. A schematic diagram of a layer and an etch stop layer; and FIG. 5 is a schematic diagram showing the formation of an N-type work function metal layer and a low-resistance metal layer in a trench of a gate stack structure in accordance with the disclosed technology.

10‧‧‧Substrate

102‧‧‧Isolation components

12‧‧‧ gate dielectric layer

14‧‧‧Linear barrier

14a‧‧‧The surface of the linear barrier layer

22‧‧‧ spacers

24‧‧‧Contact hole etch stop layer

26‧‧‧ Inner dielectric layer

21a‧‧‧ source area

21b‧‧‧Bungee Area

32‧‧‧ditch

34‧‧‧ sidewall surface (inside side wall)

36‧‧‧U-type repair layer

38‧‧‧etch stop layer

Claims (19)

A gate stack structure having an etch stop layer, comprising: a substrate; and a gate stack structure disposed over the substrate and having a spacer on a sidewall of the gate stack structure, the gate stack structure comprising a gate dielectric layer disposed on the substrate; a linear barrier layer disposed on the gate dielectric layer; a U-type repair layer disposed on the linear barrier layer and opposite to the spacer On the inner side wall; an etch stop layer is disposed on the U-type repair layer. The gate stack structure having an etch stop layer as described in claim 1, wherein the gate dielectric layer has a dielectric constant greater than 4. A gate stack structure having an etch stop layer as described in claim 1, wherein the linear barrier layer is titanium nitride (TiN). A gate stack structure having an etch stop layer as described in claim 1, wherein the linear barrier layer has a thickness ranging from 15 Å to 25 Å. The gate stack structure having an etch stop layer according to claim 1, wherein the material of the U-type repair layer is titanium nitride (TiN) or titanium (Ti). The gate stack structure having an etch stop layer as described in claim 1, wherein the U-type repair layer has a thickness ranging from 7 angstroms to 15 angstroms. A gate stack having an etch stop layer as described in claim 1 The structure wherein the etch stop layer is tantalum nitride (TaN). A gate stack structure having an etch stop layer as described in claim 1, wherein the etch stop layer has a thickness ranging from 15 angstroms to 25 angstroms. A gate stack structure having an etch stop layer as described in claim 1, wherein an N-type work function metal layer is disposed on an inner side surface of the etch stop layer. The gate stack structure having an etch stop layer according to claim 9, wherein the material of the N-type work function metal layer is: hafnium, titanium, tantalum, and aluminum (aluminum) And selected from the group consisting of the above metal alloys. A method for forming an etch stop layer, the method comprising: providing a substrate; forming a gate stack structure over the substrate, the gate stack structure comprising at least a sacrificial polysilicon layer and a linear barrier layer; removing the sacrificial polysilicon Forming a trench to expose the surface of the linear barrier layer in the gate stack structure; forming a U-type repair layer on a sidewall surface of the trench and the surface of the linear barrier layer; and in the U-type repair An etch stop layer is formed on the surface of the layer and on the sidewall of the trench. The method of forming the method of claim 11, wherein the step of removing the sacrificial polysilicon layer in the gate structure comprises: Performing a first etching process on the sacrificial polysilicon layer to remove a portion of the sacrificial polysilicon layer; and performing a second etching process on the remaining portion of the sacrificial polysilicon layer to completely remove the gate stack structure The sacrificial polysilicon layer. The method of forming according to claim 12, wherein the first etching process is a dry etching process. The method of forming according to claim 12, wherein the second etching process is a wet etching process. The method of forming according to claim 11, wherein the U-type repair layer is formed to have a thickness of 7 angstroms to 15 angstroms. The method of forming according to claim 11, wherein the material of the U-type repair layer is titanium nitride (TiN) or titanium. The method of forming according to claim 11, wherein the method of forming the etch stop layer is an atomic layer deposition. The method of forming according to claim 11, wherein the material of the etch stop layer is tantalum nitride. The method of forming according to claim 11, wherein the etch stop layer is formed to have a thickness ranging from 15 angstroms to 25 angstroms.