KR100896862B1 - Method for fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: a gate electrode composed of a gate metal sequentially stacked on a gate insulating film on a semiconductor substrate and a silicided capping silicon layer, an LDD region formed on semiconductor substrates on both sides of the gate electrode, A gate spacer is formed on both sides of the gate electrode, and the semiconductor substrate on both sides of the gate electrode is connected to the LDD region, and includes a silicided source / drain region. Accordingly, the present invention not only suppresses the poly depletion phenomenon occurring in the application device of the conventional polysilicon gate by applying a thin metal gate and silicided polysilicon as the gate electrode, By effectively reducing the EOT, the performance of the semiconductor device is improved, and the source / drain regions are silicided to effectively reduce the resistance of the source / drain regions, thereby further improving the performance of the semiconductor device, thereby requiring high speed. It has an effect that can be suitably applied to a semiconductor device.

Gate metal, capping silicon layer, silicided, source / drain regions

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1A to 1D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

11 semiconductor substrate 12 device isolation film

13,13a: gate insulating film 14,14a: gate metal

15,15a: capping silicon layer 15b: silicided capping silicon layer

16 gate electrode 17 LDD region

18: gate spacer 19: source / drain region

19a: silicided source / drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, poly depletion generated in an application device of a conventional poly silicon gate by applying a thin metal gate and silicided poly silicon as a gate electrode. The present invention relates to a method for manufacturing a semiconductor device capable of suppressing the phenomenon and improving the performance of the semiconductor device by having a silicided source / drain region.

In general, a metal-oxide semiconductor field effect transistor (MOSFET) device employs a poly Si gate and a SiO 2 -based gate oxide.

However, as the size of a semiconductor device decreases, poly depletion phenomenon occurs in a semiconductor device using a polysilicon gate. As a result, the equivalent oxide thickness (EOT) of the semiconductor device increases, which causes the performance of the semiconductor device to deteriorate.

In order to overcome the disadvantages of the semiconductor device using the polysilicon gate, the MOSFET device uses a metal gate in place of the polysilicon gate.

However, when the metal gate is applied to the semiconductor device, not only is the process complicated by plasma damage and metal residue, etc. generated during the etching process of the metal, but also a problem that causes defects. I had.

In order to overcome the complexity of the process and the possibility of causing defects, the damascene process and the replacement process are applied. However, this is not a fundamental solution to the above-mentioned problem, but the size of the semiconductor device As the size decreases, the resistance of the source / drain regions increases, which lowers the performance of the semiconductor device.

Therefore, there is a need to develop a semiconductor device capable of improving the performance of the semiconductor device and a process for manufacturing the same by overcoming a disadvantage of the process of applying the metal gate to the semiconductor device and reducing the resistance of the source / drain regions.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to simplify the process of applying a metal gate and to minimize the occurrence of defects, and to provide a semiconductor due to the high resistance of the source / drain regions of the semiconductor device. It is to provide a method for manufacturing a semiconductor device that can prevent a decrease in the performance of the device.

The present invention relates to a semiconductor device comprising: a gate electrode composed of a gate metal sequentially stacked on a gate insulating film on a semiconductor substrate and a silicided capping silicon layer; an LDD region formed on semiconductor substrates on both sides of the gate electrode; Gate spacers formed on both sides and semiconductor substrates on both sides of the gate electrode are connected to the LDD region, and include silicided source / drain regions.

In addition, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate electrode comprising a gate metal and a capping silicon layer sequentially stacked on a gate insulating film on a semiconductor substrate, and forming LDD regions on semiconductor substrates on both sides of the gate electrode. Forming a gate spacer on both sides of the gate electrode, forming a source / drain region connected to the LDD region on the semiconductor substrate on both sides of the gate electrode, and forming a capping silicon layer and a source / drain region. Silicidation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

As shown in FIG. 1D, the semiconductor device 10 according to the present invention has a gate metal 14a stacked on a gate insulating film 13a on the semiconductor substrate 11, and silicided capping silicon. Of the gate electrode 16 formed of the layer 15b, the lightly doped drain (LDD) region 17 formed on the semiconductor substrate 11 on both sides of the gate electrode 16, and the gate electrode 16. Gate spacers 18 formed on both sides and the semiconductor substrate 11 on both sides of the gate electrode 16 are formed so as to be connected to the LDD regions 17 and are suicided source / drain regions. (19a).

The gate insulating film 13a formed by evaporation on the semiconductor substrate 11 is made of any one of SixOy series such as SiO2 and SiON, HfxOy series such as HfO2, AlxOy series such as Al2O3, or a compound thereof.

The gate metal 14a is formed of any one of TiN, TaN, HfN, LaN, and Sc, formed on the semiconductor substrate 11 with the gate insulating film 13a therebetween, and stacked and silicided on top. ) And the gate electrode 16 is formed. At this time, the gate metal 14a preferably has a thickness of 5 nm to 40 nm, and the silicided capping silicon layer 15b has a thickness of 40 nm to 150 nm.

The manufacturing process and operation of the semiconductor device 10 according to the present invention will be described in detail together with the manufacturing method of the present invention.

As shown in FIG. 1A, an isolation layer 12 having a shallow trench isolation (STI) structure is formed in a predetermined region of the semiconductor substrate 11. Here, the device isolation layer 12 may form a trench having a predetermined depth in the semiconductor substrate 11, and then fill a gap-fill material in the trench to planarize a process such as a chemical-mechanical polishing (CMP) process. Form through.

When the device isolation layer 12 is formed on the semiconductor substrate 11, the gate insulating layer 13, the gate metal 14, and the capping silicon layer 15 are sequentially stacked on the entire surface of the semiconductor substrate 11.

The gate insulating layer 13 may be formed by applying a material or a compound of SixOy series such as SiO2 or SiON, or by applying a high dielectric material or compound of AlxOy series such as HfO2 or Al2O3 to further improve the performance of a semiconductor device. The semiconductor layer 11 may be formed on the semiconductor substrate 11 using an atomic layer deposition (ALD) process.

The gate metal 14 is preferably made of any one of TiN, TaN, HfN, LaN, Sc, or a compound thereof. At this time, the metal of the NMOS and the PMOS may be differently applied. In addition, the deposition thickness of the gate metal 14 is formed to be thin enough, such as 5nm to 40nm, so as to minimize the damage to the plasma insulating film 13 during the etching process while fully serving as the gate metal.

The capping silicon layer 15 is deposited on the gate metal 14 by a CVD process using poly-Si or Amorphous Si, wherein the deposition temperature is preferably 600 ° C. to 850 ° C., which will be described later. As the drain region 19 becomes deep silicide and becomes fully silicide, the drain region 19 serves as the gate electrode 16 together with the lower gate metal 14.

The capping silicon layer 15 has a thickness of 40 nm to 150 nm deposited, which is a deep source / drain implant process and a deep silicede for forming a source / drain region 19 which is a subsequent process. The process must be taken into account.

When the gate insulating layer 13, the gate metal 14, and the capping silicon layer 15 are sequentially formed on the semiconductor substrate 11, the device isolation layer 12 may be selectively patterned by performing a photolithography process and an etching process. A gate electrode 16 (shown in FIG. 1B) is formed on the semiconductor substrate 11 between. That is, a photoresist is coated on the entire surface of the semiconductor substrate 11 and then a photolithography process such as exposure and development is performed to form a photoresist pattern (not shown) defining the gate electrode 16. Using the photoresist pattern as a mask, the capping silicon layer 15, the gate metal 14, and the gate insulating layer 13 are sequentially etched by an etching process, and as shown in FIG. 1B, the semiconductor substrate 11 is etched. A gate electrode 16 made of the gate metal 14a and the capping silicon layer 15a is formed on the gate insulating film 13a.

As illustrated in FIG. 1C, when the gate electrode 16 is formed on the semiconductor substrate 11, lightly doped drain (LDD) regions 17 are formed on both sides of the gate electrode 16. To this end, low concentration impurity ions are implanted into the entire surface of the semiconductor substrate 11 using the gate electrode 16 as a mask to form the LDD region 17 in the surface of the semiconductor substrate 11 on both sides of the gate electrode 16. Then, an insulating film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 16 by using a silicon oxide film or a silicon nitride film, and an etch back process is performed on the entire surface of the insulating film to form the gate electrode 16. Gate spacers 18 are formed on both sides.

When the gate spacers 18 are formed, a source / drain impurity is implanted into the entire surface of the semiconductor substrate 11 using the gate spacers 18 and the gate electrodes 16 as masks to form semiconductors on both sides of the gate electrodes 16. A source / drain region 19 is formed in the surface of the substrate 11 to be connected to the LDD region 17.

As shown in FIG. 1D, when the source / drain regions 19 (shown in FIG. 1C) are formed on both sides of the gate electrode 16, the resistance of the source / drain regions 19 (shown in FIG. 1C) is reduced, and the semiconductor device is reduced. The capping silicon layer 15b in which the capping silicon layer 15a (shown in FIG. 1C) and the source / drain region 19 (shown in FIG. 1C) is silicided by performing a deep silicidation process to improve the performance of the ) And source / drain regions 19a. In this case, a metal for silicidation such as Co or Ni is deposited by sputtering on the entire surface of the semiconductor substrate 11 for the silicide process, and then, as well as the source / drain regions 19 (shown in FIG. 1C) through a heat treatment process. The capping silicon layer 15a is also allowed to be fully silicidated. At this time, the deposition thickness of the silicided metal deposited on the entire surface of the semiconductor substrate 11 is preferably 10 nm to 30 nm.

When the silicided capping silicon layer 15b and the source / drain regions 19a are formed, a wiring process of a general CMOSFET device is followed. In this case, Al, Cu, or the like is applied.

According to a preferred embodiment of the present invention as described above, the gate first metal gate (Gate First) applying the thin gate metal 14a to the gate electrode 16 and the capping silicon layer 15a on the gate metal 14a Metal Gate) process is applied. Therefore, it is possible to effectively reduce the damage (damage) and metal residue (metal residue) generated in the gate etching process, it is possible to apply the conventional manufacturing process of the CMOSFET (Complementary MOSFET) device.

In addition, in order to lower the resistance of the source / drain regions 19, a deep silicided source / drain region 19a is formed, and at this time, the capping silicon layer 15a is pulled silicided on the gate metal 14a (fully). silicidation). Therefore, it is possible to effectively lower the high resistance of the source / drain region which is a problem in the conventional semiconductor device, and to suppress the poly depletion phenomenon without significantly changing the manufacturing process of the conventional CMOSFET device.

Therefore, it can effectively be applied to high performance semiconductor devices requiring high speed by effectively overcoming the problems caused by the conventional metal gate application and lowering the resistance of the source / drain regions 19a. As a result, the semiconductor device may have higher performance than existing semiconductor devices.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a poly depletion phenomenon occurs in an application device of a conventional polysilicon gate by applying a thin metal gate and silicided polysilicon as a gate electrode. In addition, the performance of the semiconductor device may be improved by effectively reducing the EOT of the semiconductor device, and the resistance of the source / drain area may be effectively reduced by silicifying the source / drain regions, thereby further improving the performance of the semiconductor device. As a result, the present invention can be suitably applied to high performance semiconductor devices requiring high speed.

What has been described above is only one embodiment for carrying out the method of manufacturing a semiconductor device according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims of the present invention Without departing from the gist of the present invention, one of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

Claims (12)

delete delete delete delete delete In the manufacturing method of a semiconductor device, Forming a gate electrode comprising a gate metal and a capping silicon layer sequentially stacked on the gate insulating film on the semiconductor substrate; Forming LDD regions on semiconductor substrates on both sides of the gate electrode; Forming gate spacers on both sides of the gate electrode; Forming a source / drain region on the semiconductor substrate at both sides of the gate electrode, the source / drain region being connected to the LDD region; Fully silicideing the capping silicon layer and the source / drain regions, Forming the gate electrode to form the gate metal to a thickness of 5nm to 40nm, Forming the gate electrode is to form the capping silicon layer to a thickness of 40nm ~ 150nm Method for manufacturing a semiconductor device, characterized in that. The method of claim 6, Forming the gate electrode, Wherein the gate insulating film is made of any one of SixOy-based, HfxOy-based, AlxOy-based material or a compound thereof Method for manufacturing a semiconductor device, characterized in that. The method of claim 6, Forming the gate electrode, Wherein the gate metal is made of any one of TiN, TaN, HfN, LaN, Sc Method for manufacturing a semiconductor device, characterized in that. delete delete The method of claim 6, The silicidation step, The metal to be deposited for suicide is Ni or Co Method for manufacturing a semiconductor device, characterized in that. The method according to claim 6 or 11, wherein The silicidation step, The deposition thickness of the silicided metal deposited on the entire surface of the semiconductor substrate is 10 nm to 30 nm Method for manufacturing a semiconductor device, characterized in that.

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