TWI517220B - Semiconductor device formation - Google Patents

Description

Structure of semiconductor device

Embodiments of the invention relate to semiconductor devices, and more particularly to the fabrication of non-volatile semiconductor devices.

The traditional way of increasing the aspect ratio of the floating gate technology often leads to the creation of holes or large gaps in the gap filling process. This may reduce the yield of the floating gate technology and/or the performance of the floating gate device. At present, the techniques for solving these problems include re-adding hydrogen during annealing treatment, depositing polycrystalline germanium in a two-stage manner, forming a floating gate etching combined etching process, and using a hexafluoride mixed gas for chemical gas in forming a floating gate device. In the phase deposition process. These processes are not only complex but inefficient, and often fail to detect the above problems and create floating gates without holes and gaps. Therefore, it is necessary to develop a simple process to generate floating gates without holes and gaps.

The disclosure herein relates to a floating gate semiconductor structure having substantially no gaps and holes and a method of fabricating such a floating gate semiconductor structure having substantially no gaps and holes.

The method includes forming a trench in a semiconductor substrate. The trench is defined by a trench base portion and a sidewall adjacent to the shallow trench isolation structure. Wherein the side wall is gradually inclined, and wherein the distance between the upper half of the side wall is greater than the distance between the lower half of the side wall.

According to an embodiment of the invention, the cloth is formed at a first angle to form a cloth The planting area is adjacent to a first side wall of the shallow trench isolation structure. The shallow trench isolation structure, the trench, and the impurity may be annealed. Part or all of the planting area is removed. Forming a tunnel oxide layer over the trench base portion and the sidewall of the shallow trench isolation structure. A conductive film is formed over the tunnel oxide layer.

The polysilicon film can be patterned using a patterning process to form a floating gate.

According to another embodiment of the invention, the first angle of inclination is in the range of 0 to 30 degrees relative to the side wall of the shallow trench isolation structure.

According to another embodiment of the present invention, the first tilt angle is a range of 10 to 70 degrees with respect to the sidewall of the shallow trench isolation structure, rotating the semiconductor structure; and implanting impurities at a second angle to form a implant The region is adjacent to a second sidewall of the shallow trench isolation structure. According to design considerations, the first tilt angle is substantially the same as or different from the second tilt angle.

According to another embodiment of the invention, the implant and the tunnel cleaning result in a serrated structure being created in the upper half of the sidewall (or the sidewall adjacent the implanted region).

According to another embodiment of the present invention, there is still a residue in the planting area after the tunnel cleaning process.

According to another embodiment of the invention, the impurities implanted include nitrogen gas (N ₂ ), helium, carbon, and fluorine.

It is still another object of the present invention to provide a floating gate semiconductor structure comprising: a shallow trench isolation structure formed in a semiconductor substrate, thereby defining an active region trench of the semiconductor structure. The trench includes an opening defined by a trench base portion and a sidewall adjacent the shallow trench isolation structure. Wherein the side wall is gradually inclined, and wherein the distance between the upper half of the side wall is greater than the distance between the lower half of the side wall.

According to an embodiment of the invention, the serrated structure is defined in the upper half of the side wall.

According to another embodiment of the present invention, the residual implanted area may be defined adjacent to Near the upper half of the side wall of the shallow trench isolation structure.

Please refer to Figures 1A and 1B, which show the relationship between the loss of wet cleaning oxide and the fluorine implant dose, respectively, and the relationship between the loss of wet cleaning oxide and the boron implant dose. Graph 100 shows the relationship between oxide loss and fluorine implant dose in the presence of annealing 102 and without annealing 104. Graph 150 shows the relationship between oxide loss and boron implant dose. When the implant dose exceeds 1E13 cm ^-2 , the etch rate of the thermal oxide increases as the implant dose of fluorine or boron increases. Therefore, this annealing process can reduce the etch rate, and the dose and anneal process can be used to adjust the appropriate amount of loss in the high-density plasma (HDP) shallow trench isolation region.

Figures 2A-2D show a comparison of standard floating gate devices 200, 201 without the implantation process of the present invention with floating gate devices 250, 251 using the fluorine implant process of the present invention. The 2B and 2D views show enlarged views of the areas 201 and 251. For example, the fluorine implantation process is carried out using a two-stage rotary process with an energy of about 15 keV, a dose of 1.5E15 cm ^-2 , a planting angle of 55°, and then a 90° rotation. The floating gate devices 250, 251 are substantially free of gaps and holes, while the standard floating gate devices 200, 201 include holes 202.

This fluorine implant process uses a 55 nm node technology of the anti-gate (NOR) flash memory to create a floating gate structure with substantially no gaps and holes.

Figure 3 is a flow diagram of a process 300 for forming a floating gate device having substantially no gaps and holes. In step 302, a shallow trench isolation (STI) structure is formed in a semiconductor substrate to define an active region trench of the semiconductor device.

At step 304, impurities are implanted into the sidewalls of the shallow trench isolation (STI) structure. These impurities use a number of different tilt angles to tilt the ions The sidewalls of this shallow trench isolation (STI) structure are implanted.

For example, in some embodiments, the impurities are implanted into the first sidewall of the shallow trench isolation (STI) structure using a first angle and the second shallow trench isolation (STI) structure is implanted using the second angle a sidewall adjacent the first sidewall. The first angle and the second angle are preferably substantially the same, but may be different depending on design considerations. The implantation of the first angle and the second angle may be performed substantially simultaneously, but may also be performed using a two-stage or multi-stage planting method. In the case of a two-stage or multi-stage planting mode, the device can be rotated during the implantation phase so that the same ion gun can be used to implant different sidewall regions. This device can be rotated one, two or more times depending on design considerations. In other embodiments, the impurities are implanted using a substantially 0° (or vertical). These different arrangements will be described in more detail below in conjunction with Figure 7.

These (in step 304) implanted impurities may include, but are not limited to, nitrogen gas (N ₂ ), helium, carbon, and fluorine. In an embodiment, the first angle of inclination is 55°. In some embodiments, the first angle of inclination is in the range of 10 to 70 degrees.

Thereafter, in step 304, certain embodiments may employ different implant energies and dose ranges depending on the angle of incidence of the implanted impurities. For example, in embodiments where the impurity is implanted using a substantially 0 (or vertical) implant, the implant energy range can be between 1 keV and 20 keV and the dose range is between 1E12 cm" ² and 1E14 cm" ² . Approximately 0° (or vertical) implant angle may include an angle of inclination from 0 to 30°. In another embodiment, the inclination angle is in the range of 10 ~ 70 °, the implant energy may be between the range 1keV to 100keV and a dose is in the range of 1E12cm ^-2 to 1E16cm ^-2.

At step 306, the shallow trench isolation (STI) structure and the trench are annealed. Annealing of the shallow trench isolation (STI) structure includes activating impurities in a memory cell critical voltage implant region. In general, this annealing step can repair areas of the semiconductor structure that are damaged during implantation.

In some embodiments, the shallow trench isolation (STI) structure and trenches of step 306 are annealed prior to implanting impurities into the sidewalls of the shallow trench isolation (STI) structure (step 304). In other embodiments, the shallow trench isolation (STI) structure and trenches of step 306 are annealed after implanting impurities into the sidewalls of the shallow trench isolation (STI) structure (step 304).

At step 308, a tunnel cleaning step is performed in the shallow trench isolation (STI) structure and the trench region. This tunnel cleaning step can include an increase in the etch rate of the sidewall regions having impurities implanted into the shallow trench isolation (STI) structure. At step 310, a tunnel oxide layer is formed over the sidewalls and trenches of the shallow trench isolation (STI) structure. At step 312, a floating gate is formed. Step 312 can include forming a polysilicon film over the tunnel oxide layer and then patterning the polysilicon film into a floating gate using a patterning process.

4A~4C, 5A~5C, 6A~6C and 7A~7C are schematic cross-sectional views showing different stages in the process steps of the floating gate device disclosed herein. Figures 4A~4C, 5A~5C, 6A~6C, and 7A~7C also show schematic diagrams of different aspect ratios in this floating gate structure. For example, the regions 412, 422, 432, and 452 in the 4A, 5A, 6A, and 7A diagrams respectively show an aspect ratio of about 1, and the regions 414, 424, 434 in the 4B, 5B, 6B, and 7B diagrams. And 454 respectively show an aspect ratio of about 1.5, while the regions 416, 426, 436, and 456 in the 4C, 5C, 6C, and 7C diagrams respectively show an aspect ratio of about 2.

Referring first to Figures 4A-4C, a substrate 402 is provided and then etched using conventional lithography and etching techniques to produce a patterned substrate 402. In an embodiment, the substrate 402 is germanium. An oxide layer 404 is formed over the germanium substrate 402. The device is chemically mechanically ground to produce a shallow trench isolation (STI) structure 404 and a trench 406. Thus, a shallow trench isolation (STI) structure 404 is formed over the semiconductor substrate 402, defining an active region 406 of the device (eg, step 302 in FIG. 3).

Figures 4A-4C also show the implantation of impurities into the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 (e.g., step 304 in Figure 3). In one embodiment, the impurities are implanted in a manner relative to the first slope angle 401 of the first sidewall 403 of the shallow trench isolation (STI) structure 404 to form a implant region on the first sidewall 411. Also implanting may also include implanting in a second oblique angle 407 relative to the second sidewall 405 of the shallow trench isolation (STI) structure 404 to form a implanted region on the second sidewall 410. These implants entering the first and second sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 constitute the implant region 409 and may be implanted simultaneously or sequentially. The first and second implant angles 401 and 407 can be substantially the same or different.

Additionally, the step of implanting into the first and second sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 can be performed using a two-stage or multi-stage (not shown) implant. For example, the first sidewall 403 of the shallow trench isolation (STI) structure can be implanted using the first angle 401, and then the device is rotated 180°, and then the same ion gun is used to implant the shallow trench isolation ( The second sidewall 405 of the STI) structure (substantially implanted at the same angle relative to the first angle 401 of the first sidewall 403 after being rotated 180°). Or in other embodiments, the first sidewall 403 of the shallow trench isolation (STI) structure can be implanted using the first angle 401, and then the device can be rotated by 90°, and then impurities are implanted into the shallow trench isolation. The other side wall of the (STI) structure (substantially implanted at the same angle relative to the first angle 401 of the first side wall 403 after being rotated 180°), then the device is rotated 90° again, and then the same ions are used The gun implants impurities into the other side wall of the shallow trench isolation (STI) structure (substantially implanted at the same angle relative to the first angle 401 of the first sidewall 403 after being rotated 180°), and the like. Therefore, the number of implants and the number of rotations of the implanted side walls are both elastic according to the size, shape and depth of the implanted region 409.

In certain embodiments, these implanted impurities may include, but are not limited to, nitrogen gas (N ₂ ), helium, carbon, and fluorine. Moreover, in an embodiment, the ion implantation is performed in an implanted manner at an oblique angle (e.g., 401 and 407). As previously described in FIG. 3, in an embodiment, the tilt angle may be 55°. In some embodiments, the angle of inclination is in the range of 10 to 70 degrees. In addition, some embodiments may employ different implant energies and dose ranges depending on the angle of incidence of the implanted impurities, the implant energy range being between 1 keV and 100 keV, and the dose range being 1E12 cm ^-2 to 1E16 cm. ^-2 . This dose can be determined based on the loss of high density plasma oxide shallow trench isolation.

The 5A-5C diagram shows another embodiment of implanting impurities into the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 (e.g., step 304 in FIG. 3). In one embodiment, the impurity is at an angle of 0° relative to the first sidewall 403 of the shallow trench isolation (STI) structure 404, substantially opposite the first and second sidewalls 403, 405 of the shallow trench isolation (STI) structure 404. 421 (or vertical) implant. In one embodiment, the impurities are implanted in a manner that is substantially at an angle of inclination 421 of 0° with respect to the first sidewall 403 of the shallow trench isolation (STI) structure 404 to form a implanted region on the first sidewall 411. In one embodiment, the impurities are implanted in a manner that is at an oblique angle 421 of substantially 0° relative to the second sidewall 405 of the shallow trench isolation (STI) structure 404 to form a implanted region in the second sidewall 410. These impurities may also be implanted on the surface of the ruthenium substrate 402 at a tilt angle 421 of approximately 0° to form a implanted region on the surface of the substrate 408. These implants entering the first and second sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 constitute the implant region 409 and may be implanted simultaneously or sequentially.

Likewise, in certain embodiments, these implanted impurities can include, but are not limited to, nitrogen gas (N ₂ ), helium, carbon, and fluorine. As previously described in FIG. 3, in an embodiment, the tilt angle may be 0°. In some embodiments, the angle of inclination is in the range of 0 to 30 degrees. In addition, some embodiments may employ different implant energies and dose ranges depending on the angle of incidence of the implanted impurities, the implant energy range being between 1 keV and 20 keV, and the dose range being 1E12 cm ^-2 to 1E14 cm. ^-2 . This dose can be determined based on the loss of high density plasma oxide shallow trench isolation.

Figures 6A-6C show the outline of the apparatus of the above embodiments after tunnel cleaning and tunnel oxide formation. After the tunnel is cleaned, the implanted areas (409 in Figures 4A-4C and 5A-5C) have a higher etch rate relative to the unimplanted areas. In other words, the implanted area will be etched faster than the area without any impurity implants. Figures 6A-6C show the outline after the etching is completed. The upper portions 442, 444, 446 of the shallow trench isolation (STI) structure 404 sidewalls 403, 405 have more high density plasma (HDCVD) oxide than the lower portions 443, 445, 447 of the sidewalls 403, 405. The loss results in a wide, narrow, V-shaped profile of the shallow trench isolation (STI) trench 406. In other words, the side wall 405 is gradually contracted, resulting in an active area trench having an upper wide and a lower narrow V-shaped profile. Thus, the distance D1 between the upper portions 442, 444, 446 of the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404 will be greater than the distance D2 between the lower portions 443, 445, 447 of the sidewalls 403, 405.

As a result of the implant and tunnel cleaning process, a rougher (or small zigzag wrinkle) surface 449 is formed over the upper portions 442, 444, 446 of the shallow trench isolation (STI) structure 404 sidewalls 403, 405. For purposes of illustration, FIGS. 6A-6C show only a portion of the small zigzag wrinkles 449, but these small zigzag wrinkles may exist over the upper portions 442, 444 of the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404. 446 (for example, the portions of the 4A to 4C and 5A to 5C maps near the planting region 409). Thus, the upper portions 442, 444, 446 of the sidewalls 403, 405 are rougher than the lower portions 443, 445, 447 of the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404.

In some embodiments, the implanted area (eg, 4A~4C and 5A~5C) 409) will not be completely removed during the tunnel cleaning process. Therefore, there may be residual planting areas 419. In one embodiment, the tunnel cleaning process removes almost all of the implanted areas (e.g., 409 in Figures 4A-4C and 5A-5C).

In short, the most severely damaged area of the implant process is the upper portion 442, 444, 446 of the sidewalls 403, 405 of the shallow trench isolation (STI) structure 404, which may allow for high density plasma oxidation above. The loss of material is more lost than the upper high density plasma oxide and it can result in a small zigzag structure at the upper portions 442, 444, 446 along the sidewalls 403, 405. This results in a floating gate structure that is substantially free of gaps and holes because subsequent layers, such as tunnel oxide layers or polysilicon, can more easily and smoothly fill the V-shaped trenches 406 due to the wide and narrow profile on the trench. Inside.

Figures 7A-7C show the floating gate devices 452, 454, 456 with substantially no gaps and holes. A tunnel oxide layer 408 is formed over the substrate 402, and a polysilicon layer 418 is formed over the tunnel oxide layer 408 to create floating gate devices 452, 454, 456 that are substantially free of gaps and holes.

Although the invention uses floating gate memory as an embodiment, the process disclosed herein can be applied to various memories, such as floating gates and memories, charge trapping memories, non-volatile memories, or embedded memories.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

200, 201‧‧‧ standard floating gate device

250,251‧‧‧Floating gate device of the fluorine cloth planting process of the invention

202‧‧‧ hole

402‧‧‧Substrate

403, 405‧‧‧ side wall

404‧‧‧Shallow trench isolation (STI) structure

406‧‧‧ Ditch

408‧‧‧ Tunnel Oxidation Layer

409‧‧‧planting area

410‧‧‧ second side wall

411‧‧‧First side wall

418‧‧‧Polysilicon layer

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figures 1A and 1B are graphs showing the relationship between the loss of wet cleaning oxide and the amount of fluorine implant, and the relationship between the loss of wet cleaning oxide and the boron implant dose, respectively.

Figures 2A-2D show a comparison of a standard floating gate device without the implantation process of the present invention and a floating gate device using the fluorine cloth implant process of the present invention.

FIG. 3 is a flow chart showing the process of forming a floating gate device having substantially no gaps and holes according to an exemplary embodiment of the present invention.

Figures 4A, 4B, and 4C are schematic cross-sectional views showing different stages in the process steps disclosed herein.

Figures 5A, 5B, and 5C are schematic cross-sectional views showing different stages in the process steps disclosed herein.

Figures 6A, 6B, and 6C are schematic cross-sectional views showing different stages in the process steps disclosed herein.

Figures 7A, 7B, and 7C are schematic cross-sectional views showing different stages in the process steps of the floating gate device disclosed herein.

Claims (23)

A method of fabricating a floating gate semiconductor structure, comprising: forming a trench in a semiconductor substrate, the trench being defined by a trench base portion and a sidewall adjacent to the shallow trench isolation structure; and forming a trench region to be isolated from the adjacent shallow trench One or both side walls of the structure, wherein the side walls are progressively inclined, and wherein the distance between the upper halves of the side walls is greater than the distance between the lower half of the side walls. The method of claim 1, further comprising forming a V-shaped profile opening in the trench. The method of claim 1, further comprising: annealing the shallow trench isolation structure, the trench and the implanted region; removing a portion of the implanted region; forming a tunnel oxide layer on the base portion of the trench and Overlying the sidewall of the shallow trench isolation structure; forming a conductive film over the tunnel oxide layer. The method of claim 3, wherein forming the implanted region comprises implanting the implant at a first oblique angle to form a first sidewall of the implanted region adjacent the shallow trench isolation structure. The method of claim 4, wherein the first angle of inclination is in the range of 0 to 30 degrees relative to the side wall of the shallow trench isolation structure. The method of claim 4, wherein forming the planting area further comprises Impurities are implanted at a second angle of inclination to form a second sidewall of the adjacent shallow trench isolation structure. The method of claim 3, wherein the implanting further comprises forming another implanted region in the trench partition base portion. The method of claim 4, wherein the first angle of inclination is substantially 0° with respect to the side wall of the shallow trench isolation structure. The method of claim 4, further comprising: rotating the semiconductor structure; and wherein forming the implanted region further comprises implanting the impurity at a second angle to form the implanted region in the adjacent shallow trench isolation structure Second side wall. The method of claim 9, wherein the first tilt angle is substantially the same as the second tilt angle. The method of claim 9, wherein the first and the second angle of inclination are in the range of 10 to 70 degrees with respect to the side wall of the shallow trench isolation structure. The method of claim 9, wherein the first and second angles of inclination are substantially 55° with respect to the side wall of the shallow trench isolation structure. The method of claim 3, wherein the implanting and the removing result in a serrated structure being produced in the upper half of the sidewall. The method of claim 13, wherein the upper half of the side wall includes the side wall portion adjacent to the planting area. The method of claim 3, wherein the planting area remains after the removal process. The method of claim 4, wherein the impurities implanted include nitrogen gas (N ₂ ), helium, carbon, and fluorine. A semiconductor structure comprising: a shallow trench isolation structure formed in a semiconductor substrate, thereby defining a trench of the semiconductor structure; and wherein the trench comprises an opening defined by a trench base portion and a sidewall of the adjacent shallow trench isolation structure Wherein the side wall is progressively inclined, and the distance between the upper halves of the side wall is greater than the distance between the lower half of the side wall, and the upper half of the side wall includes the implanted area. The semiconductor structure of claim 17, wherein the sawtooth structure is defined in an upper half of the sidewall. The semiconductor structure of claim 17 further comprising a residual implant region defined by a shallow trench isolation region adjacent the upper half of the sidewall. The semiconductor structure according to claim 19, wherein the impurity implanted in the residual implant region comprises one of nitrogen gas (N ₂ ), helium, carbon and fluorine. The application of the semiconductor structure of patentable scope of item 19, wherein the remaining region comprises implanting the implant dose range between implant 1E12cm ^-2 to 1E16cm ^-2. The semiconductor structure of claim 17 wherein the upper half of the sidewall comprises the sidewall portion adjacent the implant region. The semiconductor structure of claim 17, further comprising a planting region on the upper half of the sidewall and the trench base portion.