TWI517134B - Scan circuit and shift register - Google Patents

Description

Scanning circuit and shift register

This invention relates to an electronic circuit. In particular, a scanning circuit and a shift register.

With the rapid development of electronic technology, display panels have been widely used in people's lives, such as mobile phones or computers.

In general, the display panel may include a scanning circuit, a data circuit, and a plurality of pixels arranged in a matrix. The scanning circuit can include a shift register in which the plurality of stages are electrically connected in series with each other. The scan circuit can sequentially generate a plurality of scan signals through the shift register, and provide the scan signals to the scan lines in the pixel array to turn on the pixels column by column. The data circuit can generate a plurality of data signals at the same time, and provide the data signals to the opened pixels, so that the opened pixels update their display state (for example, gray scale). In this way, the image can be updated and displayed on the display panel.

A typical scan circuit provides a reset signal to the last stage shift register to reset the last stage shift register. However, the transmission path of the reset signal is usually short, so that electrostatic discharge is likely to occur, which causes damage to the display panel.

Therefore, how to solve this problem is an important research direction in the field.

One aspect of the present invention is to provide a scanning circuit. According to an embodiment of the invention, the scanning circuit includes a plurality of shift registers. The shift registers are electrically connected in series with each other. At least one of the shift registers includes an input circuit, an output circuit, a disable circuit, a first reset circuit, and a second reset circuit. The input circuit is configured to receive an input voltage at the input and provide an input voltage to the first node. The output circuit is configured to receive the first clock signal and provide an output voltage to the output according to the first clock signal and the potential of the first node. The de-energizing circuit is configured to provide a supply voltage to the output according to the second clock signal. The first reset circuit is configured to provide a supply voltage to the first node according to a reset voltage of the second node. The second reset circuit is configured to selectively provide the reset voltage and the supply voltage to the second node according to the output voltage of the output terminal, the second clock signal, and the potential of the first node.

One aspect of the present invention is to provide a shift register. According to an embodiment of the invention, the shift register includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth A transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a capacitor. The first transistor includes a first end, a second end, and a control end. The first end of the first transistor and the control end of the first transistor are electrically connected to the input end, and the second end of the first transistor is electrically connected to the first node. The second transistor includes a first end, a second end, and a control end, wherein the The first end of the second transistor is configured to receive the first clock signal, the second end of the second transistor is electrically connected to the output end, and the control end of the second transistor is electrically connected to the first node. The third transistor includes a first end, a second end, and a control end, wherein the first end of the third transistor is electrically connected to the first node, the second end of the third transistor is configured to receive the supply voltage, and the third The control end of the crystal is electrically connected to the second node. The fourth transistor includes a first end, a second end, and a control end, wherein the first end of the fourth transistor and the control end of the fourth transistor are electrically connected to the output end, and the second end of the fourth transistor is electrically Connect to the third node. The fifth transistor includes a first end, a second end, and a control end, wherein the first end of the fifth transistor is configured to receive the second clock signal, and the second end of the fifth transistor is electrically connected to the second node, and The control end of the fifth transistor is electrically connected to the third node. The sixth transistor includes a first end, a second end, and a control end, wherein the first end of the sixth transistor is electrically connected to the third node, the second end of the sixth transistor is configured to receive the supply voltage, and the sixth The control end of the crystal is electrically connected to the fourth node. The seventh transistor includes a first end, a second end, and a control end, wherein the first end of the seventh transistor is electrically connected to the second node, the second end of the seventh transistor is configured to receive the supply voltage, and the seventh The control end of the crystal is electrically connected to the first node. The eighth transistor includes a first end, a second end, and a control end, wherein the first end of the eighth transistor is electrically connected to the fourth node, the second end of the eighth transistor is configured to receive the supply voltage, and the eighth The control end of the transistor is electrically connected to the first node. The ninth transistor includes a first end, a second end, and a control end, wherein the first end of the ninth transistor is electrically connected to the first node, the second end of the ninth transistor is used to receive the supply voltage, and the ninth The control end of the transistor is electrically connected to the fourth node. Tenth transistor, including the first a first end, a second end, and a control end, wherein the first end of the tenth transistor is electrically connected to the output end, the second end of the tenth transistor is used to receive the supply voltage, and the control end of the tenth transistor is electrically connected Four nodes. The eleventh transistor includes a first end, a second end, and a control end, wherein the first end of the eleventh transistor is electrically connected to the output end, and the second end of the eleventh transistor is configured to receive the supply voltage, and The control end of the eleventh transistor is configured to receive the second clock signal. The capacitor includes a first end and a second end. The first end of the capacitor is configured to receive the second clock signal, and the second end of the capacitor is electrically connected to the fourth node.

By applying the above embodiment, a shift register having an automatic reset function can be realized. By applying this shift register, the last stage shift register in the scan circuit can be automatically reset without receiving an external reset signal. In this way, the scanning circuit does not need to provide an additional reset signal to the last stage of the shift register, thereby avoiding electrostatic discharge.

100‧‧‧ display panel

102‧‧‧data circuit

104‧‧‧ pixel array

106‧‧‧ pixels

110‧‧‧Scan circuit

110a‧‧‧Scan circuit

SR1-SRN‧‧‧Shift register

SR1a-SRNa‧‧‧Shift register

A‧‧‧ node

B‧‧‧ node

BT‧‧‧ node

RST‧‧‧ node

G(1)-G(N)‧‧‧ scan signal

D(1)-D(M)‧‧‧Information Signal

IN‧‧‧ input

OUT‧‧‧ output

112‧‧‧Input circuit

114‧‧‧Output circuit

116‧‧‧Disable circuit

118‧‧‧First reset circuit

120‧‧‧Second reset circuit

T1-T11‧‧‧O crystal

C1‧‧‧ capacitor

Cgs‧‧‧ capacitor

CK‧‧‧ clock signal

XCK‧‧‧ clock signal

CK1‧‧‧ clock signal

CK2‧‧‧ clock signal

VSS‧‧‧ supply voltage

During the period of D1-D6‧‧

STP‧‧‧ signal

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. 2 is a schematic diagram of a scanning circuit according to an embodiment of the invention; FIG. 3A is a schematic diagram of a shift register according to an embodiment of the invention; FIG. 3B is a schematic diagram of a shift register according to an embodiment of the invention; FIG. 4 is a schematic diagram of a shift register according to an embodiment of the invention; A signal diagram of a shift register according to an embodiment of the invention; and FIG. 6 is a schematic diagram of a scan circuit according to another embodiment of the invention.

The spirit and scope of the present disclosure will be apparent from the following description of the preferred embodiments of the present disclosure. Modifications do not depart from the spirit and scope of the disclosure.

The use of the terms "first", "second", etc., and the like, as used herein, are not intended to limit the present invention, and are not intended to limit the invention.

"Electrical connection" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "electrical connection" may also mean two or A plurality of component elements operate or operate with each other.

The terms used in this document, unless otherwise specified, generally have the usual meaning of each term used in the art, in the context of the disclosure, and in the particular content. Certain terms used to describe the disclosure Additional guidance will be provided below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the present disclosure.

FIG. 1 is a schematic diagram of a display panel 100 according to an embodiment of the invention. The display panel 100 can include a scanning circuit 110, a data circuit 102, and a pixel array 104. The pixel array 104 can include a plurality of pixels 106 arranged in a matrix. The scanning circuit 110 can sequentially generate and provide a plurality of scanning signals G(1), . . . , G(N) to the pixels 106 in the pixel array 104 to sequentially open the pixels 106 in sequence, where N is a natural number. . The data circuit 102 can simultaneously generate a plurality of data signals D(1), ..., D(M), and provide the data signals D(1), ..., D(M) to the opened pixels 106 to enable the opening. The pixel 106 updates its display state (eg, color and grayscale), where M is a natural number. In this way, the image can be updated and displayed on the display panel 100.

FIG. 2 is a schematic diagram of a scanning circuit 110 according to an embodiment of the invention. In this embodiment, the scanning circuit 110 may include a shift register SR1, . . . , SRN in which a plurality of stages are electrically connected in series, for example, the shift register SR1 is electrically connected to the shift register SR2, and the shift is temporarily suspended. The register SR2 is electrically connected to the shift register SR3, and so on. The shift registers SR1, . . . , SRN are respectively used to generate an output voltage (for example, a scan signal having a high voltage level) as the scan signal G(1), . . . , G according to the start signal and the clock signals CK and XCK. (N). For example, in this embodiment, the shift register SR1 can receive the signal STP as a start signal, and generate the scan signal G(1) according to the signal STP and the clock signals CK, XCK. The shift register SRn can receive the scan signal G(n-1) outputted by the shift register (ie, the shift register SR(n-1)) of the previous stage as the start signal, and according to the scan signal G (n-1) and The clock signals CK and XCK generate a scanning signal G(n).

In addition, in this embodiment, the shift registers SR1, . . . , SR(N-1) respectively receive the scan signals output by the next stage shift register as reset signals, and reset according to the reset signals. . For example, the shift register SR1 receives the scan signal G(2) as a reset signal, and according to the reset, the shift register SR(N-1) receives the scan generated by the shift register SRN. The signal G(N) is used as a reset signal and is reset accordingly.

In this embodiment, the shift register SRN is the last stage shift register, so it automatically resets without receiving the scan signal output by the next stage shift register. Specific details regarding the shift registers SR1, ..., SRN will be detailed in the following paragraphs.

In this embodiment, the scan circuit 110 can provide, for example, the clock signal CK1 to the odd-numbered shift register SR1, SR3, . . . , as the clock signal CK of the odd-numbered shift registers SR1, SR3, . And the clock signal CK2 to the odd-numbered shift register SR1, SR3, ... are provided as the clock signal XCK of the odd-numbered shift registers SR1, SR3, . At the same time, the scan circuit 110 can provide the clock signal CK1 to the even-numbered shift register SR2, SR4, ... as the clock signal XCK of the even-numbered shift registers SR2, SR4, ..., and provide the clock signal The CK2 to even-stage shift registers SR2, SR4, ... are used as the clock signals CK of the even-numbered shift registers SR2, SR4, .

In an embodiment, the periods of the clock signals CK1, CK2 are identical to each other and the phases are opposite to each other.

When noting, the shift register SRn shown in FIG. 2 is for example The shift register SRN is, for example, an even-numbered shift register, but the present invention is not limited by this illustrative example.

In addition, it should be noted that the clock signal CK1 can also be used as the clock signal of the odd-numbered shift register SR1, SR3, ... and the clock signals of the even-numbered shift registers SR2, SR4, . CK, and the clock signal CK2 can also be used as the clock signal CK of the odd-numbered shift registers SR1, SR3, ... and the clock signal XCK of the even-numbered shift registers SR2, SR4, . The present invention is not limited to the above embodiments.

FIG. 3A is a schematic diagram of a shift register SRN with an automatic reset function according to an embodiment of the invention. In the present embodiment, the shift register SRN includes an input circuit 112, an output circuit 114, a disable circuit 116, a first reset circuit 118, and a second reset circuit 120.

In this embodiment, the input circuit 112 is electrically connected between the input terminal IN and the node BT. The output circuit 114 is electrically connected between the node BT and the output terminal OUT. The de-energizing circuit 116 is electrically connected between the node BT, the output terminal OUT and the voltage source of the supply voltage VSS. The first reset circuit 118 is electrically connected between the node BT, the node RST, and the voltage source of the supply voltage VSS. The second reset circuit 120 is electrically connected between the output terminal OUT, the node RST, and the voltage source of the supply voltage VSS.

In this embodiment, the input circuit 112 is configured to receive an input voltage from the input terminal IN (ie, the scan signal G(N-1)), and provide the input voltage to the node BT to charge the node BT to a specific one. The enabling potential (for example, the voltage level of the scanning signal G(N-1)). The output circuit 114 is configured to receive the clock signal CK and to use the potential of the clock signal CK and the node BT. An output voltage is supplied to the output terminal OUT to output a scan signal G(N) having a high voltage level. The de-energizing circuit 116 is configured to supply a supply voltage VSS (eg, having a low voltage level) to the output terminal OUT according to the clock signal XCK to clear (stop outputting) the charge of the scan signal G(N). The second reset circuit 120 is configured to selectively supply the reset voltage and the supply voltage VSS to the node RST according to the output voltage of the output terminal OUT, the clock signal XCK, the potential of the node BT and the node B. The first reset circuit 118 is configured to receive the reset voltage and the supply voltage VSS from the node RST, and supply the supply voltage VSS to the node BT according to the reset voltage on the node RST to discharge the node BT to a specific de-energization potential. And the reset operation of the shift register SRN is completed.

In this way, the shift register SRN with automatic reset function can be completed.

On the other hand, FIG. 3B is a schematic diagram of the shift register SRn according to an embodiment of the invention. It should be noted that since each shift register SR1, ..., SR(N-1) has the same or similar structure and operation as the shift register SRn, only the shift register SRn is used here. Illustrative. In addition, in this embodiment, the structure and operation of each shift register SR1, . . . , SR(N-1) are substantially the same as or similar to the shift register SRN, and the difference is only in all shift temporary storage. None of the devices SR1, ..., SR(N-1) has the second reset circuit 120, and the node RST of each shift register SR1, ..., SR(N-1) is connected to the next stage shift The output terminal OUT of the register (that is, the reset voltage on the node RST is the scan signal outputted by the previous stage shift register), instead of being connected to the second reset circuit 120. Therefore, the details of the shift registers SR1, . . . , SR(N-1) can be referred to the shift register SRN. I will not go into details here.

4 is a circuit diagram of an input circuit 112, an output circuit 114, a disabling circuit 116, a first reset circuit 118, and a second reset circuit 120 in the shift register SRN according to an embodiment of the invention. The description is as follows.

In the present embodiment, the input circuit 112 includes a transistor T6. The first end and the control end of the transistor T6 are electrically connected to the input terminal IN, and the second end of the transistor T6 is electrically connected to the node BT. In this way, during the period when the input terminal IN receives the input voltage (for example, the scan signal G(N-1) having the high voltage level), the transistor T6 can be turned on and provide the input voltage to the node BT, so that The node BT is charged to a specific enable potential (e.g., equal to the high voltage level of the scan signal G(N-1)).

In the present embodiment, the output circuit 114 includes a transistor T7 and a capacitor Cgs. The first end of the transistor T7 is configured to receive the clock signal CK, the second end of the transistor T7 is electrically connected to the output terminal OUT, and the control end of the transistor T7 is electrically connected to the node BT. One end of the capacitor Cgs is electrically connected to the control end of the transistor T7, and the other end is electrically connected to the second end of the transistor T7. In an embodiment, the capacitance Cgs may also be the parasitic capacitance of the transistor T7. In this way, when the node BT has an enable potential (for example, a high voltage level equal to the scan signal G(N-1)), when the pulse signal CK is switched from the low voltage level to the high voltage level, the node BT The potential can be coupled to a higher operating potential to continuously turn on the transistor T7 to provide a clock signal CK having a high voltage level to the output terminal OUT as an output voltage (ie, the scanning signal G(N) ).

In the present embodiment, the de-energizing circuit 116 includes transistors T8, T9, T10, T11 and a capacitor C1.

The first end of the transistor T8 is electrically connected to the node B, the second end of the transistor T8 is used to receive the supply voltage VSS, and the control end of the transistor T8 is electrically connected to the node BT. The transistor T8 is configured to supply the supply voltage VSS to the node B according to the potential of the node BT.

The first end of the transistor T9 is electrically connected to the node BT, the second end of the transistor T9 is used to receive the supply voltage VSS, and the control end of the transistor T9 is electrically connected to the node B. The transistor T9 is configured to supply the supply voltage VSS to the node BT according to the potential of the node B.

The first end of the transistor T10 is electrically connected to the output terminal OUT, and the second end of the transistor T10 is used to receive the control terminal of the supply voltage VSS transistor T10. The transistor T10 is configured to supply the supply voltage VSS to the output terminal OUT according to the potential of the node B.

The first end of the transistor T11 is electrically connected to the output terminal OUT, the second end of the transistor T11 is used to receive the supply voltage VSS, and the control end of the transistor T11 is used to receive the clock signal XCK. The transistor T11 is configured to supply the supply voltage VSS to the output terminal OUT according to the clock signal XCK.

One end of the capacitor C1 is used to receive the clock signal CK, and the other end is electrically connected to the node B. The capacitor C1 is used to transmit the clock signal CK to the node B.

Through the above arrangement, during a period in which the node BT has an enable potential (such as a high voltage level having the scan signal G(N-1)), the transistor T8 is turned on to supply the supply voltage VSS to the node B. In this way, the transistor T10 can be prevented from supplying the supply voltage VSS to the output terminal OUT.

In addition, in the case that the clock signal XCK has a high voltage level, the transistor T11 can be turned on to supply the supply voltage VSS to the output terminal OUT to clear the output voltage of the output terminal OUT having a high voltage level (ie, the scanning signal G). (N)).

Furthermore, after the node BT is discharged to a specific potential, the transistor T8 no longer supplies the supply voltage VSS to the node B, and the potential of the node B changes at any time, so that the transistor T9 is based on the clock signal CK. The supply voltage VSS is supplied to the node BT to stabilize the potential of the node BT, and the transistor T10 is supplied with the supply voltage VSS to the output terminal OUT according to the clock signal CK to stabilize the potential of the output terminal OUT.

In the present embodiment, the second reset circuit 120 includes transistors T2, T3, T4, and T5.

The first end of the transistor T2 and the control end are electrically connected to the output end OUT, and the second end of the transistor T2 is electrically connected to the node A. The transistor T2 is used to provide an output voltage (ie, a scan signal G(N) having a high voltage level) to the node A.

The first end of the transistor T3 is configured to receive the clock signal XCK, the second end of the transistor T3 is electrically connected to the node RST, and the control end of the transistor T3 is electrically connected to the node A. The transistor T3 is configured to provide a reset voltage to the node RST according to the potential of the node A and the clock signal XCK.

The first end of the transistor T4 is electrically connected to the node A, the second end of the transistor T4 is used to receive the supply voltage VSS, and the control end of the transistor T4 is electrically connected to the node B. The transistor T4 is configured to supply the supply voltage VSS to the node A according to the potential of the node B.

The first end of the transistor T5 is electrically connected to the node RST, the second end of the transistor T5 is used to receive the supply voltage VSS, and the control end of the transistor T5 is electrically connected to the node BT. The transistor T5 is configured to supply the supply voltage VSS to the node RST according to the potential of the node BT.

Through the above arrangement, during a period in which the node BT has an enable potential (such as a high voltage level having the scan signal G(N-1)), the transistor T5 is turned on to supply the supply voltage VSS to the node RST.

In addition, during the period in which the output terminal OUT receives the output voltage (ie, the high voltage level scan signal G(N)), the transistor T2 is turned on to provide an output voltage to the node A. While the node A has an output voltage, when the pulse signal XCK is switched from the low voltage level to the high voltage level, the potential of the node A can be coupled to a higher operating potential to continuously turn on the transistor T3. The clock signal XCK having a high voltage level is supplied to the node RST as a reset voltage.

Moreover, during the period when the node B receives the clock signal CK of the high voltage level, the transistor T4 is turned on to supply the supply voltage VSS to the node A to clear the output voltage on the node A.

In the present embodiment, the first reset circuit includes a transistor T1. The first end of the transistor T1 is electrically connected to the node BT, the second end of the transistor T1 receives the supply voltage VSS, and the control end of the transistor T1 is electrically connected to the node RST. The transistor T1 is configured to supply the supply voltage VSS to the node BT according to the reset voltage on the node RST. With such a setting, in the case where the node RST receives the reset voltage (such as the clock signal XCK having the high voltage level), the transistor T1 is turned on to supply the supply voltage VSS to the node BT. The node BT is discharged to the de-energization potential, and the reset operation of the shift register SRN is completed.

Through the above settings, the shift register SRN with automatic reset function can be completed.

The following paragraphs will be further combined with Figure 5 to provide specific details of the operation of the present invention.

Referring to FIG. 4 and FIG. 5 simultaneously, in the period D1, the input terminal IN receives an input voltage (ie, a scanning signal G(N-1) having a high voltage level). At this time, the transistor T6 is turned on and supplies an input voltage to the node BT to charge the node BT to a specific enable potential (for example, a high voltage level equal to the scan signal G(N-1)).

At this time, the transistor T5 is turned on according to the enable potential of the node BT to supply the supply voltage VSS to the node RST to turn off the transistor T1. The transistor T7 is turned on according to the enable potential of the node BT to provide the clock signal CK of the low voltage level to the output terminal OUT to turn off the transistor T2. The transistor T8 is turned on according to the enable potential of the node BT to supply the supply voltage VSS to the node B to turn off the transistors T4, T9, T10. The transistor T3 is turned off according to the low voltage level of the node A. The transistor T11 is turned on according to the clock signal XCK having a high voltage level.

In the period D2, when the pulse signal CK is switched from the low voltage level to the high voltage level, the potential of the node BT can be coupled to a higher operating potential to continuously turn on the transistor T7 to provide a high voltage level. The clock signal CK of the bit is output to the output terminal OUT as the output voltage (ie, the scanning signal G(N)).

At this time, the transistor T2 is turned on by receiving the output voltage of the output terminal OUT (ie, the high voltage level of the scanning signal G(N)) to provide an output voltage to the node A, so that the transistor T3 is turned on, and the transistor T3 is turned on. A clock signal XCK having a low voltage level is provided to the node RST. The transistor T5 is turned on according to the enable potential of the node BT to supply the supply voltage VSS to the node RST to turn off the transistor T1. The transistor T6 is turned off because the input terminal IN does not receive the input voltage (ie, receives the low voltage level). The transistor T8 is turned on according to the operating potential on the node BT to supply the supply voltage VSS to the node B to turn off the transistors T4, T9, T10. The transistor T11 is turned off according to the clock signal XCK having a low voltage level.

During the period D3, the clock signal XCK is switched from the low voltage level to the high voltage level to turn on the transistor T11 to supply the supply voltage VSS to the output terminal OUT, and to clear the output with the high voltage level on the output terminal OUT. Voltage (ie scan signal G(N)).

At this time, the transistor T2 is turned off according to the supply voltage VSS of the output terminal OUT.

In addition, when the pulse signal XCK is switched from the low voltage level to the high voltage level, the potential of the node A can be coupled to a higher operating potential to continuously turn on the transistor T3 to provide a high voltage level. The pulse signal XCK to the node RST is used as the reset voltage. The transistor T1 is turned on according to the reset voltage on the node RST to supply a supply voltage to the node BT to turn off the transistors T5, T7, T8. The transistors T4, T9, and T10 are turned off according to the clock signal CK having a low voltage level at point B. Transistor T6 is intercepted by the input terminal IN not receiving the input voltage (ie, receiving the signal of low voltage level) stop.

During the period D4, the clock signal XCK is switched from the high voltage level to the low voltage level to pull the potential of the node RST to a potential (for example, equal to the low voltage level of the clock signal XCK). The transistor T1 is turned off.

At this time, the transistor T4 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the node A to turn off the transistor T3. The transistor T9 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the node BT to stabilize the power of the node BT at the supply voltage VSS. The transistor T10 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the output terminal OUT to stabilize the power of the output terminal OUT at the supply voltage VSS. The transistors T5, T7, T8 are turned off according to the supply voltage VSS on the node BT. The transistor T2 is turned off according to the supply voltage VSS of the output terminal OUT. The transistor T11 is turned off according to the clock signal XCK having a low voltage level. The transistor T6 is turned off because the input terminal IN does not receive the input voltage (ie, the signal receiving the low voltage level).

In the period D5, the clock signal XCK is switched from the low voltage level to the high voltage level to couple the potential of the node RST to a higher operating potential to conduct the transistor T1 to enable the transistor T1 to supply the supply voltage VSS to The node BT is located at the supply voltage VSS to stabilize the node BT.

At this time, the transistors T5, T7, and T8 are turned off in accordance with the supply voltage VSS on the node BT. The transistors T4, T9, and T10 are turned off according to the clock signal CK having a low voltage level at point B. The transistor T11 is turned on according to the clock signal XCK having a low voltage level to provide the supply voltage VSS to the output terminal. OUT, to stabilize the output of the OUT terminal, is located at the supply voltage VSS. The transistor T2 is turned off according to the supply voltage VSS of the output terminal OUT. The transistor T6 is turned off because the input terminal IN does not receive the input voltage (ie, the signal receiving the low voltage level). The transistor T3 is turned off according to the supply voltage VSS on the node A.

In the period D6, the transistor T4 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the node A to stabilize the electric power of the transistor T3 at the supply voltage VSS. The transistor T9 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the node BT to stabilize the power of the node BT at the supply voltage VSS. The transistor T10 is turned on according to the clock signal CK having a high voltage level at the point B to supply the supply voltage VSS to the output terminal OUT to stabilize the power of the output terminal OUT at the supply voltage VSS. The transistors T5, T7, T8 are turned off according to the supply voltage VSS on the node BT. The transistor T2 is turned off according to the supply voltage VSS of the output terminal OUT. The transistor T11 is turned off according to the clock signal XCK having a low voltage level. The transistor T6 is turned off because the input terminal IN does not receive the input voltage (ie, the signal receiving the low voltage level).

It is noted that, through the above setting, the clock signal XCK can intermittently couple the potential of the node RST to a higher operating potential, so that the transistor T1 in the first reset circuit can be based on the clock signal XCK. The supply voltage VSS is intermittently supplied to the node BT to stabilize the potential of the node BT. For example, in the periods D3, D5, the transistor T1 continuously supplies the supply voltage VSS to the node BT.

In addition, it is also noted that, through the above arrangement, the transistor T1 in the first reset circuit 118 and the transistor T9 in the disable circuit 116 can be The supply voltage VSS is alternately supplied to the node BT according to the clock signals CK, XCK, respectively, to stabilize the potential of the node BT. For example, in the periods D3 and D5, the transistor T1 supplies the supply voltage VSS to the node BT according to the clock signal XCK, and in the periods D4 and D6, the transistor T9 supplies the supply voltage VSS to the node BT according to the clock signal CK.

Furthermore, the transistor T4 in the second reset circuit 120 can intermittently supply the supply voltage VSS to the node A according to the clock signal CK to stabilize the potential of the node A (please refer to the periods D4, D6). The transistors T10 and T11 in the de-energizing circuit 116 can alternately supply the supply voltage VSS to the output terminal OUT according to the clock signals CK and XCK to stabilize the potential of the output terminal OUT (refer to the period D3-D6).

By applying the above-described embodiment, the shift register SRN which is stable and has an automatic reset function can be realized. By applying the shift register SRN as the last stage shift register in the scan circuit 110, the scan circuit 110 does not need to provide an additional reset signal to the last stage shift register, thereby avoiding static electricity generation. Release phenomenon.

FIG. 6 is a schematic diagram of a scanning circuit 110a according to another embodiment of the invention. The scanning circuit 110a includes shift registers SR1a, . . . , SRNa in which a plurality of stages are electrically connected in series, wherein each of the shift registers SR1a, . . . , SRNa is shifted from that shown in FIG. 3A or FIG. The bit register SRN has the same structure and operation. That is, each of the shift registers SR1a, . . . , SRNa can be automatically reset without receiving an external reset signal. Therefore, each shift register SR1a, ..., SRNa does not receive the scan signals G(1), ..., G(N) from the next stage shift register.

In addition, the first reset circuit 118 and the disable circuit 116 of each of the shift registers SR1a, . . . , SRNa of the present embodiment alternately supply the supply voltage VSS to the node according to the clock signals CK and XCK, respectively. BT, to stabilize the potential of the node BT (please refer to the period D3-D6 in Figure 5). Therefore, the scanning circuit 110a of the present embodiment is more stable than the scanning circuit 110 shown in FIG.

It should be noted that in different embodiments, the shift register having the automatic reset function can be disposed at any one or more positions of the scan circuit according to actual needs, and is not limited to the above embodiment.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

SRN‧‧‧Shift register

112‧‧‧Input circuit

114‧‧‧Output circuit

116‧‧‧Disable circuit

118‧‧‧First reset circuit

120‧‧‧Second reset circuit

B‧‧‧ node

BT‧‧‧ node

RST‧‧‧ node

G(N-1), G(N)‧‧‧ scan signals

IN‧‧‧ input

OUT‧‧‧ output

CK‧‧‧ clock signal

XCK‧‧‧ clock signal

VSS‧‧‧ supply voltage

Claims (9)

A scanning circuit includes a plurality of shift registers, wherein the shift registers are electrically connected in series with each other, and at least one of the shift registers includes: an input circuit for receiving an input An input voltage is supplied to the first node; an output circuit is configured to receive a first clock signal and provide an output voltage according to the first clock signal and the potential of the first node And an output circuit for providing a supply voltage to the output terminal according to a second clock signal; a first reset circuit for providing a reset voltage according to a second node The supply voltage is applied to the first node; and a second reset circuit is configured to selectively provide the reset voltage according to the output voltage of the output terminal, the second clock signal, and the potential of the first node. The supply voltage is to the second node. The scanning circuit of claim 1, wherein when the second clock signal is a first voltage level and the second node has the reset voltage, the first reset circuit provides the supply voltage to The first node, and when the second clock signal is a second voltage level, the first reset circuit isolates a voltage source of the supply voltage from the first node. The scanning circuit of claim 1, wherein the first reset circuit And the de-energizing circuit alternately supplies the supply voltage to the first node. The scanning circuit of claim 1, wherein the second reset circuit comprises: a first transistor for providing the output voltage to a third node; and a second transistor for the third The potential of the node and the second clock signal provide the reset voltage to the second node. The scanning circuit of claim 4, wherein the second reset circuit is further configured to couple the potential of the third node to an operating potential according to the second clock signal, so that the second transistor is The operating potential is turned on. The scanning circuit of claim 4, wherein the second reset circuit further comprises: a third transistor for providing the supply voltage to the second node according to the potential of the first node. The scanning circuit of claim 4, wherein the second reset circuit further comprises: a fourth transistor for providing the supply voltage to the third node according to a potential of the fourth node. The scanning circuit of claim 7, wherein the de-energizing circuit comprises: a fifth transistor for supplying the supply voltage to the fourth node according to the potential of the first node; a sixth transistor for providing the supply voltage to the first according to the potential of the fourth node a seventh transistor, configured to provide the supply voltage to the output terminal according to the potential of the fourth node; an eighth transistor for providing the supply voltage to the output according to the second clock signal And a capacitor for transmitting the second clock signal to the fourth node. A shift register includes a first transistor, a first end, a second end, and a control end, wherein the first end of the first transistor and the control end of the first transistor Electrically connecting an input end, and the second end of the first transistor is electrically connected to a first node; a second transistor includes a first end, a second end, and a control end, wherein the first The first end of the second transistor is configured to receive a first clock signal, the second end of the second transistor is electrically connected to an output end, and the control end of the second transistor is electrically connected to the first end a third transistor, comprising a first end, a second end, and a control end, wherein the first end of the third transistor is electrically connected to the first node, the third transistor The second end is configured to receive a supply voltage, and the control end of the third transistor is electrically connected to a second node; a fourth transistor includes a first end, a second end, and a control The first end of the fourth transistor and the control end of the fourth transistor are electrically connected to the output end, and the second end of the fourth transistor is electrically connected to a third node; The fifth transistor includes a first end, a second end, and a control end, wherein the first end of the fifth transistor is configured to receive a second clock signal, and the second end of the fifth transistor The second terminal is electrically connected to the second node, and the control terminal of the fifth transistor is electrically connected to the third node; a sixth transistor includes a first end, a second end, and a control end, wherein the The first end of the sixth transistor is electrically connected to the third node, the second end of the sixth transistor is configured to receive the supply voltage, and the control end of the sixth transistor is electrically connected to a fourth a seventh transistor includes a first end, a second end, and a control end, wherein the first end of the seventh transistor is electrically connected to the second node, and the seventh transistor The second end is configured to receive the supply voltage, and the control end of the seventh transistor is electrically connected to the first node An eighth transistor includes a first end, a second end, and a control end, wherein the first end of the eighth transistor is electrically connected to the fourth node, and the second end of the eighth transistor Receiving the supply voltage, and the control end of the eighth transistor is electrically connected to the first node; a ninth transistor includes a first end, a second end, and a control end, wherein the ninth The first end of the ninth transistor is electrically connected to the first node, and the second end of the ninth transistor is electrically connected to the fourth node; a tenth transistor comprising a first end, a second end, and a control The first end of the tenth transistor is electrically connected to the output end, the second end of the tenth transistor is configured to receive the supply voltage, and the control end of the tenth transistor is electrically connected The fourth node; and an eleventh transistor, comprising a first end, a second end, and a control end, wherein the first end of the eleventh transistor is electrically connected to the output end, the tenth The second end of the transistor is configured to receive the supply voltage, and the control end of the eleventh transistor is configured to receive the second clock signal; and a capacitor includes a first end and a second end The first end of the capacitor is configured to receive the second clock signal, and the second end of the capacitor is electrically connected to the fourth node.